JP2855999B2 - Automatic generation of test input sequence using hardware simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically generating a test input sequence, in particular, by setting an input value to an undefined input bit string, performing a failure simulation, and performing backtracking when no failure is found, thereby performing detection. The present invention relates to an automatic generation method of a test input sequence for improving a rate.

[0002]

2. Description of the Related Art Conventionally, after a random input value is set to an undefined input bit string, a concurrent fault simulation is performed to obtain a fault detection rate. For the concurrent failure simulation, see Kinoshita and Fujiwara, "Diagnosis of Digital Circuit Failure (Part 1)", Engineering Books, 1983.

[0003]

In the above-described conventional automatic generation method of the test input sequence, the first input bit is given a value at random. For this reason, there has been a problem that the detection rate cannot be efficiently improved by setting the required value as feedback from the initial setting.

[0004]

According to a first aspect of the present invention, there is provided a first operation unit which is a target of failure detection in a processor first.
An initial target setting unit for generating a failure detection request of
Receiving the failure detection request and the second failure detection request, the value of a value to be set so that a failure is found from the failure list of the operation unit on the fan-in side, which is the direction of the input bit string of the operation unit in which the failure is set. A node setting request unit that outputs a setting request, and a multiplex backward propagation unit that propagates the setting value of the node setting request unit to all the fan-in side operation units connected to the 'undefined' input of the operation unit. ,
A request setting unit that requests the input bit sequence to set the set value propagated by the multiple backward propagation unit and reaches the input bit sequence; and inputs the requested value in response to the input bit sequence setting request and the input bit sequence addition request. An input setting unit that sets a predetermined bit in a bit string, a simulation unit that performs a concurrent failure simulation based on the input value set in the input bit string, and a failure simulated by the simulation unit. An end setting unit for determining whether or not to end the operation, an input setting update unit for changing an input value set in the input bit string when the end judgment unit determines that the operation is not to be ended, and the input when the failure is found. An input bit fixing unit for making an input value set in a bit string unchangeable; An input addition instruction unit that outputs the input bit string addition request to add an input to another unset input bit string according to an instruction from a bit fixing unit, and a value of the failure list output of the operation unit by the failure simulation And a D frontier recognizing unit that outputs the second failure detection request when is "undefined".

A second invention provides a processor unit target selection unit for uniformly selecting one or more calculation units of an initial target failure initially targeted by a plurality of processors performing parallel processing to each processor, And an initial target setting unit for generating a first failure detection request for the calculated operation unit.

[0006]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the first invention. First, one fault to be detected is determined (hereinafter referred to as an initial target fault), and a request for detecting a target fault is generated. The initial target setting unit 12 receives a detection request output from the initial target setting unit 12, and sets a value to be set as an operation unit in the direction of the input bit string 7 (fan-in side) from the operation unit in which the failure is set. And a multiplex that propagates the setting request issued from the node setting request unit 9 to all the fan-in side operation units connected to the “undefined” input of the operation unit. Back propagation unit 10,
Further, the input bit string 7
Setting unit 11 for requesting the input bit string 7 to set the requested value that has arrived at the input setting unit 11 and setting the value requested by the request setting unit 11 to the input bit string 7 several bits at a time.
A simulation unit 2 for performing a concurrent failure simulation from an input value set in the input setting unit 1;
As a result of the simulation performed by the simulation unit 2,
If no failure is found, an end determination unit 3 that determines whether or not to end the operation, and when the end determination unit 3 determines that the operation is not to be ended, the input value set so far is changed (hereinafter referred to as a backtrack). An input setting updating unit 4; an input bit fixing unit 5 that makes it impossible to change the input bit string 7 set so far when a failure is found; and an input setting unit that adds an input to another unset input bit string 7 The input addition instructing unit 6 and the simulation unit 2 perform concurrent failure simulation for each operation unit, and the normal output result is different from the output result at the time of the failure list operation. When the value is “undefined”, it recognizes that there is an “undefined” input in this operation unit, and notifies the node setting request unit 9 of the presence of the D frontier and generates a setting request. And an ear recognition unit 8.

An operation example of the present invention will be described with reference to FIG. 1 and a flowchart of FIG. 1. The initial target setting unit 12 sets the failure to be detected as 1
Once determined (hereinafter referred to as an initial target failure), a request for detection of a target failure is generated and notified to the node setting request unit 9.

[0009] 2. The node setting request unit 9 calculates what kind of input is the calculation unit notified from the initial target setting unit 12 and determines whether the failure list output is not “undefined” and becomes an output in which a failure is found, and calculates the input value for that. A request is made to the multiplex backward propagation unit 10 to have the operation unit set.

[0010] 3. If the operation unit notified from the node setting request unit 9 is not the input bit string 7, the multiplex backward propagation unit 10 sets the input value to be set to the fan-in side for all inputs for which the notified operation unit setting request is issued. Request (called a request value). Thereafter, an input value (new required value) for outputting a required value for the fan-in side operation unit is calculated and requested to the fan-in side.

4. If there is a request value reaching the input bit string 7 in the multiplex backward propagation section 10, the request setting section 11 is notified.

5. The request setting unit 11 sets the request value notified from the multiplex backward propagation unit 10 to the requested bit position when adding a value to the input bit string 7.
Notify.

6. The input setting unit 1 determines whether the input setting is possible (101), and since it can be set at the start, sets the request value notified from the request setting unit 11 and notifies the simulation unit 2 (103). 7. If the input setting unit 1 has already set the input to all of the input bit strings 7 and cannot set the input (101)
After the current input bit sequence is registered as a test input sequence and the input bit sequence 7 is initialized (102), the requested input value is set in the input bit sequence 7 and notified to the simulation unit 2 (103).

8. After being notified, the simulation unit 2 performs a concurrent failure simulation using the input bit string 7 as an input. At this time, the D frontier recognizing unit 8 is operated after the operation for each operation unit is completed.

9. After the completion of the concurrent failure simulation operation for each operation unit, the D frontier recognizing unit 8 checks whether a failure list has occurred in the operation unit and whether the operation result of the failure list is “undefined”, and satisfies the condition. If so, the node setting request unit 9 is notified.

10. After the simulation is performed, the end determination unit 3 notifies the input bit fixing unit 5 if there is a detected failure, and if there is no detected failure and the specified detection rate has not been reached, the input setting update unit 4 performs backtracking. Notice. If the specified detection rate has been reached, the execution ends.

11. When notified from the end determination unit 3, the input bit fixing unit 5 fixes the input set value of the input bit currently set in the input bit string 7, and sets the input setting update unit 4.
So that updates by After that, the input addition instructing unit 6 is notified.

[12] The input addition instructing unit 6 includes the input setting unit 1
Instructs to set the addition to input bits that have not yet been set. (Return to 6.) When notified from the end determination unit 3, the input setting update unit 4 changes the input set value of the input bit currently set in the input bit string 7 and notifies the simulation unit 2 of the change.

14. The node setting request unit 9 calculates what kind of input value is required for the fault list output of the calculation unit notified from the D frontier recognizing unit 8 to be an output in which a fault is found instead of “undefined”, and the input value is calculated. Is notified to the multiplex backward propagation unit 10 so as to be set as the operation unit.

15. If the operation unit notified from the node setting request unit 9 is not the input bit string 7, the multiplex backward propagation unit 10 requests input values to be set on the fan-in side for all inputs for which the notified operation unit setting request is issued. (Called a required value). Thereafter, an input value (new required value) for outputting a required value for the fan-in side operation unit is calculated and requested to the fan-in side.

16. If there is a request value that has reached the input bit string 7 in the multiplex backward propagation unit 10, the request setting unit 11 is notified.

17. If there is a request value notified from the multiplex backward propagation unit 10, the request setting unit 11 sets the input value so that when the input setting unit 1 adds a value to the input bit string 7, the request value is set to the requested bit position. Part 1 is notified.

FIG. 3 is a block diagram of an embodiment of the second invention, in which a processor unit for uniformly selecting one or more faults to be detected first (hereinafter referred to as initial target faults) equally for each processor. A target selecting unit 14, an initial target setting unit 13 that generates a request for detecting each initial target failure notified by the processor unit target selecting unit 14, and an initial target setting unit 1
A node setting request unit 9 for receiving a detection request output from the node 3 and requesting to set a value to be set in the operation unit in the direction of the input bit string 7 (fan-in side) from the operation unit in which the fault is set. A multi-back propagation unit 10 for propagating the setting request issued from the node setting request unit 9 to all the operation units on the fan-in side connected to the "undefined" input of the operation unit; A request setting unit 11 for requesting the input bit string 7 to set a request value that has been propagated and reaching the input bit string 7, and an input setting unit 1 for setting the value requested by the request setting unit 11 to the input bit string 7 several bits at a time. And a simulation unit 2 for performing a concurrent failure simulation based on the input value set in the input setting unit 1. If none is found, an end determination unit 3 that determines whether to end, and an input setting update unit that changes the input value set up to now (hereinafter referred to as backtrack) when the end determination unit 3 determines that the operation is not to end. 4, an input bit fixing unit 5 for making the input bit string 7 set so far unchangeable when a failure is found, and an input setting unit 1 to instruct the input setting unit 1 to add an input to another unset input bit string 7. In the input addition instructing unit 6 and the simulation unit 2, when a concurrent failure simulation is performed for each operation unit, the normal output result is different from the output result at the time of the failure list operation, and the value at the time of the failure list operation is “undefined”,
A D frontier recognizing unit 8 that recognizes that there is an “undefined” input in this operation unit, notifies the node setting requesting unit 9 of the presence of the D frontier, and generates a setting request.

Next, an operation example of the present invention will be described with reference to FIG. 3 and a flowchart of FIG.

1. First, the processor unit target selection unit 14
Selects uniformly one or more initial target faults to be detected by each processor performing the parallel processing. 1. The following processing is performed in each processor. The initial target setting unit 13 generates a detection request for an initial target failure assigned to the processor by the processor unit target selection unit 14 and notifies the node setting request unit 9 of the request.

3. The node setting request unit 9 calculates what kind of input the calculation unit notified from the initial target setting unit 13 is, and outputs a fault list output that is not “undefined” and a fault is found, and calculates an input value for that. A request is made to the multiplex backward propagation unit 10 to have the operation unit set.

4. If the operation unit notified from the node setting request unit 9 is not the input bit string 7, the multiplex backward propagation unit 10 requests input values to be set on the fan-in side for all inputs for which the notified operation unit setting request is issued. (Called a required value). Thereafter, an input value (new required value) for outputting a required value for the fan-in side operation unit is calculated and requested to the fan-in side.

5. If there is a request value that has reached the input bit string 7 in the multiplex backward propagation unit 10, the request setting unit 11 is notified.

6. The request setting unit 11 notifies the input setting unit 1 of setting the request value notified by the multiplex backward propagation unit 10 at the requested bit position when adding a value to the input bit string 7.

[7] The input setting unit 1 determines whether the input setting is possible (101), and since it can be set at the start, sets the request value notified from the request setting unit 11 and notifies the simulation unit 2 (103). 8. If the input setting unit 1 has already set the input to all of the input bit strings 7 and cannot set the input (101)
After the current input bit sequence is registered as a test input sequence and the input bit sequence 7 is initialized (102), the requested input value is set in the input bit sequence 7 and notified to the simulation unit 2 (103).

9. After being notified, the simulation unit 2 performs a concurrent failure simulation using the input bit string 7 as an input. At this time, after the end of the operation for each operation unit,
The D frontier recognition unit 8 is operated.

10. After the completion of the concurrent failure simulation operation for each operation unit, the D frontier recognizing unit 8 checks whether a failure list has occurred in the operation unit and whether the operation result of the failure list is “undefined”, and satisfies the condition. If so, the node setting request unit 9 is notified.

11. After the simulation is performed, the end determination unit 3 notifies the input bit fixing unit 5 if there is a detection failure. If there is no detection failure and the designated detection rate has not been reached, the input setting updating unit 4 is notified to perform backtracking. If the specified detection rate has been reached, the execution ends.

12. When notified from the end determination unit 3, the input bit fixing unit 5 fixes the input set value of the input bit currently set in the input bit string 7, and sets the input setting update unit 4.
So that updates by After that, the input addition instructing unit 6 is notified.

13. The force addition instructing unit 6 instructs the input setting unit 1 to set addition to an input bit that has not been set yet. (Return to 7.) When notified from the end determination unit 3, the input setting update unit 4 changes the input set value of the input bit currently set in the input bit string 7 and notifies the simulation unit 2 of the change.

15. The node setting request unit 9 calculates what kind of input value is required for the fault list output of the calculation unit notified from the D frontier recognizing unit 8 to be an output in which a fault is found instead of “undefined”, and the input value is calculated. Is notified to the multiplex backward propagation unit 10 so as to be set as the operation unit.

16. If the operation unit notified from the node setting request unit 9 is not the input bit string 7, the multiplex backward propagation unit 10 sets the input value to be set to the fan-in side for all inputs for which the notified operation unit setting request is issued. Request.
Thereafter, an input value (new required value) for outputting a required value is calculated for the fan-in side calculation unit, and a request is made to the fan-in side.

17. If there is a request value that has reached the input bit string 7 in the multiplex backward propagation unit 10, the request setting unit 11 is notified.

18. If there is a request value notified from the multiplex backward propagation unit 10, the request setting unit 11 sets the input value so that when the input setting unit 1 adds a value to the input bit string 7, the request value is set to the requested bit position. Part 1 is notified.

[0040]

As described above, the first aspect of the present invention has the effect of generating a high-quality pattern with a large number of faults to be found, since the input value is always determined not by random but by a required value. Further, the second invention has an effect that a high-quality pattern can be generated in a short time by performing parallel execution for many failures in addition to the first invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the first invention.

FIG. 2 is a flowchart inside an input setting unit of the embodiment.

FIG. 3 is a block diagram showing one embodiment of the second invention.

[Description of Signs] 1 input setting unit 2 simulation unit 3 end determination unit 4 input setting updating unit 5 input bit fixing unit 6 input addition instructing unit 7 input bit string 8 D frontier recognition unit 9 node setting request unit 10 multiplex backward propagation unit 11 Requirement setting unit 12, 13 Initial target setting unit 14 Processor unit target selection unit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28 G06F 11/25 G06F 17/50

Claims (2)

(57) [Claims] An initial target setting unit for first generating a first failure detection request of an operation unit targeted for failure detection in the processor; receiving the first failure detection request and the second failure detection request; A node setting request unit that outputs a request for setting a value to be set so that a failure is found from the failure list of the operation unit to the fan-in side, which is the direction of the input bit string of the operation unit in which the failure is set, and the node setting A multiplex back propagation unit that propagates the setting value of the request unit to all the operation units on the fan-in side connected to the 'undefined' input of the operation unit; A request setting unit for requesting the input bit string to set the set value, and receiving the input bit string setting request and the input bit string addition request to set the requested value to the input bit string. An input setting unit for setting a predetermined bit at a time, a simulation unit for performing a concurrent failure simulation based on an input value set for the input bit string, and if no failure is found as a result of simulation by the simulation unit. An end determination unit for determining whether or not to end, an input setting updating unit for changing an input value set in the input bit string when the end determination unit determines that the processing is not to be ended, and the input bit string when the failure is found An input bit fixing unit for making the input value set to be unchangeable, and an input for outputting the input bit string addition request so as to add an input to another unset input bit string according to an instruction from the input bit fixing unit An additional instructing unit, wherein the value of the fault list output of the operation unit by the fault simulation is An automatic generation method of a test input sequence using a hardware simulator, comprising: a D frontier recognizing unit that outputs the second failure detection request when “undefined”. 2. A processor unit target selection section for uniformly selecting one or more operation units of an initial target failure initially targeted by a plurality of processors performing parallel processing for each processor, and the selected operation units. The method according to claim 1, further comprising the initial target setting unit configured to generate a first failure detection request.