JP2592682B2 - Low temperature etching equipment for semiconductor devices - Google Patents
Low temperature etching equipment for semiconductor devicesInfo
- Publication number
- JP2592682B2 JP2592682B2 JP23723589A JP23723589A JP2592682B2 JP 2592682 B2 JP2592682 B2 JP 2592682B2 JP 23723589 A JP23723589 A JP 23723589A JP 23723589 A JP23723589 A JP 23723589A JP 2592682 B2 JP2592682 B2 JP 2592682B2
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- chamber
- semiconductor substrate
- low
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 238000005530 etching Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims description 29
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 8
- 238000001816 cooling Methods 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000012805 post-processing Methods 0.000 description 8
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007710 freezing Methods 0.000 description 1
- 230000008014 freezing Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、半導体装置の低温エッチング装置に関す
る。The present invention relates to a low-temperature etching apparatus for a semiconductor device.
（従来の技術） 近年、半導体装置のエッチング装置では半導体基板を
氷点下に保ったままエッチング（低温エッチング）する
装置が利用されつつある。(Prior Art) In recent years, as an etching apparatus for a semiconductor device, an apparatus for performing etching (low-temperature etching) while keeping a semiconductor substrate below freezing has been used.
第２図は従来のアルミニウム（Al）合金膜の低温エッ
チング装置の説明図であって、11はエッチング室、12は
後処理室、13は搬送室、14は半導体基板の受け体、15は
半導体基板の移送部である。FIG. 2 is an explanatory view of a conventional low-temperature etching apparatus for an aluminum (Al) alloy film, in which 11 is an etching chamber, 12 is a post-processing chamber, 13 is a transfer chamber, 14 is a semiconductor substrate receiver, and 15 is a semiconductor. This is a substrate transfer unit.
同図において、エッチング室11において半導体基板
（図示せず）の温度を−10℃に保ち、Al合金膜の低温エ
ッチングを行う。この低温エッチングではエッチング反
応生成物（AlCl3）が揮発化せずにAl合金膜の側壁を保
護するため、異方性エッチングを実現することができ
る。In the figure, the temperature of a semiconductor substrate (not shown) is kept at −10 ° C. in an etching chamber 11, and the Al alloy film is etched at a low temperature. This low-temperature etching protects the side wall of the Al alloy film without volatilizing the etching reaction product (AlCl 3 ), so that anisotropic etching can be realized.
次に半導体基板は、搬送室13,移送部15を経て、後処
理室12に移送され、酸素プラズマによりレジストや残留
塩素の除去処理が施される。この際、前記反応生成物
（AlCl3）中に含まれている塩素を容易に除去できるよ
うに、半導体基板の温度は＋250℃に保たれる。Next, the semiconductor substrate is transferred to the post-processing chamber 12 via the transfer chamber 13 and the transfer section 15, and subjected to a process of removing resist and residual chlorine by oxygen plasma. At this time, the temperature of the semiconductor substrate is kept at + 250 ° C. so that chlorine contained in the reaction product (AlCl 3 ) can be easily removed.
（発明が解決しようとする課題） しかしながら、上記の従来技術では、半導体基板の温
度は−10℃から＋250℃に急激に変化するので、半導体
基板や、その上に形成された配線、絶縁膜に、熱膨脹係
数の差によるストレスが加わり、結晶欠陥や配線の断
線、あるいは浮き上りが発生するという問題があった。(Problems to be Solved by the Invention) However, in the above-described conventional technology, the temperature of the semiconductor substrate rapidly changes from −10 ° C. to + 250 ° C., so that the semiconductor substrate, the wiring formed thereon, and the insulating film are hardly formed. In addition, there is a problem that stress due to a difference in thermal expansion coefficient is applied, and crystal defects, disconnection of wiring, or floating occur.
さらに後処理室12では最初に半導体基板の温度が上昇
するまでレジストや残留塩素の除去処理が行われず、装
置の制御性に支障をきたしていた。Further, in the post-processing chamber 12, the resist and the residual chlorine are not removed until the temperature of the semiconductor substrate first rises, which hinders the controllability of the apparatus.
本発明の目的は、半導体基板の損傷を低減し、しか
も、エッチング処理の制御性の向上が図れる半導体装置
の低温エッチング装置を提供することにある。An object of the present invention is to provide a low-temperature etching apparatus for a semiconductor device which can reduce damage to a semiconductor substrate and improve controllability of an etching process.
（課題を解決するための手段） 上記の目的を達成するため、本発明は、複数の反応室
を有する半導体装置の低温エッチング装置において、前
記反応室の処理温度がそれぞれ異なり、前記反応室の間
に、一方の反応室の処理温度から他方の反応室の処理温
度まで処理対象の半導体基板の温度を昇降させるために
温度制御ができ、しかも熱容量が前記反応室よりも小さ
い真空室を備えたことを特徴とする。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a low-temperature etching apparatus for a semiconductor device having a plurality of reaction chambers, wherein the processing temperatures of the reaction chambers are different from each other. In addition, a vacuum chamber having temperature control capable of raising and lowering the temperature of the semiconductor substrate to be processed from the processing temperature of one reaction chamber to the processing temperature of the other reaction chamber and having a smaller heat capacity than the reaction chamber is provided. It is characterized by.
（作 用） 上記手段を採用したため、真空室において、半導体基
板は次の反応室に移送される前に温度制御されるので、
熱膨脹係数の差による半導体基板の損傷を回避でき、さ
らに次の反応室に移送される前に半導体基板の温度を所
定の温度に制御できるので、後処理の制御性の向上が図
れ、しかも真空室の熱容量が小さいため昇温および降温
の変化速度が速いので、温度変化を容易に制御すること
ができる。(Operation) Since the above means is adopted, the temperature of the semiconductor substrate is controlled in the vacuum chamber before being transferred to the next reaction chamber.
The semiconductor substrate can be prevented from being damaged due to the difference in thermal expansion coefficient, and the temperature of the semiconductor substrate can be controlled to a predetermined temperature before being transferred to the next reaction chamber. Because of its small heat capacity, the rate of change in temperature increase and decrease is fast, so that temperature change can be easily controlled.
（実施例） 以下、本発明の実施例を図面に基づいて説明する。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明の半導体装置の低温エッチング装置を
Al合金膜の形成装置に適用した一実施例を示す説明図で
あって、１と２は反応室であって、それぞれエッチング
室と後処理室、３は半導体基板（図示せず）の受け体、
４は搬送室を兼ねたAlからなる真空室、５は加熱用のラ
ンプヒータ、６は冷却用の窒素導入路、７は半導体基板
の移送部である。FIG. 1 shows a low-temperature etching apparatus for a semiconductor device according to the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view showing one embodiment applied to an apparatus for forming an Al alloy film, wherein 1 and 2 are reaction chambers, respectively an etching chamber and a post-processing chamber, and 3 is a receiver for a semiconductor substrate (not shown). ,
Reference numeral 4 denotes a vacuum chamber made of Al also serving as a transfer chamber, 5 denotes a lamp heater for heating, 6 denotes a nitrogen introduction path for cooling, and 7 denotes a semiconductor substrate transfer section.
同図において、半導体基板の移送部７は、エッチング
室１では第２図で説明した公知の処理が施され、次に冷
却用の窒素によって予め−10℃に温度制御されている真
空室４に移送され、ランプヒータ５によって十分長い時
間（５分程度）をかけて＋250℃まで昇温される。この
後、半導体基板は後処理室２に移送されて、第２図で説
明した公知の処理が施される。In the figure, a transfer section 7 for a semiconductor substrate is transferred to a vacuum chamber 4 which has been subjected to the known processing described in FIG. 2 in an etching chamber 1 and then temperature-controlled to −10 ° C. in advance by cooling nitrogen. After being transported, the temperature is raised to + 250 ° C. by the lamp heater 5 over a sufficiently long time (about 5 minutes). Thereafter, the semiconductor substrate is transferred to the post-processing chamber 2 and subjected to the known processing described with reference to FIG.
また前記真空室４は半導体基板が後処理室２に移送さ
れた後、次の半導体基板に備えて再び冷却用の窒素によ
って予め−10℃に降温させられる。真空室４は容易に昇
温または降温できるように熱容量の小さなAlなどで構成
されている。After the semiconductor substrate is transferred to the post-processing chamber 2, the vacuum chamber 4 is cooled down to −10 ° C. again by nitrogen for cooling in preparation for the next semiconductor substrate. The vacuum chamber 4 is made of aluminum or the like having a small heat capacity so that the temperature can be easily raised or lowered.
また移送部７は各反応室1,2と真空室４を断熱するた
めに熱容量の大きなセラミックスなどで構成されてい
る。The transfer section 7 is made of ceramics having a large heat capacity to insulate the reaction chambers 1 and 2 and the vacuum chamber 4 from each other.
以上のように本実施例によれば、反応室1,2の間に半
導体基板の温度を制御できる真空室４を備えたことによ
り、半導体基板は冷却用の窒素と加熱用のランプヒータ
５によって十分に長い時間をかけて−10℃から250℃ま
で昇温されるので、熱膨脹係数の差による半導体基板の
損傷を防止できる。さらに半導体基板の温度は後処理室
２に入る前に、既に真空室４で250℃まで上昇されてい
るので後処理の制御性を向上させることができる。As described above, according to the present embodiment, by providing the vacuum chamber 4 that can control the temperature of the semiconductor substrate between the reaction chambers 1 and 2, the semiconductor substrate is cooled by the nitrogen for cooling and the lamp heater 5 for heating. Since the temperature is raised from −10 ° C. to 250 ° C. over a sufficiently long time, damage to the semiconductor substrate due to a difference in thermal expansion coefficient can be prevented. Further, since the temperature of the semiconductor substrate has already been raised to 250 ° C. in the vacuum chamber 4 before entering the post-processing chamber 2, the controllability of the post-processing can be improved.
また窒素以外の不活性ガスを真空室４に導入して、上
記の温度制御を行ってもよく、さらに受け体３を窒素や
不活性ガスで冷却することで温度制御を行うことも考え
られる。The above-described temperature control may be performed by introducing an inert gas other than nitrogen into the vacuum chamber 4, and the temperature control may be performed by cooling the receiver 3 with nitrogen or an inert gas.
なお、上記の実施例ではAl合金膜の低温エッチング装
置の例を示したが、多結晶シリコン膜や高融点シリサイ
ド膜などのエッチングの場合にも利用できる。In the above embodiment, an example of a low-temperature etching apparatus for an Al alloy film has been described, but the present invention can also be used for etching a polycrystalline silicon film or a high melting point silicide film.
また真空室４は反応室の１種としても利用できる。 The vacuum chamber 4 can also be used as one type of a reaction chamber.
（発明の効果） 本発明によれば、反応室の間に半導体基板の温度を制
御できる真空室を備えたことにより、半導体基板の損傷
を低減でき、温度制御を含むエッチング処理の制御が高
精度かつ容易に行える半導体装置の低温エッチング装置
を提供できる。(Effect of the Invention) According to the present invention, by providing a vacuum chamber between the reaction chambers for controlling the temperature of the semiconductor substrate, damage to the semiconductor substrate can be reduced, and the control of the etching process including the temperature control can be performed with high precision. A low-temperature etching apparatus for a semiconductor device that can be easily performed can be provided.
第１図は本発明による半導体装置の低温エッチング装置
の一実施例を示す説明図、第２図は従来の半導体装置の
低温エッチング装置を示す説明図である。 1,2……反応室、３……受け体、４……真空室、５……
ランプヒータ、６……窒素導入路、７……移送部。FIG. 1 is an explanatory view showing one embodiment of a low-temperature etching apparatus for a semiconductor device according to the present invention, and FIG. 2 is an explanatory view showing a conventional low-temperature etching apparatus for a semiconductor device. 1,2 ... reaction chamber, 3 ... receiver, 4 ... vacuum chamber, 5 ...
Lamp heater 6 Nitrogen introduction path 7 Transfer section
Claims (4)
ッチング装置において、前記反応室の処理温度がそれぞ
れ異なり、前記反応室の間に、一方の反応室の処理温度
から他方の反応室の処理温度まで処理対象の半導体基板
の温度を昇降させるために温度制御ができ、しかも熱容
量が前記反応室よりも小さい真空室を備えたことを特徴
とする半導体装置の低温エッチング装置。1. A low-temperature etching apparatus for a semiconductor device having a plurality of reaction chambers, wherein the processing temperatures of the reaction chambers are different from each other, and the processing temperature of one reaction chamber is reduced from the processing temperature of the other reaction chamber between the reaction chambers. A low-temperature etching apparatus for a semiconductor device, comprising: a vacuum chamber capable of controlling the temperature of a semiconductor substrate to be processed up to a temperature and having a heat capacity smaller than that of the reaction chamber.
のための搬送室を兼ねることを特徴とする請求項（１）
記載の半導体装置の低温エッチング装置。2. The semiconductor device according to claim 1, wherein said vacuum chamber doubles as a transfer chamber for transferring a semiconductor substrate between reaction chambers.
A low-temperature etching apparatus for a semiconductor device as described in the above.
する請求項（１）記載の半導体装置の低温エッチング装
置。3. The low-temperature etching apparatus for a semiconductor device according to claim 1, wherein said vacuum chamber doubles as a reaction chamber.
るいは窒素や不活性ガスの真空室への導入、または窒素
や不活性ガスによる半導体基板の受け体の冷却によって
行うことを特徴とする請求項（１）記載の半導体装置の
低温エッチング装置。4. The temperature control in the vacuum chamber is performed by heating a lamp, introducing nitrogen or an inert gas into the vacuum chamber, or cooling a semiconductor substrate receiver with nitrogen or an inert gas. A low-temperature etching apparatus for a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23723589A JP2592682B2 (en) | 1989-09-14 | 1989-09-14 | Low temperature etching equipment for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23723589A JP2592682B2 (en) | 1989-09-14 | 1989-09-14 | Low temperature etching equipment for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03101224A JPH03101224A (en) | 1991-04-26 |
| JP2592682B2 true JP2592682B2 (en) | 1997-03-19 |
Family
ID=17012391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23723589A Expired - Fee Related JP2592682B2 (en) | 1989-09-14 | 1989-09-14 | Low temperature etching equipment for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2592682B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970003600A (en) * | 1995-06-29 | 1997-01-28 | 김주용 | Low Temperature Etching Method |
| KR102554014B1 (en) * | 2018-06-15 | 2023-07-11 | 삼성전자주식회사 | Method of etching in low temperature and plasma etching apparatus |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6027129A (en) * | 1983-07-25 | 1985-02-12 | Mitsubishi Electric Corp | Method for annealing metallic film wiring |
| JPS62193099A (en) * | 1986-02-20 | 1987-08-24 | 富士通株式会社 | Vacuum chamber |
| JP2585277B2 (en) * | 1987-07-17 | 1997-02-26 | 株式会社日立製作所 | Surface treatment equipment |
-
1989
- 1989-09-14 JP JP23723589A patent/JP2592682B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03101224A (en) | 1991-04-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |