JP2652993B2 - Counting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counting circuit.
The present invention relates to a counting circuit that independently counts a plurality of independent status signals in a reference frame.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional counting circuit of this type uses, as an example, a data signal in which three independent status signals are multiplexed in one frame. The signal generator 61 includes a series of the unit 31, the output circuit 51, a series of the input circuit 12, the counting unit 32, and the output circuit 52, and a series of the input circuit 13, the counting unit 33, and the output circuit 53. It is configured. As shown in FIG. 2, the input channel status data signal D1 includes the status signals A1, B1, and C1 of the first, second, and third channels in one frame, and the first, second, and second status signals in the next frame. Status signals A2, B2, and C2 of three channels are arranged.

Next, the operation of the conventional example will be described with reference to FIG.
The status signal A1 in the channel status data signal D1 in which three independent status signals are multiplexed in one frame is supplied to the input circuit 11, and the status signal B
1 to the input circuit 12, and the status signal C1 to the input circuit 1.
3, a control signal SC1 indicating the head of a status signal generated by the signal generator 61 by the frame reference signal SR;
SC2, SC3 and status signal DS
1 to the counter 31 and the status signal DS2 to the counter 32
, The status signal DS3 is input to the counting unit 33. Further, the counting units 31, 3 according to the control signals SCK1, SCK2, SCK3 instructing the counting generated by the signal generator 61.
At 2 and 33, the status signals are counted, and the counting section information DC1 is input to the output circuit section 51, the counting section information DC2 is input to the output circuit 52, and the counting section information DC3 is input to the output circuit section 53. Further, control signals SCO1 and SCO2 for instructing each channel output generated by the signal generator 61, and the counting result DO
2. The counting result DO3 is output.

[0004]

In the conventional counting circuit described above, one input circuit is provided for each one of a plurality of status signals in one frame.
Since a counting unit and an output circuit are required, and the number of input control signals, count control signals, and output control signals generated by the signal generator are required as many as the number of status signals,
When there are a plurality of status signals, there are disadvantages that the circuit scale increases and control by a signal generator becomes complicated.

It is an object of the present invention to provide a counting circuit which avoids an increase in circuit scale even if the number of status signals increases, and which prevents an increase in control signals by a signal generator.

[0006] Multiplexed to each frame arranged in time series
At the beginning of input data signals of multiple channels
Status data signals such as parity bits
A storage unit for storing the data as independent data in the channel;
Input the input data signal and start each channel from the outside.
As the starting point, the status data signal of each channel is set to 1
Input circuit output as a unit and read signal from outside
One frame before the current time stored in the storage unit
The status data signal of the corresponding channel of (D)
TA0) from the input circuit after reading
Input status data signal (A1) and input external coefficient
In response to the instruction signal, the status data signal (DTA0)
(DTA0) and the status data signal (A1)
+ A1 = DTA1) is transferred to the storage circuit
Counting section, and a data bus signal from outside,
Transfer of count data between the storage unit and the counting unit and for each channel
A selection circuit for outputting the operation data, Ji from outside
An output circuit that outputs the operation data transferred from the storage circuit via the selection circuit in parallel by a channel instruction signal, and each of the input circuit, the counting unit, the storage unit, the selection circuit, and the output circuit And a signal generating means for transmitting the external control signal for controlling at a predetermined timing.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the embodiment. Here, a description will be given of a circuit for independently counting status signals in a data signal in which three independent status signals are multiplexed in one frame as shown in FIG.

In the embodiment shown in FIG. 1, a channel status signal DI in which statuses to be counted are multiplexed in a time series in one frame is input, and status data for each channel is extracted by a control signal described later. An input circuit 1 for sequentially outputting, a counting unit 3 for counting the output status data in a procedure described later, a storage circuit 2 for storing the counting data of the counting unit 3 for each channel, and a counting unit 3 and a storage circuit 2. A selection circuit 4 also serving as a data bus for transmitting and receiving data during a predetermined procedure, an output circuit 5 for outputting a counting result by an instruction signal according to a channel order, the input circuit 1, the counting section 3, and a storage circuit 2 described above. , A selection circuit 4 and an output circuit 5 each comprising a signal generator 6 for outputting an instruction signal in accordance with a predetermined procedure and timing.

Next, the operation of this embodiment will be described with reference to FIG. First, assuming that the status data signals of three channels in one frame are A1, B1, and C1 as described above, the processing of the status signal A1 will be described. In the next frame, status data A of the same channel
2, B2 and C2 are sequentially arranged. When the signal generator 6 externally inputs a frame reference signal SR indicating the beginning of a frame, a built-in clock counter starts the three-channel pulse signal S starting from the frame reference signal SR.
C is generated and supplied to the input circuit 1. For example, the status signal A1 is input to the counting unit 3 as A1 status data (DS) by the first channel head pulse signal.
Here, the signal generator 6 sends a read signal ((R) in FIG. 2) of the read / write signal SCM to the storage circuit 2, and
An instruction to read the status signal (for example, A0) before the frame is issued. Further, the signal generation circuit 6 sends the data bus signal SCL to the selection circuit 4, and transfers the count data of A0 one frame before from the storage circuit 2 to the counting unit 3. After inputting the data of the status signals A1 and A0, the counting unit 3 inputs the count instruction signal SCK from the signal generation circuit 6 and starts counting A1 and A0. As an example, when the counting circuit of the present embodiment is applied to a parity check, the sum of the status data A0 and A1 is calculated. Here, DTA0 in the count data signal DC of FIG.
Corresponds to the status signal A0 described above, and DTA1 corresponds to A0.
The calculation result of + A1 is shown. If the operation result is correct, the data of A1 is stored in the storage circuit 2 via the selection circuit 4 by the write instruction signal shown in FIG. 2 (W) of the read / write signal SCM and the corresponding data bus signal SCL. Is stored. The counting result is transmitted from the output circuit 5 as data of the channel output DO1 by the channel output signal SCO output from the signal generation circuit 6. The output data from the output circuit 5 is converted and output in parallel for each channel. That is, in the case of the channel 1, it is transmitted as status data A0, A1, A2. Thus, the status data A of channel 1
The processing of No. 1 is performed during the timing of the time slot A1 of each status data DS in FIG. 2, and the processing of the status data B1 is subsequently performed during the timing of the time slot B1. Thereafter, the same processing is performed in the case of the time slot C1.

As described above, the processing performed independently is temporally divided by using one circuit, so that a plurality of processings can be performed independently by one circuit.
In this embodiment, the counting circuit has been described. However, the function of the present invention can be easily realized not only by the counting circuit but also by a logic circuit.

[0012]

As described above, according to the present invention, when the same signal processing is performed a plurality of times in the reference frame, each processing is performed in a time-divided manner, and the data in the circuit is stored in the storage circuit. , A plurality of signal processings can be independently performed by a configuration including one input circuit, a counting unit, an output circuit, and a storage circuit / selection circuit. Therefore, the circuit scale becomes the minimum configuration regardless of the number of times of signal processing. Further, there is an effect that the control signal for controlling the signal processing operation does not become complicated even if the number of times of the signal processing increases.

[Brief description of the drawings]

FIG. 1 is a block diagram of a counting circuit according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram of a conventional counting circuit.

[Explanation of symbols]

 1, 11, 12, 13 input circuit 2 storage circuit 3, 31, 32, 33 counting section 4 selection circuit 5, 51, 52, 53 output circuit 6, 61 signal generator

Claims (2)

(57) [Claims] 1. A multiplexed signal which is multiplexed into respective frames arranged in time series.
At the beginning of input data signals of multiple channels
Status data signals such as parity bits
A storage unit for storing the data as independent data in the channel;
Input the input data signal and start each channel from the outside.
As the starting point, the status data signal of each channel is set to 1
Input circuit output as a unit and read signal from outside
One frame before the current time stored in the storage unit
The status data signal of the corresponding channel of (D)
TA0) from the input circuit after reading
Input status data signal (A1) and input external coefficient
In response to the instruction signal, the status data signal (DTA0)
(DTA0) and the status data signal (A1)
+ A1 = DTA1) is transferred to the storage circuit
Counting section, and a data bus signal from outside,
Transfer of count data between the storage unit and the counting unit and for each channel
A selection circuit for outputting the operation data, Ji from outside
An output circuit that outputs the operation data transferred from the storage circuit via the selection circuit in parallel by a channel instruction signal, and each of the input circuit, the counting unit, the storage unit, the selection circuit, and the output circuit And a signal generating means for transmitting the external control signal for controlling the timing at a predetermined timing. 2. The control signal according to claim 1, wherein said signal generating means captures a plurality of status data signals in each frame into said input circuit at a predetermined timing, and a count for causing said counting section to start counting for each status data signal. A control signal, a control signal for instructing the storage unit to write and read, a control signal for the selection circuit to control data transfer between the counting unit and the storage unit, and a control signal for the output circuit. 2. The counting circuit according to claim 1, wherein a control signal for outputting status data is transmitted via the control circuit.