JPS5849826B2 - pulse counting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse counting circuit that counts the number of pulses of an input signal for a certain period of time and outputs the counting result.

Conventionally, in pulse counting circuits that count the number of pulses of an input signal over a fixed period of time, even if the frequency of the pulses is constant, the phase of the pulses to be counted and the reference fixed period of time do not match, so the actual A counting error of ±1 pulse number occurred with respect to the pulse value.

Furthermore, even if the pulse is synchronized with a reference pulse that counts for a certain period of time, if there is a slight change in the pulse frequency, there will still be a difference between the counted number and the actual number of pulses.
There was a difference of 1.

Therefore, when the count number is displayed, even if the number of pulses of the input signal is constant, the display is not constant, and the display of the least significant bit becomes unstable and flickers, making it very difficult to read.

This invention was made in view of the above circumstances, and its purpose is to provide a pulse count that can accurately count the number of pulses of an input signal and that can stably display the counting results. The purpose of this invention is to provide a counting circuit.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a first timer circuit 1 starts operating in response to an input signal and stops operating after a predetermined period of time has elapsed.

That is, an input signal is supplied to a set input terminal of a flip-flop circuit (hereinafter simply referred to as an FF circuit) 2.

The set output of this FF circuit 2 is supplied to the counter 3,
This counter 3 is also supplied with a clock signal from a reference signal generating circuit 4.

The counter 3 outputs a logic "1" signal after a predetermined time has elapsed, that is, when the count by the clock signal reaches a predetermined value.

The output of the counter 3 is supplied to the reset input terminal of the FF circuit 2 and also to the second timer circuit 5.

This second timer circuit 5 starts operating in response to the output of the counter 3, and stops operating after a predetermined period of time has elapsed.

That is, the set input terminal of the FF circuit 6 is connected to the counter 3.
output is supplied.

The set output of this FF circuit 6 is supplied to the counter 7,
The counter 7 is also supplied with a clock signal from the reference signal generating circuit 4.

The counter 7 outputs a logic "1" signal after a predetermined time has elapsed, that is, when the count by the clock signal reaches a predetermined value.

The output of the counter 7 is supplied to the reset input terminal of the FF circuit 6.

On the other hand, a counter (counting circuit) 8 is supplied with the input signal and the set output of the FF circuit 2.

This counter 8 counts the number of pulses of the input signal while the set output from the FF circuit 2 is being supplied.

The count contents of the counter 8 are supplied to a latch circuit 9, and the output of the counter 3 is supplied to the latch circuit 9.

The latch circuit 9 is a circuit that stores the contents of the counter 8 when the output signal of the counter 3 is supplied.

The output of the latch circuit 9 is the latch circuit (memory circuit) 10
This latch circuit 10 is supplied with a signal from an AND circuit 14, which will be described later.

The latch circuit 1o is a circuit that stores the contents of the latch circuit 9 according to the output signal of the AND circuit 14.

Note that the stored contents of the latch circuit 10 are supplied to a display device (not shown) so that the contents are displayed on the display device.

Further, each output of the latch circuits 9 and 10 is connected to a comparison circuit 11.
is supplied to.

This comparison circuit 11 compares the previous counting result of the latch circuit 10 and the current counting result of the latch circuit 9, and if the result of the comparison is that the current counting result is r-1j less than the previous counting result, logic "1" is generated. This is a circuit that outputs a logic "ON" signal when the difference is other than the above-mentioned "-11".

On the other hand, the input signal is supplied to the clock pulse input terminal CP of a determination circuit, for example, a D-type flip-flop circuit (hereinafter simply referred to as a D-FF circuit) 12, and the set output of the FF circuit 6 is supplied to the data input terminal D. is supplied.

The D-FF circuit 12 is a circuit that outputs a signal when a pulse of the input signal is detected during the operation of the counter 7.

The set output of the D-FF circuit 12 is supplied to one input terminal of a NAND circuit 13, and the output signal of the comparison circuit 11 is supplied to the other input terminal of this NAND circuit 13.

The output of the NAND circuit 13 and the output of the counter 7 are supplied to the latch circuit 10 via an AND circuit 14.

Next, the operation in such a configuration will be explained.

For example, assume that an input signal as shown in FIG. 2a is being supplied.

Then, the FF circuit 2 is set at the rising edge of the first pulse, and the counter 3 counts the clock pulses from the reference signal generating circuit 4 based on this set output.

At this time, the counter 8 counts the number of pulses of the input signal based on the set output of the FF circuit 2.

When the count number of the counter 3 reaches a predetermined value, the counter 3 stops its operation and outputs the signal shown in FIG. 2d.

This output resets the FF circuit 2 and stops the counting operation of the counter 8, and sets the FF circuit 6 so that the set output counter 7 counts the clock signal from the reference signal generating circuit 4.

Also, at this time, the latch circuit latches the contents of the counter 8.

When the current counting result is latched in the latch circuit 9, the comparison circuit 11 compares the previous counting result of the latch circuit 10 with the current counting result, and if the current counting result is r-1j less than the previous counting result. It outputs a "1" signal, and otherwise issues an "O" signal.

Thereafter, when the count number of the counter 7 reaches a predetermined value, the counter 7 stops its operation, and the FF circuit 6 is reset by outputting the signal shown in FIG. 2e.

When a pulse according to an input signal is supplied to the D-FF circuit 12 while the counter 7 is operating, the D-FF circuit 1
2 is set.

The NAND circuit 13 and the AND circuit 14 decide whether or not to supply the output of the counter 7 to the latch circuit 10 based on the comparison result of the comparison circuit 11 and the judgment result of the D-FF circuit 12. This time there is a difference of 11 less than the previous time. When the D-FF circuit 12 is being reset, the output of the counter 7 is supplied to the latch circuit 10 via the AND circuit 14, and the latch circuit 10 outputs the contents of the latch circuit 9. Latch the current count result.

Furthermore, when the difference between the previous time and this time is "-1" less this time and the D-FF 12 is set, the output of the counter 7 is not supplied to the latch circuit 10, and the latch circuit 10 stores the previous counting result. ing.

Further, when the difference between the previous time and this time is other than "-1-1", the output of the counter 7 is supplied to the latch circuit 10 via the OR circuit 14.

Then, the latch circuit 10 latches the contents of the latch circuit 9.

The timing chart of the above-mentioned main parts is shown in Figure 2a...
...shown in j.

Figure 3 shows a display characteristic diagram of the input signal and display output of the device according to the present invention, where the solid line shows the relationship between the input signal and display output when the input signal increases, and the broken line shows the relationship between the input signal and display output when the input signal decreases. shows the relationship between the input signal and display output.

The difference in the display value change point when the input signal increases and decreases is the second
It is determined by the timer circuit time, and the shorter the second timer circuit time, the less the difference in display value change points when the input signal fluctuates, and the closer the display characteristics are to ideal.

Furthermore, as the second timer circuit time becomes longer, the difference in display value change points when the input signal fluctuates becomes larger.

For this reason, in the present invention, the second timer circuit time is determined according to the constant cycle fluctuation error of the input signal, and a predetermined value is set, thereby achieving stable display characteristics and ideal display characteristics. It is.

In this way, as long as the current time is r-1j less than the previous time and the pulse signal of the input signal is being supplied while the second timer circuit 5 is operating, the contents of the latch circuit 10 are left as they were last time, and other than that. Notogi is designed to update the contents of the latch circuit 10 with the current count result, that is, the contents of the latch circuit 9, so even if the previous count value differs due to a slight difference in the pulse cycle of the input signal, it will remain unchanged from the previous count value. The same count value is obtained, the count value becomes stable, and the display of the count value does not flicker.

In the above embodiment, in the comparison circuit, the output is changed depending on whether the difference between this time and the previous time is "-L1 less" or something else. It is also possible to change the output depending on whether it is less than -2'' or other than that.

As detailed above, according to the present invention, it is possible to provide a pulse counting circuit that can accurately count the number of pulses of an input signal and can stably display the counting results. .

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a schematic block diagram showing the whole, FIG. 2 a...j is a timing chart for explaining the operation, and FIG. FIG. 3 is a display characteristic diagram for explaining display characteristics of the invention. 1...First timer circuit, 2,6...
FF circuit, 3, 7... Counter, 4...
Reference signal generation circuit, 5...1...Second timer circuit, 8
...Counter (counting circuit) 9...Latch circuit, 10...1...Latch circuit (memory circuit) 11...1...Comparison circuit, 12...D-FF Circuit (judgment circuit), 13... NAND circuit, 14...
AND circuit.

Claims (1)

[Claims] 1. In a pulse counting circuit that counts the number of pulses of a human input signal for a certain period of time and outputs the counting result, a first timer circuit that starts operation in response to the input signal and stops operation after a predetermined period of time has elapsed; When the first timer circuit operates,
a counting circuit that counts the number of pulses of the input signal; a second timer circuit that starts operation when the operation of the first timer circuit ends and stops operation after a predetermined period of time; During operation, a determination circuit that determines whether a pulse of the input signal is detected; a storage circuit that stores the previous counting result of the counting circuit; A pulse counting circuit comprising means for comparing the current counting result and updating the contents of the storage circuit to the contents of the counting circuit according to the comparison result and the judgment result of the judgment circuit.