JP2678596B2 - Thin film transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a thin film transistor applied to an active matrix type liquid crystal display, an image sensor, a three-dimensional integrated circuit, or the like. [Prior Art] A conventional thin film transistor is, for example, an international display research conference.
The structure was as shown in 1985 p.30-p.31. This structure is generalized, and its outline is shown in FIG.
A gate electrode 202 made of chromium or the like and a gate insulating film 203 so as to cover the gate electrode 202 are provided on an insulating substrate 201 made of glass, quartz sapphire, or the like. On this, a channel region 204 made of a non-quality silicon thin film, and a source region 205 and a drain region 206 made of an amorphous silicon thin film doped with an impurity to be a donor or an accessor are in contact with the upper side of the end of the channel region. Has been formed. Further, a source electrode 207 and a drain electrode 208 are provided in contact with this. [Problems to be Solved by the Invention] However, the conventional thin film transistor has the following problems. That is, in order to reduce the OFF current (current flowing between the source and the drain when the transistor is off), when forming the source region 205 and the drain region 206 so that the channel region 204 can maintain high resistance, It is necessary to prevent impurities, which are contained therein and serve as donors or acceptors, from diffusing into the channel region 204. However, conversely, for this reason, the impurity concentration of the source / drain region is lowered to increase the resistance of the region, or the impurities are less likely to diffuse into the channel region in contact with the source / drain region, and the high-resistance channel is formed. The increase in parasitic resistance has been remarkable, such as the increase in resistance corresponding to the film thickness of the region. That is, the gate insulating film 20
Carriers of the inversion layer induced at the interface between 3 and the channel region 204 flow to the source region 205 or the drain region 206 via the parasitic resistance RS. However, since RS is large, how to reduce the equivalent resistance of the inversion layer. However, the ON current (current between the source and drain that flows when the transistor is in the ON state) was kept small. FIG. 3 is an equivalent circuit diagram of a thin film transistor for quantitatively clarifying the above problems. V _G , V
_{D 1} and I _D are the gate voltage, the drain voltage, and the drain current, respectively. V _GE and V _DE are effective gate voltage and drain voltage applied to the transistor, respectively, and are represented by the following equations. V _GE = V _G −I _D R _S (1) V _DE = V _D −2 I _D R _S (2) Therefore, the series resistance component RS effectively lowers the gate voltage and drain voltage and reduces the ON current. . At this time, under V _G −V _th > V _D , I _D = β (V _GE −V _th ) V _DE (3) Therefore, from equations (1), (2), and (3), Becomes Where β is the gain of the transistor (β = W / LC
_OX μ, L is the channel length, W is the channel width, C _OX is the capacitance of the gate insulating film, μ is the mobility), and I _O is the drain current when R _S = 0. Therefore, I _D is the second denominator of equation (4).
It will be reduced by the number of terms. Moreover, it can be seen that as β, V _G , and V _D are increased to increase the ON current, the effect of reducing I _D becomes more remarkable. The present invention solves such a problem, and an object of the present invention is to provide a thin film transistor capable of reducing the parasitic resistance R _S while maintaining a high resistance in the channel region. [Means for Solving the Problem] The present invention provides a thin film transistor formed on an insulating substrate, in which a source region and a drain region of the thin film transistor are separated from each other by a first silicon thin film doped with an impurity to be a donor or an acceptor. Island-shaped regions, the source and drain regions of the thin film transistor have a film thickness of 500 to 3000 angstroms, and the channel region of the thin film transistor is formed between the source and drain regions and part of the upper surface. 2 silicon thin film, the source electrode is formed so as to be connected to the source region, the drain electrode is formed so as to be connected to the drain region, and the gate insulating film is formed by the source electrode, the source region, and the source region. It is formed so as to completely cover the channel region, the drain region, and the drain electrode. Now,
The gate electrode is formed on the gate insulating film on the channel region. [Examples] Hereinafter, the present invention will be described in detail based on Examples. FIG. 1 is an example of a sectional structural view showing a thin film transistor according to an embodiment of the present invention. Glass, quartz, on an insulating substrate 101 such as sapphire, a film thickness of 500 ~ 5000 Å polycrystalline silicon doped with impurities to serve as donors or acceptors,
Source region 10 made of a silicon thin film such as amorphous silicon
2 and the drain region 103 are formed. A channel region 104 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is provided so as to contact the upper side of the source region end and the upper side of the drain region end so as to connect them. The source electrode 105 made of metal, a transparent conductive film, or the like is in contact with the source region 102, and the same drain electrode
106 is in contact with the drain region 103. All of these are Si
A gate insulating film 107 such as O ₂ , SiN _x , and SiON is coated,
A gate electrode 108 made of metal, a transparent conductive film, or the like is provided on this. The gate insulating film 107 also serves as an interlayer insulating film that maintains insulation between wirings. In a thin film transistor configured in this way, the
It is possible to reduce the parasitic resistance R _S while keeping the F current low. First, in order to form the silicon thin film to be the channel region 104 at the place where the source region 102 and the drain region 103 made of the silicon thin film containing a large amount of impurities are formed in advance, the impurities in the source / drain region are It is possible to maintain the high resistance of the channel region and suppress the OFF current to a low level without diffusing all over. In addition, impurities in the source / drain regions diffuse into the silicon thin film in the channel region near the source / drain regions due to the temperature during the process of forming the silicon thin film itself, and the resistance decreases. Therefore, it is possible to reduce the parasitic resistance R _S. Further, according to the present invention, the film thickness controllability of the silicon thin film in the channel region is improved. That is, unlike the conventional case, the film thickness of the silicon thin film in the channel region is not determined by the etching end point when patterning the source / drain regions, but the film thickness is defined only by the formation of the silicon thin film. Therefore, it is possible to accurately control the film thickness without being affected by variations in etching. In particular, in order to increase the resistance of the channel region to reduce the OFF current, and to reduce the amount of space charge in the silicon thin film to reduce the threshold voltage and increase the ON current, the thickness of the silicon thin film in the channel region is set to It is important to make the thickness as thin as possible, and in order to improve the characteristics of the thin film transistor, it is extremely effective to accurately control the thickness of the ultrathin silicon thin film as described above. Furthermore, since a sufficiently large amount of impurities can be added to the source region 102 and the drain region 103 without paying attention to the diffusion of extra impurities into the channel region, the resistance of the source / drain region itself is lowered. Ohmic contact with the source electrode 105 and the drain electrode 106 is improved, and as a result, the parasitic resistance R _S is further reduced. FIG. 4 shows the relationship between the film thickness of silicon forming the source region 102 and the drain region 103 shown in FIG. 1, the parasitic low resistance R _S , and the drain current I _D. Where the gate voltage
The V _GS is 20 V, the drain voltage V _DS is 4 V, and the transistor size is that the channel length L is 20 μm and the channel width W is 10 μm. A sufficiently large amount of impurities can be added to the source region 102 and the drain region 103, but the thickness of the silicon thin film is
When the thickness is less than 500Å, the resistance of the silicon thin film itself increases, and the source electrode increases with the increase of the resistance.
The parasitic resistance R _S rapidly increases due to the effect of increasing the contact resistance value between the drain electrode 106 and the source region 102 and the drain region 103. As the parasitic resistance R _S increases,
The drain current I _D decreases. Therefore, the source region 102,
The thickness of the silicon thin film that forms the drain region 103 is 500Å
You have to do this. Further, in order to obtain a full-color high-definition liquid crystal display, it is necessary to have a finer pixel pitch, that is, a pixel with a pitch of about 100 μm, than the pixel with a pitch of 300 μm for monochrome display which is currently used as a display body of a word processor. . It is necessary to divide the pixel that was one pixel in black and white display into full color, and to divide the pixel which was one in the past into three pixels composed of red, blue and green. There are two demands that a high-definition display cannot be obtained unless the number of pixels is three times as high as the current number of pixels. When the pixel pitch becomes as small as 100 μm, it becomes particularly important to retain the electric charge written in the liquid crystal for displaying the liquid crystal display. This is because the display quality deteriorates if the electric charge is leaked. Therefore, the charge retention characteristics necessary for 100 μm pitch pixels, that is, the off current of the thin film transistor
Estimate how much Ioff is needed. The charge Q written in the liquid crystal forming the pixel is given by Q = C _LCD V. C _LCD is the capacitance of the liquid crystal, and V is the voltage applied to the liquid crystal. The charge Q is 1 field (16mse
In step c), the leak current of the thin film transistor decreases, but the amount of decrease must be such that the change amount ΔV of the voltage V applied to the liquid crystal is 0.1 V or less. Otherwise, it can be visually recognized as a change in gradation. Therefore, the amount of change in charge ΔQ is ΔQ ≦ C _LCD ΔV = 0.1C _LCD (5). The amount of charge ΔQ ′ flowing out through the thin film transistor in one field is ΔQ ′ = I _OFF t = 16 × 10 ⁻³ I _off (6). If the equations (5) and (6) are set to be equal, and the dielectric constant of the liquid crystal is 10 and the gap length of the pixel is 10 μm, Ioff is I _off = 5.5 × 10 ⁻¹³ A. Therefore, I _off must be 0.55 PA or less. FIG. 5 shows the relationship between the film thickness of the silicon thin film forming the source region 102 and the drain region 103 shown in FIG. 1 and the current value Ioff when the thin film transistor is turned off. Here, the drain voltage V _DS is 4 V, the transistor size is such that the channel length L is 20 μm and the channel width W is 10 μm. From FIG. 5, I _off becomes 0.55 PA or less when the film thickness of the silicon thin film is 5000 Å or less. Therefore, the thickness of the silicon thin film must be 5000 Å or less. Further, in FIG. 5, the film thickness 3000 Å of the silicon thin film is an inflection point regarding I _off , and below the film thickness, I _off is stable to a minute constant value satisfying 0.55 PA for the following reason. . FIGS. 6A and 6B show the spread of the depletion layer in the drain region when the thin film transistor is in the off state. The size of the depletion layer 110 is the size of the gate insulating film 108.
And the gate voltage V applied through the channel region 104
It is known to have a maximum value X _dmax , which is determined by the balance between _GS and the drain voltage V _DS . Further, since the depletion layer has no carriers inside, it is a high resistance region. FIG. _6A is a diagram in the case where the film thickness of the silicon thin film in the drain region 103 is thicker than the X _dmax . FIG. 6 (a)
The carriers pass from the drain region 103 to the channel region 104 through the path indicated by the arrow A, and the length of the depletion layer through which the carriers pass at this time is at most X _dmax . However,
As shown in FIG. 6B, when the thickness of the silicon thin film in the drain region 103 becomes smaller than X _dmax , the depletion layer spreads throughout the drain region 103. Then
The length of the depletion layer through which the carriers shown by the arrow B in FIG. 6B pass is C. X _dmax is 3000 Å which is the bending point of the graph shown in FIG. 5, and C is about 5 μm due to the mask alignment margin and the like, and C> X _dmax . I _off is smaller, and even if the thickness of the silicon thin film is further reduced, I _off
Does not change much. In addition, the thickness of the drain region 103 is X
An inflection point for I _off occurs when it equals _dmax . Its film thickness is 3000Å. Therefore, it is more desirable that the film thickness of the drain region 103 is 3000 Å or less. Similarly, the source region 102 is more preferably 3000 Å or less. FIG. 7 is a graph showing an example of characteristics of the thin film transistor according to the present invention. The horizontal axis represents the gate voltage V _GS , and the vertical axis represents the logarithmic value of the drain current _ID . Drain voltage V _DS is 4V,
The channel length L is 20 μm and the channel width W is 10 μm.
Polycrystalline silicon is used for the silicon thin film in the channel region, and the film thickness is 200Å. As is clear from the graph, the polycrystalline silicon thin film itself maintains a high resistance, and an OFF current of 5.5 × 10 ^-13 A or less can be obtained by setting the polycrystalline film 5 in the source and drain regions to a film thickness of 5000 Å or less. Has been. Also, the thickness of the source region and the drain region is 500
Since it is possible to use an extremely thin film thickness of 200Å while maintaining Å or more, the space charge amount decreases, the threshold voltage is small, that is, the ON state rapidly changes, and the ON current is large. Good characteristics are obtained. Further, according to the present invention, it is possible to apply a thinner silicon thin film. [Effects of the Invention] The present invention has the following excellent effects. First, by setting the thickness of the silicon thin film in the source region and the drain region to 500 to 3000Å, the parasitic resistance R _S can be reduced while keeping the silicon thin film in the channel region high in resistance. As a result, a small OFF current and a large ON current can be compatible for the first time. Secondly, the thickness of the silicon thin film in the channel region can be controlled accurately. As a result, an extremely thin silicon thin film, which is an essential requirement for improving the characteristics of the transistor, can be realized uniformly and with good reproducibility. Thirdly, since a large amount of impurities can be added to the source region and the drain region without adversely affecting others, the ohmic contact between the source region and the source electrode or the drain region and the drain electrode is improved. To be done. This significantly improves the transistor characteristics especially when the drain voltage V _DS is small. Fourthly, since the silicon thin film in the channel region and the silicon thin film in the source / drain regions are completely covered with the gate insulating film, the passivation effect can be automatically exerted. Fifth, since no special high-temperature heat treatment is required to manufacture the thin film transistor of the present invention, it can be manufactured on an inexpensive ordinary glass substrate and can be applied to an inexpensive and large-area active matrix substrate. is there.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing the structure of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a sectional view showing the structure of a conventional thin film transistor. FIG. 3 is an equivalent circuit diagram of the thin film transistor. FIG. 4 is a diagram showing the relationship between the parasitic resistance and drain current of the thin film transistor according to the embodiment of the present invention and the silicon film thickness. FIG. 5 shows I _{off of} a thin film transistor according to an embodiment of the present invention.
FIG. 3 is a diagram showing the relationship between the film thickness and the silicon film thickness. 6 (a) and 6 (b). FIG. 6 is a diagram showing the spread of a depletion layer in the drain region of a thin film transistor according to an example of the present invention. FIG. 7 is a graph showing characteristics of the thin film transistor of the present invention. [Description of Reference Signs] 101, 201, 801 ... Substrate 102, 205, 802 ... Source region 103, 206, 303 ... Drain region 104, 204, 304 ... Channel region 105, 207, 305 ... Source electrode 106 , 208, 306 ... Drain electrode 107, 203, 807 ... Gate insulating film 108, 202, 808 ... Gate electrode 110 ... Depletion layer 309 ... Interlayer insulating film

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Nao Sato               3-5 Yamato, Suwa-shi SEIKOE               Pson Corporation (72) Inventor Shinji Ryoko               3-5 Yamato, Suwa-shi SEIKOE               Pson Corporation (72) Inventor Ryosuke Araki               3-5 Yamato, Suwa-shi SEIKOE               Pson Corporation (72) Inventor Mutsuo Matsuo               3-5 Yamato, Suwa-shi SEIKOE               Pson Corporation                (56) References JP-A-60-251667 (JP, A)                 JP 58-84466 (JP, A)                 JP 60-186063 (JP, A)                 JP 60-260155 (JP, A)

Claims (1)

(57) [Claims] In a thin film transistor formed on an insulating substrate, a source region and a drain region of the thin film transistor are composed of isolated island-shaped regions made of a first silicon thin film to which an impurity serving as a donor or an acceptor is added. The drain region has a thickness of 500 to 3000 angstroms, the channel region of the thin film transistor is a second silicon thin film formed between the source / drain regions and a part of the upper surface, and the source electrode is the source region. The drain electrode is formed so as to be connected to the drain region, and the gate insulating film completely covers the source electrode, the source region, the channel region, the drain region, and the drain electrode. And the gate electrode is formed on the channel region. A thin film transistor formed on a gate insulating film.