JP2687498B2 - Test pattern generation method - Google Patents

Description

The present invention relates to a test pattern generation method, and more particularly to a test pattern generation method for generating a test pattern of a logic circuit including a bus.

[Conventional technology]

Conventionally, as a method for investigating a failure of a logic circuit, when a test pattern signal is input to the logic circuit from an input terminal and an output different from an expected output is detected at the output terminal, it is determined that the circuit under test has a failure. Testing is being done. To generate this test pattern signal,
First, it is necessary to obtain a test pattern signal for investigating one focused point in the logic circuit, and the following method is used for this purpose.

First, a test pattern signal is obtained for one path from the fault point to be investigated in the logic circuit to the input terminal and the output terminal. Therefore, when a test pattern signal is input to the input terminal, a pattern that is different from the pattern expected as a normal output is output to the output terminal, and the output signal can be used to check the fault condition at the fault point. Signal (first test pattern signal)
Generate

Next, in addition to the one path from the input terminal including the fault point to the output terminal described above, if there is another input terminal to which a test pattern signal can be added in the entire logic circuit, A test pattern signal (second test pattern signal) generated by a random condition generated by a random number or the like, which is different from the above test pattern, is assigned as an input signal.

[Problems to be solved by the invention]

In the conventional test pattern generation method described above, when a bus is included in the logic circuit to be tested, when the logic circuit operates by the input of the first test pattern signal and the second test pattern signal, There is a problem in that the bus receives a plurality of bus controls at the same time, and there is a possibility that contention for the bus control will occur.

It is an object of the present invention to provide a test pattern generation method capable of generating a test pattern signal without causing bus control conflict when generating a test pattern signal of a logic circuit including a bus.

[Means for solving the problem]

The test pattern generation method of the present invention generates a first test pattern by tracing the front and rear sides of a logic circuit while focusing on a failure, and when there is an input terminal to which a test pattern is to be added, a random test pattern is generated. In the test pattern generation method for generating the second test pattern in which the applied signal is determined under the conditions, (A) the input value of the control gate is not determined after the generation of the first test pattern focused on a certain fault. Bus extracting means for extracting the remaining bus and outputting bus control information; (B) bus controlling means for determining an input value of the control gate so that only one bus control is valid according to the bus control information; (C) A test pattern for performing a backward trace based on an input value of the control gate to generate a third test pattern before the generation of the second test pattern. And it is configured to include emissions generating means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of one embodiment of the present invention.

The logic circuit data 1 is input to the test pattern generation means 2 to generate a first test pattern focusing on a certain fault, and a partial test pattern 6 is generated by backward tracing from the fault point of the logic circuit to the test pattern application point. To do.
Next, the logic circuit data 1 is input to the bus extraction means 4 to extract a bus which remains undecided because an input value is not given to the control gate input of the bus included in the logic circuit and the bus control information is output. .

The fault simulator 3 simulates the partial test pattern 6 and outputs the control gate input value of the bus in the logic circuit to the bus input value memory 8.

When the bus control means 5 refers to the bus input value memory 8 to determine the control gate input value of the bus, if the bus conflicts, the partial test pattern 6 is discarded and the test pattern generating means 2 determines whether or not there is a failure. The test pattern 6 is generated again. If the bus does not cause a conflict, if there is a test pattern whose applied value is not determined when the partial test pattern 6 is applied, a random pattern is assigned to the applying point by the test pattern generating means 2 to generate a second pattern. Output a test pattern. When the control gate input value of the bus is not determined, one of the control gate input values of the bus is assigned a fixed value and the other is assigned a high impedance value, and the test pattern generating means 2 traces backward, Partial test pattern 7 which is the test pattern of
Get. Partial test pattern 6 and partial test pattern 7
When both are applied, a random pattern is assigned by the test pattern generation means 2 to a test pattern application point whose applied value has not yet been determined, and the test pattern 9 is output as the second test pattern.

In this way, the bus control means 5 repeats the above procedure for each bus in the logic circuit.

FIG. 2 is an explanatory diagram showing an application example of the test pattern generation method of FIG.

A test pattern is generated by focusing on a certain fault 11 of the logic circuit 10, the application point 13 of the partial test pattern 6 is determined, and as a result of the fault simulation, the test pattern application point of which the control gate input value of the bus 12 is undetermined is found. It is assumed that it still remains.

Further, it is assumed that a definite value is given to any one of the control gate inputs of the bus, the other parts are set to high impedance, and the test pattern generation is traced backward from the bus 12 to determine the application point 14 of the partial test pattern 7.

If there is an undetermined test pattern application point even after applying the partial test patterns 6 and 7, a random pattern is assigned to this application point and the test pattern application point 15
By determining, it is possible to generate a test pattern that does not cause bus contention.

〔The invention's effect〕

As described above, the present invention has an effect of being able to generate a test pattern signal in which no bus control conflict occurs when generating a test pattern of a logic circuit including a bus.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
It is explanatory drawing which shows the application example of the test pattern generation system of the figure. 1 ... Logic circuit data, 2 ... Test pattern generation means, 3 ... Fault simulator, 4 ... Bus extraction means, 5
... Bus control means, 6 ... partial test pattern, 7 ...
Partial test pattern, 8 ... Bus input value memory, 9 ...
Test pattern, 10 …… Logic circuit, 11 …… Failure, 12 ……
Bus, 13 ... partial test pattern application point, 14 ... partial test pattern application point, 15 ... test pattern application point.

Claims (1)

(57) [Claims] 1. When an input signal to which a test pattern is added is generated by performing a front / back trace of a logic circuit by paying attention to a failure and further a test pattern is added, an applied signal is applied under a random condition. In the test pattern generation method for generating the second test pattern in which the control gate input value remains undecided after (A) the first test pattern generation performed by focusing on a certain fault. And (B) bus control means for determining the input value of the control gate so that only one bus control is valid according to the bus control information. Before the second test pattern is generated, there is provided a test pattern generating means for performing a backward trace based on the input value of the control gate and generating a third test pattern. A test pattern generation method characterized in that