JP3441315B2 - Method and apparatus for creating test data - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device for electronic parts mounted on a printed board or the like, and more particularly to a method for creating test data necessary for confirming part operation.

[0002]

2. Description of the Related Art In order to confirm the operation of a component mounted on an apparatus, test data including an input signal of a target component and an output signal corresponding to the input signal is required. Usually, the test data is created by using the result of the logic simulation to obtain the input signal and the expected value. Input this to the part and confirm that the output is the same as the expected value.

As a method for confirming the operation of the parts mounted on the printed board, a method called in-circuit test is generally used, in which test data is created for each part mounted on the printed board and the operation of a single piece is tested. Are known. The test data used in this method is created based on the operation specifications of the target component and the timing specifications of the tester. However, since it takes time to create test data, there is a problem as a method of testing electronic components with a short product life.

Therefore, as described in Japanese Patent Application Laid-Open No. 3-158767, a method of creating test data for an in-circuit test by utilizing a logic simulation result has been realized. Here, when performing the logic simulation, the input data is created in consideration of the timing specifications of the tester and the connection state of the components mounted on the printed board, and the result of the logic simulation satisfies the timing specifications of the tester. I have confirmed that.

[0005]

As described above, when the test data for confirming the operation of the component mounted on the printed board is created by the logic simulation, the timing simulation of the tester is not taken into consideration. There is a contradiction between the tester operation and the tester operation based on the operation confirmation test data edited from the result.

FIG. 2 illustrates an example of conventional test data generation, in which the logic simulation result is used as it is and a mismatch occurs between the logic simulation result and the tester operation. In the same figure (a), the input signals A and B for logic simulation are used to arbitrarily set the signal change from the logic operation of the circuit. In the same figure (b), input signals A and B are given to the target component (2-input OR) to perform a logic simulation, and an output signal C is obtained at the output terminal.

FIG. 1C shows the result of logic simulation, which is composed of input signals A and B and an output signal C. As shown in the figure, the input A has a logical value [11], and the input B has a logical value [0 that causes a change within the time of the element ready td from the change of the input A.
1], the output C rises with a delay of the OR element delay td. When the data of the input / output signal is extracted from the extraction points 1, 2, 3 set immediately before the change point of the input signal with respect to the result of the logical simulation, the operation confirmation test data of FIG. . By the way, the logical value of A is [110], and the logical value of B is [01].
The logical values of 1] and C are [001].

FIG. 1F shows the operation of the tester. Inputs A and B of the tester apply the logic values [110] and [011] of the input signals A and B obtained by the logic simulation at a tester rate (here, 4 μs). Output C of tester
Rises with a delay of the element delay td of the target component OR. At this time, the observed value by the tester is detected at a timing delayed by the tester skew ts (about 1 μs),
The observed value C of the first and second times becomes "1.1", and the expected value C of the test data based on the logic simulation result.
Does not match “0 · 0”.

As described above, if the result of the logic simulation is used as it is, it is impossible to discriminate whether the tester operation is erroneous or the operation of the target component is abnormal, and the component operation cannot be confirmed by the tester.

Further, since the element delay td of the target component is generally quite short with respect to the operation timing of the tester due to the tester rate and the tester skew, the operation of FIG. However, if the integration of the elements of the unit parts becomes enormous and td ≧ ts, even if the operation of the tester is normal, the observation result of the tester may be inconsistent. Therefore, it is necessary to consider the timing with the tester operation in the test data.

As described above, if the logic simulation result is used as it is, it is not always possible to obtain accurate test data for operation confirmation. Therefore, when using the result of the logic simulation, conventionally, in consideration of these circumstances, the input data is manually corrected from the result of the logic simulation.

However, the length of the delay time td varies depending on the degree of integration of the unit parts and the propagation path, and at the same time, matching with the tester operation is required. Was needed. Further, there is a problem that the quality of the test data is deteriorated due to improper modification.

In view of the problems of the prior art, an object of the present invention is to use the result of logic simulation as it is, and consequently to eliminate the contradiction of logic and enable the matching with the tester operation. And to provide a device. According to this, the work of creating the test data for the in-circuit tester can be made efficient, and the quality of the test data can be improved.

[0014]

SUMMARY OF THE INVENTION The above-mentioned object is to perform a logic simulation of an electronic device on which a component is mounted, and use the result to create test data for confirming the operation of each component. Extract one or more input signals of the target component from the simulation result,
The input signal or the interval of each change point between the input signals is edited to be longer than the maximum delay time of the target component, and the input signal and the output signal of the target component are extracted from the result of the re-logic simulation by the edited input signal. Then, the former is used as the input data for the operation confirmation test, and the latter is used as the expected value for the observation result of the test.

When the target component is composed of a plurality of elements and has a plurality of signal propagation paths with the inspectability as a unit, the signal having the maximum integrated value of the element delays in the maximum delay time. Adopt the delay time of the propagation path.

According to the configuration of the present invention, the timing of the change of the input signal in the re-logic simulation is extended to the maximum delay time of the target component or more, so that matching with the tester operation can be achieved.

The above-described object is also stored in a method of performing a logical simulation of an electronic device having a component mounted thereon and using the result to create test data for confirming the operation of each target component by a tester. One or more input signals related to the target component are extracted from the input signal for the logic simulation or the input signal of the logic simulation result, and the input signal or the interval of each change point between the input signals is set to the maximum of the target component. The delay time is changed to about the delay time or more, and on the other hand, a single product is generated from the entire logic circuit of the electronic device to generate a single logic circuit for the target component, and the changed input signal and the single logic are changed. Perform re-logic simulation by the circuit, extract the input signal and output signal of the target component from the result, Input data of the operation check test a person,
This is accomplished by compiling the latter as an expected value for the observations of the test.

That is, the input signal of the target component is extracted from the result of the logic simulation using the input signal for the logic simulation set from the logic operation for each component, and the edit is performed based on the maximum delay time. Re-logic simulation is performed on the target component that has been digitized. Alternatively, the input signal of the target component is extracted from the input signal for the logic simulation set from the logic operation for each component, and the maximum delay time is directly edited to perform the re-logic simulation on the target component that has been singulated.

According to this, the creation of the test data using the logic simulation result can be realized without any human intervention. In addition, since the cut processing for the connection of the internal circuit can be performed by the single processing, the accurate result of the logic simulation can be acquired even in the case of the complicated circuit configuration, and the quality of the inspection can be improved.

Further, for the input signal and the output signal of the logic simulation and the re-logic simulation, the input / output signal of the input / output pin is extracted as the input signal or the output signal based on the switching condition during operation. It has an effect that it can be applied to a component structure having a dual-purpose pin.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration diagram of a test data creation device according to an embodiment. In this device, in order to eliminate the contradiction when the logic simulation result is used as it is, the test data creation device main body 2
As a function of a central processing unit (CPU) that configures 00,
Re-logic simulation input signal editing unit 400 and re-logic simulation individualized logic circuit processing unit 500
The feature is that the re-logic simulation execution unit 600 is added. The configuration and operation of the test data creation device will be described below.

The logic diagram input section 100 inputs the whole logic diagram 120 of the device (for example, a printed board unit) on which the test data generation target component is mounted, and generates the logic connection information file 130. This includes the designation information 110 of the target component for which the test data is created. In addition,
The unit of the component in this embodiment is determined from the testability, and each component has a signal input pin and an output pin or an input / output pin.

The logic simulation executing unit 300 uses the logic simulation input signal file 140, the logic connection information file 130, the software modeler file 210 that describes the operation of the parts in software, and the hardware modeler 220 that uses the actual parts, based on the logic. The simulation is executed and the result is stored in the logical simulation result file 310. In the logic simulation input signal file 140, the input signal of the device, that is, the input signal of the component directly connected to the input end of the device is registered.

The re-logic simulation input signal editing unit 400 extracts the input signal name, output signal name, and input / output signal name of the target component from the logic simulation result file 310, and inputs / outputs / inputs / outputs the target component. It is stored in the signal information file 410.

Here, when the target component has an input / output signal terminal, it is necessary to determine the input state / output state of the input / output signal, and the input / output signal input state / output state switching condition is set for each component. The input / output switching condition file 330 and the logical connection information file 130 which are registered are referred to, and the input signal of the input / output signal is extracted based on the file and the file 410
To store.

The re-logic simulation input signal editing section 400 edits the extracted input signal of the target component as described later in consideration of the delay characteristics of the component and the operation timing (test rate, skew, etc.) of the tester. It is stored in the input signal file 510 for re-logic simulation.

The relogic simulation single logic circuit processing section 500 creates a logic circuit that is limited to the target component from the logic connection information file 130, that is, creates a single logic circuit, that is, logic simulation logic connection information, and uses it for relogic simulation. Stored in the logical connection information file 520. The re-logic simulation execution unit 600 executes the logic simulation based on the logic connection information and the input signal for the re-logic simulation, and stores the result in the re-logic simulation result file 610.

The test data editing unit 700 extracts the input signal, the output signal, and the input / output signal of the target component from the re-logic simulation result based on the information of the input / output / input / output signal information file 410, and inputs the input signal and the input signal. For the input / output signal of the state, as the input signal of the tester, and for the output signal and the input / output signal of the output state,
The observed value of the tester output is edited as an expected value to be evaluated and stored in the operation confirmation test data file 710.

FIG. 3 is a flow chart showing a schematic processing procedure of the test data creating apparatus. In step S1, the entire logical diagram of the device mounted on the printed board is input (S11), and the target component for which test data needs to be created is designated (S12). All parts of the apparatus may be designated as the target parts.

In step S2, an input signal of the logic simulation, that is, an input signal of the apparatus is given to a software modeler in which the input entire logic diagram and the operation of the parts are described in software, and a hardware modeler using actual parts. Perform a logical simulation.

In step S3, an input signal for re-logic simulation is generated from the logic simulation result of S2. That is, the input signal of the target component is extracted (S2
1) The input signal or the interval of each change point between the input signals is extended to the maximum delay time tm of the target component or more and edited (S22).

According to the test data, since the subsequent input change is not given while the output response due to the previous input change is not obtained, the operation of the tester does not become inconsistent. Further, in order to achieve matching with the tester operation, the relationship of tm <ts is required, but the normal tester operation is slower than the operation of parts, and this relationship is maintained. As a result, the expected value of the logic simulation result matches the observed value of the tester for normal parts,
It is possible to check the operation of parts.

In step S4, a logic circuit for re-logic simulation, which is made into a single target component, is generated from the entire logic diagram. What happens is that if the input signal is given to the target component (logic circuit) in the connected state with the entire logic circuit and the re-logic simulation is executed, it may be affected by other components until the input signal propagates to the target component. This is because the propagation delay causes a shift in the change point of the input signal edited based on the maximum delay time of the target component. The generation of the logic circuit that is made into a single piece for the target component will be described later.

In step S5, the logic circuit limited to the target component is supplied with the input signal for the logic simulation generated in step S3, and the relogic simulation is executed. Then, in step S6, the input signal and the output signal of the target component are extracted based on the result of the re-logic simulation and edited into the operation confirmation test data. The operation test of each component is executed by the in-circuit tester by using this operation confirmation test data.

Each step will be described in detail below. Figure 4
Shows an example of the entire logical diagram of the device and the data structure of its logical connection information file. Overall logical diagram 12 of FIG.
At 0, the parts A, B, and
The component C is connected.

The logical connection information file 130 shown in FIG.
In the table, a pin for each component, an attribute indicating input pin / output pin / input / output pin by I, O, and B, and a pin connection signal name are stored via the logic diagram input unit 100. For pin numbers having the same connection signal, one has an input connection and the other has an output connection.
Further, when the component for which the test data is to be created is designated, “necessary” is set in the test data creation necessity information column of the logical connection information file 130.

FIG. 5 is an explanatory diagram showing the operation of the logic simulation executing section. First, logical connection information file 1
All signal names and attributes of each component of the entire logic diagram are extracted from 30, and the input and output signal names of the device are extracted from them.

Next, from the logic simulation input signal file 140, the signal name A1-, which is the input signal of the device, is input.
P, A2-P and the input signal are extracted, and the extracted A1-P,
The signal waveform of A2-P is used as an input signal for logic simulation, a logic simulation is executed by a model consisting of the software modeler file 210, the hardware modeler file 220, or a combination thereof, and the result is output to the logic simulation result file 310. Be done.

Logical simulation result file 310
In, the input signal and output signal of the device and the input signal waveforms and output signal waveforms of all parts mounted in the device are stored in correspondence with the signal names of the parts. Furthermore, the signal propagation time of each component is calculated from the result of the logic simulation, and the maximum delay time is stored for each component name. If the maximum delay time tm is known as in the case of commercially available parts, it may be registered in the logical connection information file 130 in advance.

FIG. 6 is an explanatory diagram of the propagation delay. As shown in FIG. 3A, the component B is a cell D including an OR element.
And a composite circuit of a cell E composed of a BUF element and an AND element, the component B has a plurality of signal propagation paths as shown in FIG. That is, the first pin of the component-element A-
Propagation path A by the 5th pin of the part, Propagation path B by the 2nd pin of the part-Element A-Pin 5 of the part, Propagation path C by the 3rd pin of element-Element B-Element C-Pin 6 of the part , The component 4th pin to the element C to the 6th component pin exist the propagation path D. Each path has a different delay time from the input to the output due to the difference in included element ready, and the maximum delay time of all the propagation paths is registered as the maximum delay time of the component B.

FIG. 7 is an explanatory diagram showing details of the operation of the re-logic simulation input signal editing unit. The re-logic simulation input signal editing unit 400 extracts the signal name and attribute of the target component from the logical connection information file 130,
It is stored in the input / output / input / output signal information file 410 (S311).

In this example, IN of attribute I is used as an input signal.
1, IN2, OUT1 and OUT of attribute O as output signals
2. BUS1 and BUS2 of attribute B are extracted as input / output signals. When the extraction signal of the target part includes the input / output signal of attribute B, the input / output switching condition file 33
Switching conditions for input / output signals of the target component are extracted from 0 and stored in the file 410 (S312). In this example, the input / output switching condition for the input / output signal BUS1 is I
(IN1 1) and the input / output switching condition for BUS2 is O (IN2 0), which will be described in detail later.

Further, based on the signal name and the input / output switching condition registered in the file 410, the input pin of the target component and the input / output pin in the input state are selected from the logical simulation result file 310 after the execution of the logical simulation. The input signal is extracted and stored in the file 410 (S
313).

FIG. 8 is an explanatory diagram of the input / output switching operation of the input / output pins of the component. In FIG. 3A, the input / output signal E of the component changes to the input state or the output state according to the condition of the input signal D. For example, when the input signal D is 0, the input / output signal E is in the output state, and when the input signal D is 1,
The input / output signal E is in the input state.

The switching condition of the input / output signal E is shown in FIG. The description content of the switching condition defines the condition for the input state (In) or the output state (Out) for the input / output pin number of the component. At this time, when the condition of the input state is designated, it means that the output state is obtained except for the condition. On the contrary, when the condition of the output state is designated, it means that the condition is the input state except the condition. This description is
It is stored in the input / output switching condition column of the file 410.

Next, the maximum delay time tm of the target component is fetched from the logic simulation result file 310 (S
321), edit the input signal waveform of the file 410 or the interval of each change point between waveforms so as to be the maximum delay time tm or more, and store it in the re-logic simulation input signal file 510 (S322). In addition,
Depending on the switching condition, the input / output signal in the input state extends the change point of its waveform similarly to the change points of other input signals.

FIG. 9 is an explanatory diagram showing the operation of the single circuit processing unit for re-logic simulation. In order to create the test data of the target component alone, it is necessary to apply the re-logic simulation input signal to the input of the target component.
At this time, when the target component is connected to the device, that is, when a logic simulation is performed on a logic circuit in which other components are connected to the input pin and the output pin, the propagation delay due to the influence of the other components is caused. Included, matching with TES timing specifications is no longer guaranteed. Therefore, according to the procedure of steps S41 to S47, other components are excluded from the input / output of the target component, and a single logic circuit is generated for the relogic simulation.

FIG. 10 shows a connection state of target parts mounted on the apparatus and a logic circuit for re-logic simulation excluding other parts. Target part B as shown in FIG.
In addition to the component A, the power supply Vcc 252, the self-connection connection 254 including the internal circuit and the loop connection 255 by the internal circuit, the simulation hardware modeler is also connected to the input side thereof. The component C and the software modeler are connected to the output side.

Therefore, the input / output state information of the target component is extracted from the logical connection information file 130 (S41), and the logic circuit in which only the target component is singulated is generated by the procedure of steps S42 to S47.

The input / output state information is a state in which the input of the target component is directly connected to Vcc or GND, a state in which the same signal is connected to a plurality of inputs of the target component (self-connection), an output of the target component. Is connected to the input of the target component again via another component (loop connection), the input or output of the target component is connected to the software modeler or the hardware modeler, and the like.

The extraction of the input / output state information is obtained from the connection signal of the logical connection information file 130. For example, the status information of the self-connection connection is a status in which one signal is a plurality of inputs of the target component, and can be extracted by checking the names of all signals connected to the inputs of the target component. In addition, the status information of the loop connection is the status that the output of the target component becomes the input of the target component directly or through another component, and the connection destinations are traced one after another based on the output signal name of the target component. Then, it can be extracted by checking whether the result is connected to the input of the target component.

Next, among the inputs of the target parts, Vcc and GN
The input directly connected to D is left unchanged (S4
2, S43). During the logic simulation, the Vcc input is fixed to the High level and the GND input is fixed to the Low level. In addition, the self-wired input is directly connected to the input of the apparatus by excluding its internal circuit (including the software modeler / hardware modeler) (S4).
4).

If there is a loop connection, the operation of the tester is slow and cannot follow the signal change on the gate loop path, and the output becomes unstable at the time of confirming the operation, and a normal test cannot be performed. Therefore, the input / output of the loop connection is extracted, the loop is cut, and the input side of the cut loop is always instructed to apply the uncertain value X ′, and the output side is instructed to perform the mask processing by the tester (S45). Further, the input and output in which the target component is connected to another component and its internal circuit are directly connected to the input and output of the device (S46).

The logical connection information of the single target component whose connection has been changed in this way is stored in the re-logical simulation logical connection information file 520 (S47). Figure 10 (b)
Fig. 1 shows a schematic diagram of a logic circuit based on connection information that is made into a single target component.

FIG. 11 is an explanatory diagram showing the operation of the re-logic simulation executing section. The signal name and attribute of the target component limited to a single product are extracted from the re-logical simulation logical connection information file 520 (S51). At this time, the input signal and the output signal of the target component limited to a single item become the input signal and the output signal of the device, respectively.

Next, the input signal for re-logic simulation of the target component and the value of the uncertain value X'are extracted from the re-logic simulation input signal file 510 (S5).
2, S53). This input signal, after the circuit stabilization by the input signal of the previous timing (after the maximum delay time of the target component),
The change point of the input is delayed so that the input signal of the later timing is applied. Further, when the original connection information of the target component does not include the loop connection, the uncertain value X'is unnecessary.

FIG. 12 is an explanatory diagram showing the operation of the test data editing unit. The test data editing unit 700
The input signal name, output signal name, and input / output signal name of the target component are extracted from the output / input / output signal information file 410 (S
61), if there is an input / output signal name, the input / output switching condition is also extracted (S62).

Next, the input signal of each input pin of the target component and the input / output signal in the input state when the target component has input / output pins are extracted from the re-logic simulation result file 610 (S63, S64). . Similarly, the output signal of each output pin of the target component and the input / output signal in the output state when there is an input / output pin are extracted from the re-logic simulation result file 610 (S65, S66).

The input signal and the input / output signal in the input state thus extracted are used as the input signals that the tester gives to the input terminal of the device, and the output signals and the input / output signals in the output state are input to the device by the tester. The output signal from the output terminal is edited as an expected value signal for observation and stored in the operation confirmation test data file 710.

FIG. 13 is an explanatory diagram showing a concrete operation example of the test data generating apparatus according to the present embodiment. The operation of the re-logic simulation will be described with an application example to the same target component (FIG. 2) used to explain the conventional problem.

(A) is the input signals A and B of the target component extracted from the logic simulation result, and reflects only the logical operation of each component that sequentially responds to the signal input to the device. Next, the change points A1 and A2 of the input signal A and the change points B1 and B2 of the input signal B are delayed relative to the previous change point by the maximum change time tm of the target component. (C) shows the input signal A after delaying each change point,
The waveform of B is shown. Change points A1 and B1, B1 and A
2, the interval between A2 and B2 is set to the maximum delay time tm.

The re-logic simulation is executed by using the input signals A and B as inputs of the target component (OR element) which has been singulated. (E) shows the re-logic simulation result. When the input signal A rises at the change point A1,
The output signal C rises at the change point C1 with a delay td of the OR element. Since tm> td is set here, the input signal B changes (B1) after the output signal C changes (C1).

Therefore, when the extraction point is set immediately before the change of the input signal and the input signal and the output signal are extracted from the re-logic simulation result file (e), the logical value of A becomes as shown in (g). The logical value of [110] and B is [011], and the logical value of C is [111]. That is, the input A, B is 1.0, the output C is 1, and the input A, B
The output C is 1 while the B is 1.1.

(H) shows the operation of the tester. The input signals A and B are input by extending the logic value obtained by the re-logic simulation to a tester rate (here, 4 μs) sufficiently larger than the maximum delay time tm (order of ns). The output C rises with a delay of the element delay td.

At this time, since the observed value of the tester is detected at a timing delayed by the tester skew (ts), the observed value of C becomes 1 at the first observation timing and becomes 1 at the next observation timing, and the re-logic simulation is performed. Matches the resulting logical value 1/1. In other words, the correct operation confirmation test data has been created.

In the embodiment described above, the input signal extracted from the result of the logic simulation is edited based on the maximum delay time, and the edited input signal is limited to the logic circuit of the target component that has been singulated. We are performing re-logic simulation. However, if the input signal corresponding to the logical operation of each part is set by referring to past data, etc., immediately extract the input signal of the target part, edit it based on the maximum delay time, and make it a single product. You may make it perform the logic simulation limited to the logic circuit of the processed target component.

Further, the logic simulation unit in the above embodiment can be configured to be used also for re-logic simulation.

[0068]

According to the present invention, the interval of each change point between the input signals of the logic simulation result is changed to the maximum delay time of the target component or more, and the re-logic simulation is executed by the changed input signal. Since the test data for operation confirmation is generated directly from the result, no human intervention is required.

Further, in the re-logic simulation, the target component mounted on the device such as the printed circuit board is singulated so as to eliminate the influence of other components.
The result of the re-logic simulation in which the maximum delay time is taken into consideration can be accurately acquired, and the quality of inspection can be improved.
For example, since it is possible to realize a single product for loop connection, there is an effect that it can be applied to a complicated circuit configuration.

Further, for the input signal and the output signal of the logic simulation and the re-logic simulation, the input / output signal of the input / output pin is extracted as the input signal or the output signal based on the switching condition during operation. There is also an effect that it can be applied to a configuration having dual-purpose input / output pins.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a test data creation device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a problem in the conventional test data creating method.

FIG. 3 is a flowchart showing a test data creating method according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of an overall logic diagram and a file configuration of its logical connection information.

FIG. 5 is an explanatory diagram showing the operation of a logic simulation execution unit.

6A and 6B are a logical diagram of a target component including a plurality of elements and an explanatory diagram showing a state of element delay in a propagation path thereof.

FIG. 7 is an explanatory diagram showing an operation of a relogic simulation input signal editing unit.

FIG. 8 is an explanatory diagram showing an input / output switching operation of input / output pins of a component and switching conditions.

FIG. 9 is an explanatory diagram showing an individualization processing operation of the individualization circuit processing unit for re-logic simulation.

FIG. 10 is a logic circuit diagram showing the target component before and after the individualizing process.

FIG. 11 is an explanatory diagram showing the operation of the re-logic simulation execution unit.

FIG. 12 is an explanatory diagram showing the operation of the test data editing unit.

FIG. 13 is an explanatory diagram showing a specific operation example of the test data creation device.

[Explanation of symbols]

100 ... Logical diagram input section, 110 ... Target part designation section, 1
20 ... Logical diagram, 130 ... Logical connection information file, 140
... input signal file for logic simulation, 200 ...
Test data creation device main body (CPU), 210 ... Software modeler file, 220 ... Hardware modeler,
300 ... Logic simulation executing unit, 310 ... Logic simulation result file, 330 ... Input / output switching condition file, 400 ... Re-logic simulation input signal editing unit, 410 ... Target component input / output / input / output information file, 500 ... Re Single logic circuit processing unit for logic simulation, 510 ... Input signal file for relogic simulation, 520 ... Logical connection information file for relogic simulation, 600 ... Relogic simulation execution unit, 610 ... Relogic simulation result file, 7
00 ... Test data editing unit, 710 ... Operation test test data file.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Sakakibara 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Keiyo Nimura 5-chome, Omika-cho, Hitachi-shi, Ibaraki 2-1 Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Toshiaki Kawamura 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Junya Tajima Ibaraki Prefecture 5-2-1 Omika-cho, Hitachi City, Hitachi Omika Plant, Ltd. (56) Reference JP-A-8-179956 (JP, A) JP-A-4-308942 (JP, A) JP-A-5-307070 (JP, a) JP flat 3-102270 (JP, a) (58 ) investigated the field (Int.Cl. ^7, DB ) G01R 31/3183 G01R 31/28 G06F 17/50 670

Claims (5)

(57) [Claims] 1. A method for performing a logic simulation of an electronic device equipped with a component and using the result to create test data for confirming the operation of each target component by a tester, the stored logic simulation. One or more input signals to be input to the target component are extracted from the input signal for use, and the interval between the input signals or the change points between the input signals is changed to the maximum delay time or more specific to the target component or more. A predetermined connection showing the entire logic circuit of the electronic device
I / O status of the target part is extracted from the
It is connected to the power supply (Vcc) and the ground (GND) from the state.
Inputs and outputs are left as they are and connected to other parts.
Input and output are directly with the input and output of the electronic device
Connect to and create a single logic circuit for the target part
Performing singularization processing, performing logic simulation by the logic circuit that has been singulated by the changed input signal, extract the input signal and output signal of the target component from the result, the former input data of the operation confirmation test , A method of creating test data, characterized in that the latter is edited as an expected value for the observation result of the test. 2. The singularization process according to claim 1, wherein an input in which the target component is self-connected through an internal circuit or an input or output connected to another component excludes the internal circuit. Then, the test data is generated so as to be directly connected to the input or output of the electronic device. 3. The singularization process according to claim 1 , wherein, when the target component is connected through an internal circuit between an input and an output, the internal circuit is cut, and the input is fixed to the input. A method of creating test data, characterized in that an application of a definite value signal is instructed and the output is provided so as to give a mask instruction in the tester. 4. The input / output signal of an input / output dual-purpose pin according to claim 1, wherein an input / output switching condition is given in advance when the results of the logic simulation and the re-logic simulation are edited. A method of creating test data, characterized by extracting as an input signal or an output signal based on a condition. 5. A logical connection information file of a logical diagram of an electronic device on which a component is mounted, an input signal file for logic simulation in which an input signal of the device is registered, and logical connection information and input of a designated target component. In a test data creation device that includes a logic simulation execution unit that extracts a signal and executes a logic simulation, and edits into test data that confirms the operation of each target component by using the result of this logic simulation, An input signal editing unit that extracts the input signal of the target component from the result and changes the time interval of the input signal or the change point between the input signals to be equal to or longer than the maximum delay time of the target component, and the logical connection information file of the logical diagram. Refer to at least remove the internal circuit of self-connection or
And a single logic processing unit that cuts the loop connection to generate a single logic circuit for the target component, and a relogic simulation that performs the relogic simulation by applying the changed input signal to the single logic circuit. And a test data editing unit that uses the input signal and the output signal extracted from the result of the re-logic simulation as test data of the operation confirmation tester.