JP2718076B2 - Method for manufacturing group III-V compound semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a group III-V compound semiconductor device, and more particularly to a method for manufacturing a complementary field effect transistor.

[Prior art] III-V compound semiconductor materials such as GaAs are:
It has the feature that the mobility of electrons is higher than that of conventional Si, and the significance of forming an ultrahigh-speed integrated circuit using this material is extremely large. In the case of configuring such an ultra-high-speed integrated circuit, MESFETs (Metas) as shown in FIG.
l Semiconductor Field Effect Transistor). In this MESFET, a semiconductor layer 2 having conductivity is formed on a semi-insulating substrate 1, and a Schottky electrode 3 serving as a gate is disposed thereon, and two ohmic electrodes 4 serving as a source and a drain are disposed on both sides thereof. It has a structure. In order to reduce the parasitic resistance of the element, a structure having a semiconductor region 5 in which impurities are introduced at a high concentration under two ohmic electrodes as shown in FIG. 3B is widely used.

When a large-scale integrated circuit using the MESFET is constructed, an FET having an n-type layer as a channel (n-channel FET) and an FET having a p-type layer as a channel (p-channel FE)
The use of a complementary circuit combining T) is advantageous for reducing power consumption. FIG. 4 is a diagram showing an inverter using a complementary circuit. The gates of two n-channel FETs 13 and 14 are an input terminal 15, a drain is an output terminal 16, and a source of the n-channel FET is a ground terminal 17. , P
This is a circuit in which the source of the channel FET is connected to the power supply terminal 18.

When configuring a complementary circuit using the MESFET,
This can be achieved by manufacturing an FET in which a region into which an n-type impurity and a p-type impurity are ion-implanted as described below is used as an operation layer. 5 (a) to 5 (f) are cross-sectional views of a substrate showing this manufacturing method in the order of steps.

An n-type impurity such as Si is ion-implanted into a semi-insulating GaAs substrate 521 using a photoresist 522a having an opening only in a desired region as a mask to form an operation layer 528 of an n-channel FET (FIG. 5A).

P-type impurities such as Mg are ion-implanted using a photoresist 522b having an opening in another region as a mask to form a p-channel FET.
(FIG. 5 (b)).

Subsequently, a high melting point metal such as WSi is deposited on the surface of the substrate 521,
Processing is performed by reactive ion etching to form a gate Schottky electrode 525 (FIG. 5C).

Using the photoresist 522c having the gate electrode 525 and the n-channel FET region opened as a mask, an n-type impurity such as Si is ion-implanted to form a high-concentration n-type region 526 (FIG. 5D).

In addition, a p-type impurity such as Mg is ion-implanted using the photoresist 522d in which the gate electrode 525 and the p-channel FET region are opened to form a high-concentration p-type region 538 (FIG. 5E). Next, heat treatment is performed by covering the entire surface with a protective film such as SiN to activate the ion-implanted impurities. Finally, ohmic electrodes 532 are deposited on both sides of the Schottky electrode 525, and heat treatment for alloying is performed to complete the device (FIG. 5 (f)). With this manufacturing method, complementary ME
It is possible to manufacture SFET circuits.

[Problems to be Solved by the Invention] However, in the above method, p-type impurities such as Mg and Be which are usually ion-implanted have a large diffusion and spread inside the substrate during the heat treatment. There is a problem that the characteristics of the manufactured device are deteriorated.

The present invention solves such a conventional problem, suppresses the spread of the operation layer of the p-channel FET, and forms n-channel and p-channel FETs using the FET on the same substrate.
It is an object of the present invention to provide a method for manufacturing a group V compound semiconductor device.

[Means for Solving the Problems] The present invention comprises a step of forming a semiconductor layer in which Si atoms are introduced as impurities on a substrate, and a step of forming a semiconductor layer in a desired region of the semiconductor layer.
Performing a heat treatment by ion-implanting group I atoms to invert the conductivity type of the ion-implanted region, and forming a Schottky electrode on the surface of each region having a different conductivity type and ohmic electrodes on both sides of the Schottky electrode, respectively And a method of manufacturing a group III-V compound semiconductor device.

[Operation] The operation of the present invention will be described below in the case where GaAs is used as the III-V group compound semiconductor layer, Si is used as the group IV impurity atom, and Ga is used as the ion-implanted element.

FIG. 6 shows that Si was converted to 5 × 10 ¹² cm ⁻² and 5 × 10 ¹³ cm at 120 keV.
After ion implantation of Ga at 340 keV into GaAs implanted at cm ^-2 and heat treatment, the sheet carrier concentration and mobility
This shows the dose dependence of Ga ions (Preprints of the 48th Annual Meeting of the Japan Society of Applied Physics, 848 pages, lecture number 19p-ZD-5). In the figure, ○ and Δ indicate Si, respectively.
5 shows the case where the ion implantation amounts of 5 × 10 ¹² cm ⁻² and 5 × 10 ¹³ cm ⁻² , A shows the sheet carrier concentration, and B shows the mobility. As can be seen from the figure, the Ga dose amount is 1
At x10 ¹⁴ cm ^-2 or more, inversion of Si-doped GaAs from n-type (solid line in the figure) to p-type (dashed line in the figure) is observed.

The present invention utilizes this phenomenon, and taking the above case as an example, Ga is ion-implanted into the Si-doped n-type GaAs channel layer in the region where the p-channel FET is formed, and then heat treatment is performed. Si-doped n-type GaAs in Ga ion implantation region
Since only the layers are inverted to p-type, it is possible to manufacture n-channel and p-channel FETs on the same substrate.
At this time, the p-type impurity is Si having a smaller diffusion than that of the conventional p-type impurity. Therefore, the spread of the operation layer is small, and a high-performance p-channel FET can be manufactured.

EXAMPLES Hereinafter, examples of the present invention will be described in which the III-V compound semiconductor is GaAs and the group IV impurity element is Si.

1A to 1E are cross-sectional views of a substrate showing a method of manufacturing the first embodiment of the present invention in the order of steps. N-channel FET and p-channel FET on semi-insulating GaAs substrate 121
Si is ion-implanted using a photoresist 122a having an opening in a region for fabricating a Si to form a Si-implanted GaAs layer 123 (FIG. 1A).

Then, Ga is ion-implanted into a region where a p-channel FET is to be formed using the photoresist 122b as a mask, and Ga, Si-implanted GaAs is used.
An s layer 124 is formed (FIG. 1B).

Subsequently, a high melting point metal such as WSi is deposited on the surface of the substrate 121,
Processing is performed by reactive ion etching to form a Schottky electrode 125 for the gate (FIG. 1 (c)).

A photoresist 122c having an opening in the region for forming the gate electrode 125 and the n-channel FET and the p-channel FET
Si is ion-implanted using as a mask, and a high-concentration Si-implanted GaAs layer 126 is formed.
Is formed (FIG. 1 (d)).

Further, Ga is ion-implanted using the photoresist 122d and the gate electrode 125 having an opening in a region where a p-channel FET is to be formed as a mask to form a high concentration Ga, Si implanted GaAs layer 127 (FIG. 1E).

Next, after the resist 122d is removed, a heat treatment is performed by covering the entire surface with SiN to activate the ion-implanted impurities. By this heat treatment, the regions 123 and 126 into which only Si is implanted show n-type conductivity, and the n-type GaAs layer 123 serving as an operation layer and the high-concentration n-type region 126 for reducing parasitic resistance are formed.
The regions 124 and 127 into which Si and Ga have been implanted exhibit p-type conductivity, and the p-type GaAs layer 124 and the high-concentration p-type region 127 serving as an operation layer are formed. Finally, ohmic electrodes 132 are deposited on both sides of the Schottky electrode 125 and heat treatment for alloying is performed to complete the device (FIG. 1 (f)).

Through the above steps, it has become possible to manufacture a complementary MESFET circuit while suppressing the spread of the operation layer of the p-channel FET.

2 (a) to 2 (g) are cross-sectional views of a substrate showing a method of manufacturing the second embodiment of the present invention in the order of steps. First, a non-doped GaAs buffer layer 233 and a Si-doped n-type GaAs layer 234 are grown in this order on a semi-insulating GaAs substrate 221 by molecular beam epitaxy (FIG. 2A).

Subsequently, in order to electrically isolate adjacent FETs, oxygen is ion-implanted into a region between the FETs using the photoresist 222a as a mask to form an oxygen-implanted GaAs layer 235 which is a semi-insulating region (FIG. 2 ( b)).

Further, Ga is ion-implanted using a photoresist 222b having an opening in a region for forming a p-channel FET as a mask, and Ga-implanted Si is
A doped GaAs layer 236 is formed (FIG. 2C).

Next, after removing the resist 222b, a high melting point metal such as WSi is deposited on the surface and processed by reactive ion etching,
A Schottky electrode 225 for the gate is formed (FIG. 2D).

The gate electrode 225 and a photoresist 222c having an opening in a region for forming an n-channel FET and a p-channel FET
Si is ion-implanted using as a mask, and the high-concentration Si-implanted GaAs layer 226
Is formed (FIG. 2 (e)).

Further, Ga is ion-implanted using the photoresist 222d and the gate electrode 225 having an opening in a region where a p-channel FET is to be formed as a mask to form a high concentration Ga, Si implanted GaAs layer 227 (FIG. 2 (f)).

Next, after the resist 222d is removed, a heat treatment is performed by covering the entire surface with SiN to activate the ion-implanted impurities. By this heat treatment, the region 226 into which only Si is implanted exhibits n-type conductivity, and a high-concentration n-type layer 226 for reducing parasitic resistance is formed. In the region 234 where neither Ga nor oxygen is ion-implanted, n-type conductivity is maintained, and an n-channel FET is formed.
Operation layer. Further, the region 236 in which Ga is ion-implanted in the Si-doped GaAs layer 234 and the region 227 in which Si and Ga are implanted show p-type conductivity, and the p-type GaAs layer 236 and the high-concentration p-type It is formed. Finally, ohmic electrodes 232 are deposited on both sides of the Schottky electrode 225, and a heat treatment for alloying is performed to complete the device (FIG. 2 (g)).

Through the above steps, it has become possible to manufacture a complementary MESFET circuit while suppressing the spread of the operation layer of the p-channel FET. Furthermore, since the device manufactured according to this embodiment can form a high-concentration thin-film operating layer by molecular beam epitaxy, the gate length can be reduced while suppressing the short channel effect.
High performance complementary MESFET integrated circuits can be manufactured.

[Effects of the Invention] As described above, according to the present invention, it is possible to manufacture a complementary MESFET integrated circuit while suppressing diffusion of a p-type impurity. Has become possible.

[Brief description of the drawings]

1 and 2 are sectional views of a substrate showing an embodiment of the present invention in the order of steps, FIG. 3 is a sectional view of a substrate showing the structure of a MESFET, and FIG. 4 is a circuit showing an inverter using a complementary FET. FIG. 5, FIG. 5 is a cross-sectional view of a substrate showing a manufacturing method according to a conventional example in the order of steps, and FIG. 6 is a diagram showing the relationship between carrier surface density and mobility when Ga is ion-implanted into GaAs into which Si is ion-implanted. It is. DESCRIPTION OF SYMBOLS 1 ... Semi-insulating substrate 2 ... Conductive semiconductor layer 3,125,225,525 ... Schottky electrode 4,132,232,532 ... Ohmic electrode 5 ... Highly doped semiconductor region 13 ... n-channel FET 14 ... p-channel FET 15 ... input terminal 16 ... Output terminal 17 ... Ground terminal 18 ... Power supply terminal 121,221,521 ... Semi-insulating GaAs substrate 122a-d, 222a-d, 522a-d ... Photoresist 123,528 ... Si implanted GaAs layer 124 ... Ga, Si-implanted GaAs layer 126,226,526 ... High-concentration Si-implanted GaAs layer 127,227 ... High-concentration Ga, Si-implanted GaAs layer 233 ... Non-doped GaAs layer 234 ... Si-doped GaAs layer 235 ... Oxygen-implanted GaAs layer 236 ... Ga-implanted Si Doped GaAs layer 537… Mg implanted GaAs layer 538 …… High concentration Mg implanted GaAs layer

Claims (1)

(57) [Claims] 1. A step of forming a semiconductor layer in which Si atoms are introduced as impurities on a substrate, and forming a semiconductor layer in a desired region of the semiconductor layer.
Performing a heat treatment by ion-implanting group I atoms to invert the conductivity type of the ion-implanted region, and forming a Schottky electrode on the surface of each region having a different conductivity type and ohmic electrodes on both sides of the Schottky electrode, respectively And a method of manufacturing a group III-V compound semiconductor device.