JP2769517B2 - Manufacturing method of hybrid integrated circuit - Google Patents
Manufacturing method of hybrid integrated circuitInfo
- Publication number
- JP2769517B2 JP2769517B2 JP2035482A JP3548290A JP2769517B2 JP 2769517 B2 JP2769517 B2 JP 2769517B2 JP 2035482 A JP2035482 A JP 2035482A JP 3548290 A JP3548290 A JP 3548290A JP 2769517 B2 JP2769517 B2 JP 2769517B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- trimming
- pad
- resistor
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title description 4
- 238000009966 trimming Methods 0.000 claims description 27
- 239000000523 sample Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 12
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
【発明の詳細な説明】 「産業上の利用分野」 この発明は抵抗体の抵抗値を調整するトリミングを伴
う混成集積回路の製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit with trimming for adjusting the resistance value of a resistor.
「従来の技術」 例えば第3図に示すように絶縁基板11上に回路12と回
路13とが直列に接続されたものが混成集積回路として作
られ、これを図に示してないが配線基板に装着して、回
路12の入力端子のパッド14に接続されたリード線15が配
線基板の配線に接続され、回路13の出力端子のパッド16
に接続されたリード線17が配線基板の配線に接続されて
実際に使用される。リード線15,16にはそれぞれ配線基
板の配線容量18,19が付加される。[Prior Art] For example, as shown in FIG. 3, a circuit in which a circuit 12 and a circuit 13 are connected in series on an insulating substrate 11 is formed as a hybrid integrated circuit. The lead wire 15 connected to the input terminal pad 14 of the circuit 12 is connected to the wiring of the wiring board, and the output terminal pad 16 of the circuit 13 is mounted.
Are connected to the wiring of the wiring board and are actually used. Wiring capacitances 18, 19 of the wiring board are added to the lead wires 15, 16, respectively.
このような混成集積回路の製造に当り、第4図に示す
ようにパッド14,16にそれぞれリード線15,17を接続して
いない状態で、基板11をステージ(図示せず)上に配置
し、プローブカード21をその開口22内に基板11が位置す
るように設け、プローブカード21に取付けたプローブ2
3,24,25をパッド14,16及び補助パッド26に接触させる。
補助パッド26は第5図に示すように回路12と回路13との
接続点に接続されて基板11上に形成され、トリミングに
利用されるものであり、リード線は接続されない。プロ
ーブカード21のコネクタ部27を図に示していない測定系
に接続して次のようなトリミングを行っていた。In manufacturing such a hybrid integrated circuit, the substrate 11 is placed on a stage (not shown) with the leads 15 and 17 not connected to the pads 14 and 16 respectively, as shown in FIG. , A probe card 21 is provided so that the substrate 11 is located in the opening 22 thereof, and the probe 2 attached to the probe card 21 is provided.
3, 24, 25 are brought into contact with the pads 14, 16 and the auxiliary pad 26.
The auxiliary pad 26 is formed on the substrate 11 by being connected to the connection point between the circuit 12 and the circuit 13 as shown in FIG. 5, and is used for trimming, and the lead wire is not connected. The following trimming was performed by connecting the connector section 27 of the probe card 21 to a measurement system (not shown).
(a)パッド14に信号を与え、補助パッド26の出力を測
定して回路12の直流入出力特性を測定し、これが所定の
特性になるように、回路12内の抵抗体(図示せず)の抵
抗値をレーザカットなどによりトリミング調整する。(A) A signal is applied to the pad 14, the output of the auxiliary pad 26 is measured, and the DC input / output characteristic of the circuit 12 is measured. A resistor (not shown) in the circuit 12 is set so that the characteristic becomes a predetermined characteristic. Is adjusted by laser cutting or the like.
(b)補助パッド26に信号を与え、パッド16の出力を測
定して回路13の直流入出力特性を測定し、これが所定の
特性になるように、回路13内の抵抗体(図示せず)の抵
抗値をトリミング調整する。(B) A signal is applied to the auxiliary pad 26, the output of the pad 16 is measured, and the DC input / output characteristic of the circuit 13 is measured. A resistor (not shown) in the circuit 13 is set so that the characteristic becomes a predetermined characteristic. Trimming adjustment of the resistance value.
(c)パッド14に信号を与え、パッド16の出力を測定し
て回路12,13の全体としての高周波特性を測定して、こ
れが所定の特性となるように回路12又は/及び13内の抵
抗体の抵抗値をトリミング調整する。(C) A signal is applied to the pad 14, the output of the pad 16 is measured to measure the high-frequency characteristics of the circuits 12, 13 as a whole, and the resistance in the circuit 12 and / or 13 is adjusted so that the characteristics become predetermined. Trimming and adjusting body resistance.
「発明が解決しようとする課題」 第4図に示したトリミングの際に、第5図に示すよう
に各パッド14,16,26にはプローブから測定系までの配線
に生じる容量28,29.31がそれぞれ付加される。その入出
力容量28,29は第3図に示した実装状態で生じる容量18,
19とそれぞれ対応して問題はないが、プローブカード21
を設定した状態で前記(a)〜(c)の各トリミングを
行うため、(c)のトリミングにおいて、実装状態では
存在しない容量31が付加されたものとなっているため、
正しいトリミングを行うことができなかった。なお
(c)のトリミングの際にプローブカードを交換してパ
ッド14,16のみとプローブが接触するようにすれば、容
量31の影響を受けないが、複数のプローブカードを用意
する必要があり、かつその交換に手間がかかる欠点が生
じる。[Problems to be Solved by the Invention] At the time of trimming shown in FIG. 4, capacitances 28, 29.31 generated in the wiring from the probe to the measurement system are present in the pads 14, 16, 26 as shown in FIG. Each is added. The input / output capacitances 28 and 29 are the capacitances 18 and 29 generated in the mounting state shown in FIG.
There is no problem corresponding to 19 respectively, but probe card 21
Since the respective trimmings (a) to (c) are performed in a state where is set, the capacity 31 which does not exist in the mounted state is added in the trimming of (c).
Correct trimming could not be performed. If the probe card is replaced at the time of trimming (c) so that only the pads 14 and 16 come into contact with the probe, the capacitance 31 is not affected, but it is necessary to prepare a plurality of probe cards. Further, there is a disadvantage that the replacement is troublesome.
「課題を解決するための手段」 この発明による混成集積回路の製造方法は、絶縁基板
上に少なくとも所定の配線パターンと抵抗体と絶縁基板
の周辺にリード線が接続されるべきパッドとを形成して
回路を構成し、リード線が接続されるべき個所以外にト
リミング時に絶縁基板上にプローブが接触されるべき補
助パッドを形成し、その補助パッドとリード線が接続さ
れるべきパッドにそれぞれ測定用プローブを接触させて
抵抗体に対するトリミングを行い、その後、補助パッド
を回路から切離し、リード線が接続されるべきパッドに
測定用プローブを接触させて抵抗体に対するトリミング
を行う。[Means for Solving the Problems] A method of manufacturing a hybrid integrated circuit according to the present invention comprises forming at least a predetermined wiring pattern, a resistor, and a pad to which a lead wire is to be connected around an insulating substrate on an insulating substrate. A circuit is formed, and auxiliary pads to be contacted with the probe on the insulating substrate during trimming are formed at locations other than those where the lead wires are to be connected. The probe is contacted to perform trimming on the resistor, then the auxiliary pad is separated from the circuit, and the probe for measurement is brought into contact with a pad to which a lead wire is to be connected, to perform trimming on the resistor.
「実施例」 第1図に第5図に示した従来のものと対応するものを
この発明の方法により作る例を示す。図に示してないが
従来と同様、第4図に示したようにプローブカードを使
用して第1図Aに示す状態で、パッド14及び補助パッド
26間を利用して回路12の直流入出力特性を測定して回路
12内の抵抗体のトリミングを行い、次に補助パッド26及
びパッド16間を利用して回路13の直流入出力特性を測定
して回路13内の抵抗体のトリミングを行う。このように
補助パッド26を利用したトリミングを終了した後に、こ
の発明では第1図Bに示すように補助パッド26と回路と
の抵抗線(パターン)32を切断(33)して補助パッド26
を回路から切離す。この切断は抵抗体のトリミングに利
用したレーザを利用して行えばよい。なお図に示してい
ないがプローブカードは混成集積回路にプローブを接触
したままとする。従って補助パッド26の切離し後、直ち
にパッド14及び16間を利用して全体の周波数特性を測定
して回路12又は/及び13内の抵抗体をトリミングするこ
とができる。この周波数特性測定時には補助パッド26が
切離されているため、補助パッド26に付加されている容
量31が周波数特性の測定に影響することがなく、実装状
態とほぼ同一状態の周波数特性を測定することができ、
正しいトリミングを行うことができる。"Embodiment" FIG. 1 shows an example in which a device corresponding to the conventional device shown in FIG. 5 is produced by the method of the present invention. Although not shown in the figure, the pad 14 and the auxiliary pad are used in the state shown in FIG. 1A using a probe card as shown in FIG.
Measure the DC input / output characteristics of circuit 12 using
The resistor in the circuit 12 is trimmed, and then the DC input / output characteristics of the circuit 13 are measured using the space between the auxiliary pad 26 and the pad 16 to trim the resistor in the circuit 13. After the trimming using the auxiliary pad 26 is completed in this way, according to the present invention, as shown in FIG. 1B, the resistance line (pattern) 32 between the auxiliary pad 26 and the circuit is cut (33) and the auxiliary pad 26 is cut.
Disconnect from the circuit. This cutting may be performed using a laser used for trimming the resistor. Although not shown, the probe card keeps the probe in contact with the hybrid integrated circuit. Therefore, immediately after the separation of the auxiliary pad 26, the entire frequency characteristics can be measured by using the space between the pads 14 and 16, and the resistor in the circuit 12 and / or 13 can be trimmed. Since the auxiliary pad 26 is separated during the frequency characteristic measurement, the capacitance 31 added to the auxiliary pad 26 does not affect the measurement of the frequency characteristic, and the frequency characteristic in the almost same state as the mounted state is measured. It is possible,
Correct trimming can be performed.
上述ではこの発明をファンクショントリミングを利用
する場合に適用したが、他のトリミングを行う場合にも
適用できる。例えば第2図に示すように絶縁基板11上に
分布定数線路34,35,36が形成され、これら分布定数線路
34,35,36が抵抗体37,38,39で互いに接続され、その接続
点に補助パッド41が接続されている場合に、補助パッド
41を利用して各抵抗体37,38,39の抵抗値をそれぞれトリ
ミング調整し、その後、補助パッド41を接続部42で回路
から切離す。従って補助パッド41はこの混成集積回路の
特性に影響を与えない。特に高周波の混成集積回路にお
いては補助パッド41を残しておくと、良好な高周波特性
が得られないおそれがあるが、補助パッド41をトリミン
グの後、切離すことにより所望の特性をもつ回路とする
ことができる。In the above description, the present invention is applied to a case where function trimming is used, but the present invention can be applied to a case where other trimming is performed. For example, as shown in FIG. 2, distributed constant lines 34, 35 and 36 are formed on the insulating substrate 11, and these distributed constant lines
34, 35, 36 are connected to each other by resistors 37, 38, 39, and the auxiliary pad 41 is connected to the connection point.
The resistance value of each of the resistors 37, 38, and 39 is trimmed and adjusted using the 41, and then the auxiliary pad 41 is disconnected from the circuit at the connection section. Therefore, the auxiliary pad 41 does not affect the characteristics of the hybrid integrated circuit. Particularly in a high-frequency hybrid integrated circuit, if the auxiliary pad 41 is left, good high-frequency characteristics may not be obtained, but after trimming the auxiliary pad 41, a circuit having desired characteristics is obtained by separating the auxiliary pad 41. be able to.
なお、抵抗体に対するトリミングは必ずしもすべての
素子を基板に形成、搭載した後、行うとは限らず、抵抗
体のトリミングの後、各種素子を形成又は搭載すること
もある。Note that the trimming of the resistor is not necessarily performed after all the elements are formed and mounted on the substrate, and various elements may be formed or mounted after the trimming of the resistor.
「発明の効果」 以上述べたようにこの発明によれば抵抗体に対するト
リミングの後にそのトリミングに利用した補助パッドを
回路から切離すため、前述したように例えば実装状態に
近い状態で連続的にファンクショントリミングを行うこ
とができ、あるいは補助パッドに影響されない高周波特
性の良い混成集積回路を得ることができる。[Effects of the Invention] As described above, according to the present invention, after trimming the resistor, the auxiliary pad used for the trimming is separated from the circuit. Trimming can be performed, or a hybrid integrated circuit having good high-frequency characteristics without being affected by the auxiliary pad can be obtained.
第1図はこの発明の実施例を簡略に示す図、第2図は他
の実施例を示す図、第3図は実装状態の混成集積回路を
示す略線図、第4図はファンクショントリミングを行う
ための混成集積回路とプローブカードとの接続を示す
図、第5図はファンクショントリミングを説明するため
の混成集積回路を示す図である。1 is a diagram schematically showing an embodiment of the present invention, FIG. 2 is a diagram showing another embodiment, FIG. 3 is a schematic diagram showing a hybrid integrated circuit in a mounted state, and FIG. FIG. 5 is a diagram showing the connection between the hybrid integrated circuit and the probe card for performing the operation, and FIG. 5 is a diagram showing the hybrid integrated circuit for explaining function trimming.
Claims (1)
ンと抵抗体と上記絶縁基板の周辺にリード線が接続され
るべきパッドとを形成して回路を構成し、 上記リード線が接続されるべき個所以外にトリミング時
に上記絶縁基板上にプローブが接触されるべき補助パッ
ドを形成し、 その補助パッドと上記リード線が接続されるべきパッド
にそれぞれ測定用プローブを接触させて上記抵抗体に対
するトリミングを行い、 その後、上記補助パッドを回路から切離し、上記リード
線が接続されるべきパッドに測定用プローブを接触させ
て上記抵抗体に対するトリミングを行うことを特徴とす
る混成集積回路の製造方法。1. A circuit is formed by forming at least a predetermined wiring pattern, a resistor and a pad to which a lead wire is to be connected around the insulating substrate on an insulating substrate, and the lead wire is to be connected. An auxiliary pad with which a probe is to be contacted on the insulating substrate at the time of trimming is formed at a position other than the position, and the auxiliary probe and the pad to which the lead wire is to be connected are brought into contact with a measuring probe to trim the resistor. Performing a trimming process on the resistor by separating the auxiliary pad from the circuit, and bringing a measuring probe into contact with the pad to which the lead wire is to be connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2035482A JP2769517B2 (en) | 1990-02-16 | 1990-02-16 | Manufacturing method of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2035482A JP2769517B2 (en) | 1990-02-16 | 1990-02-16 | Manufacturing method of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03239392A JPH03239392A (en) | 1991-10-24 |
| JP2769517B2 true JP2769517B2 (en) | 1998-06-25 |
Family
ID=12442975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2035482A Expired - Lifetime JP2769517B2 (en) | 1990-02-16 | 1990-02-16 | Manufacturing method of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2769517B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6451630A (en) * | 1987-08-24 | 1989-02-27 | Hitachi Ltd | Collecting substrate for electronic device |
-
1990
- 1990-02-16 JP JP2035482A patent/JP2769517B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03239392A (en) | 1991-10-24 |
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