JP2800267B2 - Time division multiplex method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing method used for a multiplexing device, and more particularly, to a time-division multiplexing which is effective for a multiplexing device in which the speed of multiplexed data is wide. About the method.

[Prior Art] Conventionally, in this type of multiplexing method, time-division multiplexing / demultiplexing of data having various speeds is performed using an 8-bit parallel demultiplexing circuit.

[Problems to be solved by the invention]

In the conventional multiplexing method described above, since only an 8-bit parallel demultiplexing circuit is used, at least 8 bits are used for one multiplexed data. Therefore, in the case of low-speed data that can be multiplexed with 8 bits or less and data that is not a multiple of 8 bits, empty bits are generated. That is, in the case of low-speed data that can be multiplexed with bits of 8 bits or less and data that is not a multiple of 8 bits, there is a problem that the multiplexing efficiency is deteriorated.

An object of the present invention is to provide a time-division multiplexing method in which multiplexing efficiency is not deteriorated even in the case of low-speed data that can be multiplexed with 8 bits or less and data that is not a multiple of 8 bits. It is in.

[Means for solving the problem]

According to the present invention, an 8-bit parallel bus demultiplexing circuit connected to an 8-bit parallel bus, a 1-bit serial bus demultiplexing circuit connected to a 1-bit serial bus,
It is characterized by having a serial / parallel demultiplexing circuit for demultiplexing the parallel bus and the serial bus.

〔Example〕

 Hereinafter, the present invention will be described with reference to examples.

Referring to FIG. 1, an 8-bit parallel bus demultiplexing circuit section a and a 1-bit serial bus demultiplexing circuit section b interface with a plurality of data interface sections having various data rates. These demultiplexing circuits a
And b are connected to a serial / parallel demultiplexing circuit section c, and the demultiplexing circuit section c is connected to an upper multiplexing section. The address of the data interface to be multiplexed by the parallel bus is set in advance in the parallel bus demultiplexing control circuit 1 of the demultiplexing unit a, and the address of the data interface to be multiplexed by the serial bus is set in the serial bus demultiplexing control circuit 4 of the demultiplexing unit b. The address is set in advance.

A clock signal from the upper multiplexing unit is provided to the timing circuit 10, and the timing circuit 10 generates a timing signal based on the clock signal. Demultiplexing control circuits 1 and 4
Outputs an address signal set according to the timing signal to the data interface. Each of the plurality of data interface units has an address, and when receiving an address signal corresponding to its own address from the demultiplexing control circuits 1 and 4, outputs the data to a corresponding serial or parallel bus.

The parallel multiplexing circuit 2 and the serial multiplexing circuit 5 take in data from the data interface unit in accordance with timing signals from the demultiplexing control circuits 1 and 4, respectively.
The data is passed to the serial / parallel multiplexing circuit 8 of the demultiplexing circuit c.

Information such as the serial bus / parallel bus multiplexing order is set in the serial / parallel multiplexing / separation control circuit 7 in advance. The serial / parallel multiplexing / separating circuit c sends the timing generation circuit 10 to the serial / parallel multiplexing circuit 8 and the serial / parallel separating circuit 9. The multiplexing and demultiplexing timing of the serial bus and the parallel bus is given according to the timing signal.

The serial / parallel multiplexing circuit 8 converts the serial bus into 8-bit parallel data, multiplexes the data of the serial bus and the parallel bus in accordance with the timing information from the serial / parallel demultiplexing control circuit 7, and multiplexes the 8-bit data into a high-order multiplexing unit. Pass to

The data flow in the multiplexing direction has been described above. On the demultiplexing side, the data is separated into a serial bus and a parallel bus by control opposite to the multiplexing, and the data is transferred to the data interface unit.

In this manner, efficient multiplexing can be performed by setting an address on the serial bus side for low-speed data and an address on the parallel bus side for high-speed data, thereby realizing highly efficient multiplexing.

〔The invention's effect〕

As described above, according to the present invention, by adding a serial multiplex bus to the conventional parallel multiplex bus in the multiplexing / demultiplexing unit in the multiplexing device, multiplexing with high multiplexing efficiency can be performed even in a wide range of speed data multiplexing. There is an effect that the device can be configured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. a ... 8-bit parallel bus demultiplexing circuit section, b ... 1-bit serial bus demultiplexing circuit section, c ... serial parallel demultiplexing circuit section, 1 ... parallel bus demultiplexing control circuit, 2 ... parallel bus multiplexing Circuit, 3 ... Parallel bus demultiplexing circuit, 4 ... Serial bus demultiplexing control circuit, 5 ... Serial bus demultiplexing circuit, 6 ... Serial bus demultiplexing circuit, 7 ... Serial / parallel demultiplexing control circuit, 8 ... Serial Parallel multiplexing circuit, 9 ... Serial / parallel separation circuit, 10 ... Timing generation circuit.

Claims (1)

(57) [Claims] 1. An 8-bit parallel demultiplexing circuit connected to a parallel bus, and a 1-bit serial demultiplexing circuit connected to a serial bus for use in a time division multiplexing device for multiplexing / demultiplexing various data having different speeds. The circuit part,
A time-division multiplexing system comprising a bit-parallel demultiplexing circuit and a demultiplexing circuit connected to the 1-bit serial demultiplexing circuit, and performing time-division multiplexing / demultiplexing.