JP2810261B2 - Method of forming bump electrodes - Google Patents
Method of forming bump electrodesInfo
- Publication number
- JP2810261B2 JP2810261B2 JP3290167A JP29016791A JP2810261B2 JP 2810261 B2 JP2810261 B2 JP 2810261B2 JP 3290167 A JP3290167 A JP 3290167A JP 29016791 A JP29016791 A JP 29016791A JP 2810261 B2 JP2810261 B2 JP 2810261B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- electrode material
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 46
- 239000007772 electrode material Substances 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000010953 base metal Substances 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 7
- 238000005192 partition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 claims 1
- 238000007493 shaping process Methods 0.000 description 7
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 239000002923 metal particle Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は赤外線センサ等の光検出
素子を1次元、或いは2次元的に配列した半導体基板、
またはCCD等の信号処理素子を1次元、或いは2次元
的に配列した半導体基板等に形成する突起電極の形成方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate in which light detecting elements such as infrared sensors are arranged one-dimensionally or two-dimensionally.
Alternatively, the present invention relates to a method for forming a protruding electrode for forming a signal processing element such as a CCD on a semiconductor substrate or the like in which one-dimensional or two-dimensional array is provided.
【0002】[0002]
【従来の技術】従来からこの種の突起電極を形成する場
合には、形成すべき半導体基板の所定位置に電気メッキ
を施す選択メッキ法により行われているが、メッキ時の
電流密度の不均一、或いは電気メッキ特有の析出金属粒
の成長ばらつき等の原因により、形成される各突起電極
の高さや形状を均一に揃えることは困難であった。突起
電極の高さが不均一であると、図6に示すように、突起
電極40を形成したCCD基板10と、センサ基板20
とを突き合わせて接続する際に、矢印aで示す箇所のよ
うに、低く形成された突起電極40が対応するセンサ基
板20の出力電極21と接続されない場合があった。2. Description of the Related Art Conventionally, this type of bump electrode has been formed by a selective plating method in which electroplating is performed at a predetermined position on a semiconductor substrate to be formed. Alternatively, it is difficult to make the heights and shapes of the formed protruding electrodes uniform evenly due to factors such as variation in the growth of deposited metal particles peculiar to electroplating. If the heights of the protruding electrodes are not uniform, as shown in FIG. 6, the CCD substrate 10 on which the protruding electrodes 40 are formed and the sensor substrate 20
When they are connected by abutting each other, there are cases where the protruding electrodes 40 formed low are not connected to the corresponding output electrodes 21 of the sensor substrate 20, as indicated by the portion indicated by the arrow a.
【0003】そこで、突起電極の高さや形状を揃える方
法が提案されている(特開昭64−7638)。この方
法は、形成した突起電極50を加熱溶融し、その表面張
力によって球状化もしくは半球状化させることにより、
突起電極50の高さや形状を均一にするものである(図
7)。Therefore, a method has been proposed in which the heights and shapes of the projecting electrodes are made uniform (Japanese Patent Laid-Open No. 64-7638). In this method, the formed protruding electrode 50 is heated and melted, and is spheroidized or hemispherical by its surface tension.
The height and shape of the protruding electrode 50 are made uniform (FIG. 7).
【0004】[0004]
【発明が解決しようとする課題】しかし、このように、
形成した突起電極を一旦溶融させる方法では、溶融状態
となった突起電極は安定性に欠け、横方向に広がり易く
なっており、振動等の外的要因によって流れ出したり、
揺動して隣接する突起電極どうしが接触し短絡する場合
があった。However, as described above,
In the method of once melting the formed protruding electrode, the protruding electrode in the molten state lacks stability and is easily spread in the lateral direction, and flows out due to external factors such as vibration,
In some cases, adjacent protruding electrodes contact each other due to rocking, causing a short circuit.
【0005】また、突起電極を形成する電極間のピッチ
をある程度広げれば、溶融状態の際に、揺動して隣接す
る突起電極どうしが接触するという問題は軽減される
が、基板の高密度化を進める上で、狭ピッチにおいても
確実に形成できる突起電極の形成方法が望まれていた。If the pitch between the electrodes forming the protruding electrodes is increased to some extent, the problem that the adjacent protruding electrodes come into contact with each other by swinging in the molten state is reduced, but the density of the substrate is increased. In order to advance the method, there has been a demand for a method of forming a protruding electrode that can be reliably formed even at a narrow pitch.
【0006】本発明は、このような問題点を解決すべく
成されたものであり、高さや形状が一定に揃った突起電
極を狭ピッチにおいても確実に形成できる突起電極の形
成方法を提供することを目的とする。The present invention has been made in order to solve such a problem, and provides a method of forming a projecting electrode capable of reliably forming projecting electrodes having a uniform height and shape even at a narrow pitch. The purpose is to:
【0007】[0007]
【課題を解決するための手段】本発明は上記目的に鑑み
てなされたものであり、その要旨は、光検出基板或いは
信号処理基板等の半導体基板に、メッキ電極用の下地金
属膜を形成する工程と、形成した下地金属膜の表面にレ
ジスト膜を選択的に形成し、複数の突起電極の形成予定
領域を露出させる工程と、レジスト膜を形成した下地金
属膜の表面に電気メッキを施し、各突起電極の形成予定
領域に突起電極の電極材料を析出させる工程と、各突起
電極の形成予定領域内に析出した電極材料を、該形成予
定領域内において、当該電極材料の周囲を囲うレジスト
膜を仕切り壁として加熱溶融する工程とを備える突起電
極の形成方法にある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned object, and its gist is to form a base metal film for a plating electrode on a semiconductor substrate such as a photodetection substrate or a signal processing substrate. A step of selectively forming a resist film on the surface of the formed base metal film, exposing regions where a plurality of projected electrodes are to be formed, and performing electroplating on the surface of the base metal film on which the resist film is formed, Depositing the electrode material of the projection electrode in the region where each projection electrode is to be formed, and depositing the electrode material deposited in the region where each projection electrode is to be formed with the resist film surrounding the electrode material in the formation region. And a step of heating and melting the partition electrode as a partition wall.
【0008】[0008]
【作用】各突起電極の形成予定領域内に電極材料を析出
させた後、この形成予定領域内において、析出した電極
材料を加熱溶融させるが、この形成予定領域は、レジス
ト膜によって周囲を囲まれた状態で形成されている。従
って、突起電極の形成予定領域を形成するレジスト膜
は、溶融状態の電極材料を収容するための仕切り壁とし
て機能すると共に、析出した電極材料を整形するための
整形型としても機能するものである。After depositing the electrode material in the area where each protruding electrode is to be formed, the deposited electrode material is heated and melted in the area where the projection electrode is to be formed. The area where the electrode material is to be formed is surrounded by a resist film. It is formed in a state where it is set. Therefore, the resist film forming the region where the projecting electrode is to be formed functions as a partition wall for accommodating the electrode material in a molten state, and also functions as a shaping type for shaping the deposited electrode material. .
【0009】[0009]
【実施例】以下、本発明に係る突起電極の形成方法を添
付図面に基づいて工程順に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a bump electrode according to the present invention will be described below in the order of steps with reference to the accompanying drawings.
【0010】図1に示すように、信号処理基板としての
CCD基板10の表面には複数の入力電極12を有して
おり、この上部には突起電極を形成するためのAl膜に
よるコンタクトホール電極13が形成されている。ま
た、図では省略したが、このCCD基板10の表面上に
は、多数の信号線電極が形成されているため、基板の表
面保護のために絶縁膜などのパッシベーション膜14を
形成している。As shown in FIG. 1, a plurality of input electrodes 12 are provided on the surface of a CCD substrate 10 as a signal processing substrate, and a contact hole electrode made of an Al film for forming a protruding electrode is provided above the input electrodes 12. 13 are formed. Although omitted in the figure, since a large number of signal line electrodes are formed on the surface of the CCD substrate 10, a passivation film 14 such as an insulating film is formed to protect the surface of the substrate.
【0011】このように形成されているCCD基板10
の全面に、Ti膜15、Au膜16を順次蒸着し、下地
金属膜を形成する(図2)。なお、このTi膜15はバ
リアメタルであり、Au膜16はメッキ用電極である。The CCD substrate 10 formed as described above
Then, a Ti film 15 and an Au film 16 are sequentially deposited on the entire surface to form a base metal film (FIG. 2). The Ti film 15 is a barrier metal, and the Au film 16 is a plating electrode.
【0012】次ぎに、Au膜16表面にレジスト膜17
をパターン形成し(図3参照)、Au膜16の表面に突
起電極の形成予定領域を露出させる。Next, a resist film 17 is formed on the Au film 16 surface.
(See FIG. 3) to expose a region where the bump electrode is to be formed on the surface of the Au film 16.
【0013】次ぎに、形成したレジスト膜17を電気メ
ッキの保護膜として使用し、選択メッキ法により、低融
点金属、例えばInによる電極材料11´を突起電極の
形成予定領域に析出させる(図3(a))。具体的に
は、CCD基板10をInメッキ溶液中に浸し、Au膜
16を電極とし、室温にて所定の電流値で数十分間メッ
キを施す。これによって、析出する金属材料は数10μ
m程度の高さとなる。なお、この際、メッキ電流を一定
に制御したとしても、電極材料11´の高さや形状は、
電気メッキ特有の析出金属粒の成長ばらつき等の原因に
より不揃いである。Next, using the formed resist film 17 as a protective film for electroplating, an electrode material 11 ′ made of a low-melting metal, for example, In, is deposited in a region where a bump electrode is to be formed by a selective plating method (FIG. 3). (A)). Specifically, the CCD substrate 10 is immersed in an In plating solution, and the Au film 16 is used as an electrode to perform plating at room temperature with a predetermined current value for several tens minutes. Thereby, the deposited metal material is several tens μm.
m. At this time, even if the plating current is controlled to be constant, the height and shape of the electrode material 11 ′ are
They are not uniform due to factors such as variations in the growth of deposited metal particles specific to electroplating.
【0014】次ぎに、析出した電極材料11´をInの
融点まで加熱し、各突起電極の形成予定領域内において
この電極材料11´を溶融させる(図3(b))。各突
起電極の形成予定領域は、レジスト膜17により周囲を
囲まれた状態で形成されているため、各形成予定領域を
形成するレジスト膜17は、この領域内に溶融状態の電
極材料11´を収容するための仕切り壁として機能する
と共に、析出した電極材料11´を整形するための整形
型としても機能する。Next, the deposited electrode material 11 'is heated to the melting point of In, and the electrode material 11' is melted in the region where each protruding electrode is to be formed (FIG. 3B). Since the region where each projection electrode is to be formed is formed so as to be surrounded by the resist film 17, the resist film 17 which forms each formation region has the electrode material 11 ′ in a molten state in this region. In addition to functioning as a partition wall for housing, it also functions as a shaping mold for shaping the deposited electrode material 11 ′.
【0015】次ぎに、溶融した電極材料11´を融点未
満の温度に下げて固化させる。次いで、整形型として機
能したレジスト膜17を除去した後、整形した電極材料
11´をマスクとして、露出したAu膜16、その直下の
Ti膜15を順にエッチングして除去し、突起電極11
の形成工程は終了する(図4)。これにより、高さや形
状が均一に揃った突起電極11が得られる。Next, the molten electrode material 11 'is lowered to a temperature lower than the melting point and solidified. Next, after removing the resist film 17 functioning as a shaping mold, the shaped electrode material is removed.
Using the 11 ′ as a mask, the exposed Au film 16 and the Ti film 15 immediately below the exposed Au film 16 are sequentially etched and removed.
Is completed (FIG. 4). Thereby, the protruding electrode 11 having a uniform height and shape can be obtained.
【0016】以上のようにしてCCD基板10上に突起
電極11を形成した後、図5に示すように、CCD基板
10と光検出基板としてのセンサ基板20との接続を行
い、半導体装置1を製造する。両基板の接続にあたって
は、まず、センサ基板20下面の各出力電極21と、C
CD基板10上の各突起電極11との位置合わせを行
い、次いで、両基板10、20を互いに突き合わせて接
続する。この際、各突起電極11の高さが全て均一に揃
っているので、各突起電極11はセンサ基板20の各出
力電極21と全て接続され、CCD基板10とセンサ基
板20の各素子を確実に接続することができる。After the protruding electrodes 11 are formed on the CCD substrate 10 as described above, as shown in FIG. 5, the CCD substrate 10 is connected to the sensor substrate 20 as a light detection substrate, and the semiconductor device 1 is mounted. To manufacture. When connecting the two substrates, first, each output electrode 21 on the lower surface of the sensor substrate 20 is connected to C
The alignment with the respective protruding electrodes 11 on the CD substrate 10 is performed, and then the two substrates 10 and 20 are connected to each other by abutting each other. At this time, since the heights of the projecting electrodes 11 are all uniform, the projecting electrodes 11 are all connected to the output electrodes 21 of the sensor substrate 20, and the CCD substrate 10 and the elements of the sensor substrate 20 are securely connected. Can be connected.
【0017】本実施例では、突起電極11をCCD基板
10に形成する例を示したが、センサ基板20側に突起
電極11を形成することもでき、他の半導体基板上に形
成することも勿論可能である。In this embodiment, the example in which the protruding electrode 11 is formed on the CCD substrate 10 has been described. However, the protruding electrode 11 can be formed on the sensor substrate 20 side, and can be formed on another semiconductor substrate. It is possible.
【0018】[0018]
【発明の効果】以上説明した通り、本発明に係る突起電
極の形成方法によれば、下地金属膜の表面に、レジスト
膜によって複数の突起電極の形成予定領域を形成し、各
形成予定領域内に電極材料を析出させた後、析出した電
極材料を各形成予定領域内において加熱溶融する方法を
採用した。As described above, according to the method for forming a bump electrode according to the present invention, a plurality of regions where bump electrodes are to be formed are formed on the surface of the underlying metal film by a resist film. Then, a method was employed in which after the electrode material was deposited, the deposited electrode material was heated and melted in each region to be formed.
【0019】従って、各形成予定領域を形成するレジス
ト膜は、溶融状態の電極材料を収容するための仕切り壁
として機能すると共に、析出した電極材料を整形するた
めの整形型としても機能するため、溶融状態の電極材料
が周囲に流れ出したり、揺動して隣接する電極材料どう
しが接触する事態を防止できると共に、高さや形状が一
定に揃った突起電極を狭ピッチにおいても確実に形成す
ることが可能となる。Therefore, the resist film forming each of the regions to be formed functions not only as a partition wall for accommodating the molten electrode material but also as a shaping type for shaping the deposited electrode material. It is possible to prevent the electrode material in the molten state from flowing around or swinging to contact adjacent electrode materials, and to reliably form a projection electrode having a uniform height and shape even at a narrow pitch. It becomes possible.
【図1】CCD基板を示す部分断面図である。FIG. 1 is a partial cross-sectional view showing a CCD substrate.
【図2】CCD基板上に下地金属膜を形成した状態を示
す部分断面図である。FIG. 2 is a partial cross-sectional view showing a state where a base metal film is formed on a CCD substrate.
【図3】図3(a)は電気メッキを施して突起電極の形
成予定領域に電極材料を析出させた状態を示すCCD基
板の部分断面図、図3(b)は析出した電極材料を加熱
溶融した状態を示すCCD基板の部分断面図である。FIG. 3A is a partial cross-sectional view of a CCD substrate showing a state where an electrode material is deposited on a region where a protruding electrode is to be formed by electroplating, and FIG. 3B is a diagram showing a state in which the deposited electrode material is heated. FIG. 3 is a partial cross-sectional view of the CCD substrate in a molten state.
【図4】突起電極を形成したCCD基板を示す部分断面
図である。FIG. 4 is a partial cross-sectional view showing a CCD substrate on which protruding electrodes are formed.
【図5】CCD基板とセンサ基板とを突き合わせて接続
した半導体装置を示す部分断面図である。FIG. 5 is a partial cross-sectional view showing a semiconductor device in which a CCD substrate and a sensor substrate are connected in abutting relation.
【図6】従来の半導体装置を示す部分断面図である。FIG. 6 is a partial sectional view showing a conventional semiconductor device.
【図7】従来の突起電極の形成方法を示す半導体基板の
部分断面図である。FIG. 7 is a partial cross-sectional view of a semiconductor substrate showing a conventional method for forming a bump electrode.
1…半導体装置、10…CCD基板(信号処理基板)、
11…突起電極、11´…電極材料、16…Au膜(下
地金属膜)、17…レジスト膜、20…センサ基板(光
検出基板)。1 ... Semiconductor device, 10 ... CCD board (signal processing board),
11: projecting electrode, 11 ': electrode material, 16: Au film (base metal film), 17: resist film, 20: sensor substrate (light detection substrate).
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平1−59945(JP,A) 特開 平1−122141(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 H01L 27/146────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-59945 (JP, A) JP-A-1-122141 (JP, A) (58) Fields investigated (Int.Cl. 6 , DB name) H01L 21/60 H01L 27/146
Claims (3)
を形成する工程と、 形成した前記下地金属膜の表面にレジスト膜を選択的に
形成し、複数の突起電極の形成予定領域を露出させる工
程と、 前記レジスト膜を形成した前記下地金属膜の表面に電気
メッキを施し、前記各突起電極の形成予定領域に突起電
極の電極材料を析出させる工程と、 前記各突起電極の形成予定領域内に析出した電極材料
を、該形成予定領域内において、当該電極材料の周囲を
囲う前記レジスト膜を仕切り壁として加熱溶融する工程
と、 を備えることを特徴とする突起電極の形成方法。1. A step of forming a base metal film for a plating electrode on a semiconductor substrate, and selectively forming a resist film on a surface of the formed base metal film to expose regions where a plurality of bump electrodes are to be formed. A step of: electroplating the surface of the base metal film on which the resist film is formed, and depositing an electrode material of the bump electrode in the area where the bump electrode is to be formed; And fusing the electrode material deposited in the region to be formed with the resist film surrounding the electrode material as a partition wall in the formation scheduled region.
変換する検出部を有し、その検出部で得られた電気信号
を取り出す複数の出力電極を備えた光検出基板であるこ
とを特徴とする請求項1記載の突起電極の形成方法。2. The semiconductor substrate according to claim 1, wherein said semiconductor substrate has a detection unit for converting an optical signal into an electric signal, and said electric signal obtained by said detection unit.
2. The method according to claim 1, wherein the substrate comprises a plurality of output electrodes for extracting light.
し、該入力電極に入力された電気信号を処理するための
処理回路を備える信号処理基板であることを特徴とする
請求項1記載の突起電極の形成方法。3. The signal processing substrate according to claim 1, wherein the semiconductor substrate has a plurality of input electrodes and includes a processing circuit for processing an electric signal input to the input electrodes. Forming method of the bump electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3290167A JP2810261B2 (en) | 1991-11-06 | 1991-11-06 | Method of forming bump electrodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3290167A JP2810261B2 (en) | 1991-11-06 | 1991-11-06 | Method of forming bump electrodes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05129308A JPH05129308A (en) | 1993-05-25 |
| JP2810261B2 true JP2810261B2 (en) | 1998-10-15 |
Family
ID=17752621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3290167A Expired - Fee Related JP2810261B2 (en) | 1991-11-06 | 1991-11-06 | Method of forming bump electrodes |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2810261B2 (en) |
-
1991
- 1991-11-06 JP JP3290167A patent/JP2810261B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05129308A (en) | 1993-05-25 |
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