JP2827181B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a stacked capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art The surface area of a storage electrode of a stacked capacitor has a three-dimensional contribution, in addition to a horizontal surface, a curved effect due to a step difference of a base such as a word line and a side effect of a storage electrode. All of these contribute to the increase in the surface area of the storage electrode at the expense of increasing the step.

Here, in order to obtain the maximum effect with the minimum sacrifice, it is better to use the side effect proportional to the four sides, for example, rather than the bending effect of the upper and lower surfaces proportional to the two sides of the storage electrode.
FIG. 12 illustrates a DRAM cell using a thick storage electrode in this manner.

In FIG. 12, a storage electrode 102 of a capacitor 101 of a DRAM cell is formed of a single layer, a dielectric film 103 is formed therearound, and a counter electrode 10 is further formed therearound.
4 is formed. In this case, the thickness of the storage electrode 103 is formed to be large, and the side surface thereof has a height that greatly contributes to the capacitance.

The storage electrode 102 is connected to the transfer transistor 10
5 is connected to one of the source / drain layers 106,
The other source / drain layer 107 has a capacitor 10
A bit line 110 is formed through a bit line contact hole 109 formed in an interlayer insulating film 108 that covers the semiconductor device 1.

Looking at this, it can be seen that the bit line contact hole
It is expected that the 109 aspects will be so severe that manufacturability will be compromised. Therefore, it is considered to work a thick storage electrode to reduce the step.

There is a fin type in which a horizontal groove is formed in the storage electrode, and the present applicant changes the number of times of growth of polysilicon and SiO ₂ without using any special technique. Accordingly, a technique for forming any number of fins without increasing the number of mask steps is disclosed in Japanese Patent Application No. 62-306416.
No. has been proposed.

An example of the manufacturing process will be described with reference to FIGS. First, as shown in FIG. 13A, a gate electrode 11 is formed in an active region of a semiconductor layer 111 via an insulating film 112.
After forming 3, a source / drain (S / D) layer 114, 115 is provided by introducing an impurity into the semiconductor layer 111 on both sides thereof, and these constitute a transfer transistor of the DRAM. In this case, an extension of the gate electrode 113 becomes a word line.

Further, after an interlayer insulating film 117 is entirely stacked, a contact hole 118 is formed on one of the S / D layers 114.
Is formed, and the bit line 119 is connected here. Next, FIG.
As shown in FIG. 3 (B), a nitride film 120 and an SiO ₂ film 121 are stacked, and then a polycrystalline silicon film 122 and an SiO ₂ film 123 are alternately stacked at least one layer. An opening 124 is formed on the / D layer 115 by photolithography.

After that, a polycrystalline silicon film 125 is laminated on the whole, and then the polycrystalline silicon films 122 and 125 in the region defining the storage electrode and the SiO ₂ film 123 sandwiched therebetween are selectively etched to form the trench 116. Then, the SiO ₂ films 121 and 123 on the nitride film 120 are selectively removed with hydrofluoric acid (FIG. 14D).

As a result, the polycrystalline silicon films 122 and 125 have a fin-shaped cross section, which is used as the storage electrode 126. Thereafter, a thin dielectric film 127 made of an insulating material such as Si ₃ N ₄ or SiO ₂ is formed around the storage electrode 126 (FIG. 14E), and a polycrystalline silicon film is entirely grown by CVD. This is patterned to form a counter electrode 128 (FIG. 14).
(F)).

[0012]

By the way, in order to improve the degree of integration of cells in a conductor device, the cell area is reduced and the storage electrode 126 of the capacitor of each cell is reduced.
It is necessary to reduce the horizontal area of the fins, and in order to secure a sufficient storage capacity, the number of fins may be increased to increase the total surface area.

However, the increase in the number of the storage electrodes 12
6 becomes high, and the aspect ratio of the groove 116 for partitioning the storage electrode 126 sharply increases, which makes processing difficult. Furthermore, the height difference between the memory cell area and the other areas increases, and from the viewpoint of the depth of focus of the photoresist exposure,
It becomes difficult to form a pattern of the counter electrode 128 extending over a plurality of cells and a wiring electrode (not shown) thereabove.

Therefore, it is extremely important to increase the surface area of the storage electrode 126 while suppressing the height of the storage electrode 126. For this purpose, it is most effective to reduce the thickness of the fin as much as possible. .

[0015] However, at present, it is not clear even technical issues such as what is a problem in promoting the thinning of fins. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device capable of reducing the thickness of a storage electrode of a stacked capacitor and a method of manufacturing the same.

[0016]

The above-mentioned object is achieved by the following means. First, as illustrated in FIG. 3 (H), it is composed of polycrystalline semiconductor films 15 and 18 having a larger grain size than the polycrystalline semiconductor film from the beginning of film formation, and has a fin-shaped side section. First electrode 20 being formed
And a dielectric film 23 formed on the surface of the first electrode 20
And a second capacitor covering the dielectric film 23 with a stacked capacitor. Second, the first semiconductor device is characterized in that the polycrystalline semiconductor film having a large grain size is a semiconductor film obtained by crystallizing an amorphous semiconductor film.

Third, in order to form the device illustrated in FIG. 11A, a step of forming an impurity introduction layer 7 of the opposite conductivity type in the semiconductor substrate 1 of one conductivity type, Forming a first insulating film 8, 13 thereon, patterning the first insulating film 8, 13 to form a contact hole 17 exposing a part of the impurity introduction layer 7, The contact holes 17 are formed on the first insulating films 8 and 13 from above.
Laminating an amorphous semiconductor film following the surface of the impurity-introduced layer 7 through the step of: introducing an impurity into the amorphous semiconductor film during or after the growth of the amorphous semiconductor film; Patterning the amorphous semiconductor film, the amorphous semiconductor film remaining in the region including the contact hole 17 as a first electrode 30 for a capacitor, the capacitor on the surface of the first electrode 30 A method of manufacturing a semiconductor device, comprising the steps of: forming a dielectric film 32 for use in a semiconductor device; and forming a second electrode 34 for the capacitor that covers the dielectric film 32.

Fourth, a step of forming an impurity introduction layer 7 of the opposite conductivity type in the semiconductor substrate 1 of one conductivity type to form a capacitor having a storage electrode having one fin; A step of sequentially laminating a first insulating film 8, 13 and a second insulating film 14 on the substrate 1 and patterning the first and second insulating films 8, 13, 14 to form the impurity-introduced layer 7. Forming a contact hole 17 exposing a part thereof, laminating an amorphous semiconductor film 18 following the impurity introduction layer 7 from the upper surface of the second insulating film 14 through the contact hole 17, During or after the growth of the amorphous semiconductor film 18, a step of introducing impurities into the amorphous semiconductor film 18, and patterning the amorphous semiconductor film 18,
A step of using the amorphous semiconductor film 18 left in the region including the contact hole 17 as a first electrode 20 for a capacitor, and supplying an etching solution through a side of the first electrode 20 to form the first electrode 20. A step of selectively removing the second insulating film 14 by isotropic etching; and a step of forming a dielectric film for the capacitor on the entire surface of the first electrode 20 above the first insulating films 8 and 13. 23. A method for manufacturing a semiconductor device, comprising: forming a second electrode 24 for the capacitor covering the dielectric film 23;

Fifth, as shown in FIGS. 1 to 3, an impurity introduction layer 7 of the opposite conductivity type is formed on the surface of the semiconductor substrate 1 of one conductivity type.
Forming the first insulating films 8 and 13 on the semiconductor substrate 1, and directly or via the second insulating film 14 on the first insulating films 8 and 13. A step of alternately laminating at least one layer of the first amorphous semiconductor film 15 and the third insulating film 16 in order, and To form a contact hole 17 exposing a part of the impurity-doped layer 7, and from the uppermost third insulating film 16 to the upper surface of the impurity-doped layer 7 through the contact hole 17. A step of laminating a second amorphous semiconductor film 18 and patterning a layer from the uppermost third insulating film 16 to the first amorphous semiconductor film 18 to a region including the contact hole 17 Remaining, the first and second amorphous semiconductor film 1
A step of forming a first electrode 20 for a capacitor having a fin-shaped cross section composed of 5 and 18, and supplying an etching solution through the side of the first electrode 20 to form a first insulating film 8, 13. A step of selectively removing the upper insulating films 14 and 16 by isotropic etching, and a step of forming the capacitor for the entire surface of the first electrode 20 above the first insulating films 8 and 13; And a step of forming a second electrode 24 for the capacitor that covers the dielectric film 23.

Sixth, the amorphous semiconductor films 15 and 18 are amorphous silicon films, and are grown at a growth temperature of 400 to 550 ° C. by a low pressure CVD method using Si ₂ H ₆ as a source gas. Or a _{third to} fifth method for manufacturing a semiconductor device, characterized by being grown at a growth temperature of 350 to 500 ° C. by a low pressure CVD method using Si ₃ H ₈ as a source gas.

[0021] Seventh, the amorphous semiconductor film 15, 18, by the manufacturing method of the fifth semiconductor device you characterized by introducing impurities after growth. Eighth, the amorphous semiconductor film 1
The third film is characterized in that the insulating film 16 laminated on the first and second semiconductor layers 5 and 18 is grown at the same temperature as the growth temperature of the first and second amorphous semiconductor films 15 and 18 or at a temperature difference of 100 ° C. or less. -Fifth
The semiconductor device manufacturing method.

Ninth, the dielectric film 23 is grown at a temperature lower than the temperature at which the amorphous semiconductor films 15 and 18 are subjected to a lowering stress than the stress applied to the storage electrodes 20 and 30 from the outside. According to the third to fifth methods of manufacturing a semiconductor device.

Tenth, a step of forming an impurity introducing layer of the opposite conductivity type on the surface of the semiconductor substrate of one conductivity type, a step of forming a first insulating film on the semiconductor substrate, and a step of forming the first insulating film. Growing a first semiconductor film and a third insulating film alternately at the same temperature at least one layer at a time directly on the film or via the second insulating film; and Patterning from the insulating film to the first insulating film to form a contact hole exposing a part of the impurity introducing layer; and introducing the impurity through the contact hole from above the uppermost third insulating film. Laminating a second semiconductor film following the upper surface of the layer, patterning from the uppermost third insulating film to the first semiconductor film and leaving it in the region including the contact hole, the first and second Consisting of two semiconductor films Forming a first electrode for a capacitor having a fin-shaped cross section, and supplying an etching solution through a side portion of the first electrode to isotropically etch the insulating film above the first insulating film; And selectively removing the capacitor and the capacitor at a temperature at which the semiconductor film does not generate a breakdown stress less than an externally applied stress on the entire surface of the first electrode above the first insulating film. And a step of forming a second electrode for the capacitor covering the dielectric film.

Eleventh, the amorphous semiconductor films 15 and 18 are
The feature is that impurities are simultaneously introduced during growth.
Fifth and tenth semiconductor device manufacturing methods. Twelfth,
As illustrated in FIG. 5, the contact holes 17 are located below the center of the upper surface of the first electrode 20, according to the third to fifth and tenth semiconductor device manufacturing methods.

[0025]

According to the first aspect, the storage electrode 20 is constituted by the polycrystalline semiconductor films 15 and 18 having a larger grain size than the polycrystalline semiconductor film from the beginning of film formation.

In this case, the grain size of that size is obtained by polycrystallizing the amorphous semiconductor layer. According to this, as shown in FIG. Also, the capacity does not decrease.

According to the second aspect, the first aspect is applied to a fin-type storage electrode. In this case, the semiconductor film having a large grain size has a large yield stress, and the fin is unlikely to be curved as shown in FIG. The curvature of the fin is a phenomenon described in FIG. 7B and is newly found by the present inventor. This generating mechanism will become apparent from the following description of the embodiments.

According to the third to fifth aspects, an amorphous semiconductor film is grown and used as the fin-shaped first electrode (storage electrode) 20 of the capacitor. The amorphous film has a good surface condition, and when it is polycrystallized by subsequent annealing, the yield stress increases. Therefore, the amorphous film is suitable for the storage electrode 20 to be thinned.

According to a third aspect of the present invention, a storage electrode having a structure in which a dielectric film is not provided on a lower surface is formed. A fourth invention relates to formation of a storage electrode having one fin, and a fifth invention relates to formation of a storage electrode having a plurality of fins.

According to the sixth invention, the amorphous silicon film 1
In growing 5,18, the growth temperature is set to 400 ° C. to 550 ° C. using Si ₂ H ₆ as a source gas, or the growth temperature is set to 3 using Si ₃ H ₈ as a source gas.
The temperature is 50 ° C to 500 ° C. According to this, the film growth rate is high, and the throughput is improved.

According to the seventh aspect, the amorphous semiconductor films 15, 1
Since impurities are introduced after the growth of 8, the semiconductor film
15,18 low resistance can be achieved. According to the eighth and tenth aspects, when forming the semiconductor films forming the storage electrodes 20 and 31, the growth temperatures of the insulating films stacked above and below the storage films are the same as or close to the semiconductor film growth temperatures. For this reason,
The stress induced in the semiconductor film due to the growth of the insulating film is reduced, and the fin of the storage electrode is less likely to bend.

According to the ninth and tenth aspects of the invention, the growth temperature of the dielectric film attached to the periphery of the storage electrode is adjusted to reduce the decrease in the yield stress of the fin of the storage electrode. For this reason, the curvature of the fin of the storage electrode is suppressed.

According to the tenth and eleventh aspects, the impurity for lowering the resistance is introduced simultaneously with the growth of the film. For this reason, the internal stress is reduced as compared with the case where it is introduced later, which is effective for suppressing the bending.

According to the twelfth aspect, since the contact hole 17 connected to the impurity-doped layer 7 is provided at the center of the storage electrode 20, the bending is less likely to occur as compared with the case where the position is shifted.

[0035]

First, a process for forming a DRAM cell having a fin-shaped stacked capacitor will be briefly described with reference to the drawings, and then conditions for forming a storage electrode of a capacitor will be described in detail. (A) Description of the manufacturing process of the device of one embodiment of the present invention FIGS. 1 to 3 are sectional views showing the manufacturing process of the device of one embodiment of the present invention.

In FIG. 1A, reference numeral 1 denotes a p-type semiconductor layer made of silicon. On the upper surface of the semiconductor layer 1, an SiO ₂ field oxide film 2 surrounding an active region X is formed to a thickness of 400 nm by a selective oxidation method. It is formed to a thickness.

In this state, first, a gate oxide film 3 of about 10 nm made of SiO ₂ is formed on the upper surface of the semiconductor layer in the active region by a thermal oxidation method, and thereafter a polycrystalline silicon film 4 having a thickness of 100 nm is formed by CVD. Then, phosphorus is introduced into the atmosphere at 1 × 10 ²⁰ / cc, and the resistance of the polycrystalline silicon film 4 is reduced by a thermal diffusion method.

Then, the polycrystalline silicon film 4 is patterned by using a photolithography technique, thereby forming a word line (WL) 5 also serving as a gate electrode. Then, using the word line 5 as a mask, phosphorus is ion-implanted into the semiconductor layer 1 on both sides thereof at about 3 × 10 ¹³ / cm ² , whereby an n ⁺ -type source / drain (S / D) is introduced into the semiconductor layer 1. Layers 6 and 7 are formed. Thereby, the transfer transistor is completed.

Next, as shown in FIG. 1B, after an interlayer insulating film 8 made of SiO ₂ is laminated to a thickness of about 100 nm by the CVD method, the S / D layers 6 and 7 on both sides of the word line 5 are formed. The upper interlayer insulating film is opened by photolithography to form a bit line contact hole 9. Then
After a polycrystalline silicon film 10 and a tungsten silicide (WSi) film 11 are sequentially grown to a thickness of 50 nm and a thickness of 100 nm by the CVD method, phosphorus is ion-implanted at an acceleration energy of 70 keV and a dose of 4 × 10 ¹⁵ / cm ^2. The resistance of the polycrystalline silicon film 10 is reduced.

Then, the WSi film 11 and the polycrystalline silicon film 1
0 is patterned by photolithography, and a bit line (BL) 12 passing through a bit line contact hole 9 is formed.
To form FIGS. 4 and 5 show an example of a plan view in which the interlayer insulating film in this state is omitted.

Thereafter, as shown in FIG. 1C, a silicon nitride film (Si ₃ N ₄ film) 13 is laminated to a thickness of about 50 nm, and subsequently, an SiO ₂ film 14 and an amorphous silicon film 15 are formed. It is formed to a thickness of 30 nm and 20 nm, respectively. These films are CVD
The silicon film 15 is grown by SiH ₄ , Si
A gas, such as ₂ H _6. Then, add phosphorus to the accelerating energy 5
After lowering the resistance of the silicon film 15 by ion implantation at keV and a dose of 4 × 10 ¹⁵ / cm ² , an SiO ₂ film 16 is grown to 30 nm.

Next, from the uppermost SiO ₂ film 16 to the interlayer insulating film 8
Patterning by photolithography
A contact hole 17 as shown in FIG. 2D is formed on the S / D layer 7 to which the bit line 12 is not connected.

Thereafter, an amorphous silicon film 18 is laminated to a thickness of 20 nm along the inner and bottom surfaces of the contact hole 17 and the uppermost SiO ₂ film 16 under the same conditions as the silicon film 15. Then, phosphorus is ion-implanted under the same conditions as described above to lower the resistance of the silicon film 18. Then, the silicon film 18, the SiO ₂ film 16, and the silicon film 15 existing on the boundary of the storage electrode formation region Y shown in FIG. A separation groove 19 as shown in FIG.

Next, when the SiO ₂ films 14 and 16 are isotropically removed with hydrofluoric acid through the portions exposed by etching, the silicon films 15 and 18 become fin-shaped in cross section as shown in FIG. This is the storage electrode 20 of the capacitor.

Although the silicon films 15 and 18 are made amorphous here, they may be annealed immediately after film formation to make them polycrystalline. In this embodiment, the silicon films 15 and 18 are
Although two fin-shaped storage electrodes 20 are formed by forming layers, one or three or more fins may be formed by laminating one or three or more silicon films depending on the capacitance of the capacitor. In the case of one, a contact hole is formed before the silicon film 15 is grown.

Thereafter, as shown in FIG. 3G, the surface of the storage electrode 20 exposed on the silicon nitride film 8
The second nitride film 21 having good coverage is formed to a thickness of 7 by the D method.
Grow uniformly to nm. Then, heat treatment is performed for 30 minutes in a wet oxygen atmosphere at about 800 ° C. to form the silicon nitride film 2.
An SiO ₂ film 22 having a thickness of about 1 nm is grown on the surface of the substrate 1 and a dielectric film 23 of the capacitor is formed by the grown SiO ₂ film 22. In this case, the leakage current is reduced by the SiO ₂ film 22 on the surface of the silicon nitride film 21.

Next, in order to obtain the state shown in FIG.
Grown to a thickness of about 100 nm, and phosphorus is added at 1 × 10 ²⁰ / cc by thermal diffusion.
Then, the resistance of the polycrystalline silicon film 24 is reduced. At this stage, since the gap between the fins of the storage electrode 23 is completely filled, it is not necessary to consider the occurrence of fin curvature in the following steps. Then, the polycrystalline silicon film 2
4 is patterned to leave a counter electrode at least in the capacitor forming region, thereby completing the capacitor Q.

Further, a flattening film 25 having a two-layer structure of SiO ₂ and BPSG is formed on the whole, and a contact hole (not shown) and an aluminum electrode wiring layer 26 are formed.
The RAM cell is completed.

In the above embodiment, the amorphous silicon film 15 and the film constituting the storage electrode 20 are used.
Although 18 is formed, the film changes to polycrystalline by heat when growing SiO ₂ or the like thereon, or by annealing after forming a silicon film or implanting impurities.

Then, the crystallized silicon films 15, 18
The grain size appearing on the upper surface of the substrate is about 1 μm, which is about 500 nm larger than the case of forming a polycrystal from the beginning of growth.

Here, various experiments and examinations were conducted on the thinning of the fins, and the following results were obtained. (B) Description of Growth of Silicon Film Constituting Storage Electrode Relationship between Film Growth Conditions and Capacitance of Capacitor When the growth method of the silicon film for forming the storage electrode is changed and the minimum film thickness acting as a capacitor is examined, The result as shown in FIG. 6 (B) was obtained. In this case, as shown in FIG. 6A, one fin of the storage electrode 27 is formed, and the above-described dielectric film 23 and the counter electrode 24 are grown thereon.
4 and the capacitance at points x and y between the S / D layer below the storage electrode 27 were examined.

First, an amorphous silicon film is grown at a low temperature, for example, at 450 ° C. using disilane (Si ₂ H ₆ ) gas, and the storage electrode 27 is formed by this . As shown in FIG.
As shown in the figure, even when the film thickness was 3 nm, a capacitance almost the same as that of the case of 10 nm was obtained.

On the other hand, a polycrystalline silicon film is grown at a temperature of 650 ° C. using monosilane (SiH ₄ ) gas,
From this, when the storage electrode 27 is formed, a sharp decrease in capacitance is observed at a thickness of 5 nm or less, and the film thickness of 5 nm becomes the limit value of the storage electrode 27.

As a result, it was found that the lowering of the growth temperature of the silicon film to make it amorphous makes it possible to reduce the minimum film thickness acting as a storage electrode and to make the fin thinner. Relationship between film growth conditions and fin curvature When two storage electrode fins were used as shown in Fig. 2 (F) and an experiment was conducted on the degree of curvature, the experimental results shown in Fig. 7 were obtained. Was. In this case, contact hole 1
The length of the fin from No. 7 was 1.7 μm.

First, an amorphous silicon film is formed at 450 ° C. using Si ₂ H ₆ gas,
When it is set to 0, the fin does not bend even when its film thickness becomes several nm.

On the other hand, a polycrystalline silicon film is grown using SiH ₄ gas at a temperature of 620 ° C. to form a storage electrode 20.
It can be seen that when a film thickness of 120 nm or less is formed, 100% of the curvature as shown in FIG. 7 occurs and the film cannot be used as a storage electrode. Forming thick fins is also effective in suppressing curvature, but contradicts the demand for thinner fins.

As a result, it has been found that the curvature of the fin of the storage electrode greatly depends on the method of growing the silicon film, and it is much less likely that the fin becomes amorphous when grown at a low temperature. The storage electrode 2 is formed by using the amorphous silicon films 15 and 18.
Even when 0 is formed, the film is polycrystallized by the heat of about 650 ° C. in the process of forming the storage electrode 20,
The grain size is about several hundred nm larger than the case where a polycrystalline film is formed from the beginning.

When a fin-type storage electrode is formed, as shown in FIGS. 1C to 2E, the SiO ₂ film 1 is formed.
4, 16 and silicon films 15, 18 are grown alternately.
When these films are formed, stress acts on each other, and when the SiO ₂ films 14 and 16 are removed, the silicon films 15 and 1 are removed.
The support of the stress of No. 8 disappears, and bending easily occurs. When this stress is equal to or higher than the yield stress of the silicon film, the silicon film is plastically deformed. This is considered to be the basic mechanism for generating the curvature of the fin.

The reason why the curvature generation rate depends on the thickness of the fin of the storage electrode 20 is that the yield stress of the silicon film is proportional to the film thickness. Further, the difference in the rate of occurrence of curvature occurs depending on the method of growing the silicon film because the yield stress of the silicon film itself is different and the difference in mutual stress between the silicon film and the SiO ₂ film is different.

Although it is effective to grow in an amorphous state, even when a polycrystalline silicon film is used, the growth temperature of the capacitor dielectric film after the fins of the silicon nitride film or SiO ₂ film are formed. If the heat treatment is performed at a temperature lower than the temperature at which the yield stress of the silicon film is reduced by lowering the temperature, the curvature can be suppressed, and these will be described later.

Relationship with impurity introduction It is necessary to introduce an impurity into the silicon film to reduce the resistance. In the above-described manufacturing process, an ion implantation method is used. It is crystallized and crystallized by a subsequent heat treatment. This also changes the internal stress of the silicon film and requires attention. In general, it is considered that internal stress increases to promote bending, and it is desirable to grow a silicon film while introducing impurities.

Next, examples of conditions for growing a silicon film will be described. When forming an amorphous silicon film, SiH ₄ gas may be used, but the growth rate is low, and Si ₂ H ₆ is more preferable.

The furnace temperature was set to 450 ° C., the internal pressure was set to 0.5 Torr, and Si ₂ H ₆
When gas is introduced into the furnace at 40 cc / min, 1.5 nm / m
The amorphous silicon films 15 and 18 grow at the growth rate of in. At this time, if the growth pressure is reduced in the range of 1.0 to 0.01 Torr, the wafer surface in the furnace and the film thickness distribution between the wafers are improved, and it is easy to secure a process margin for bending. Optimal growth temperature when using Si ₂ H ₆ is 400 ° C. to 550 ° C..

Although a lowering of the growth temperature is advantageous for the measure against the curvature, there is a disadvantage that the growth rate is reduced and the throughput is reduced. Therefore, when lowering the temperature, it is effective to use trisilane (Si ₃ H ₈ ) or the like having a high growth rate as the source gas. The optimum temperature when using Si ₃ H ₈ is 350 ° C. to 500 ° C., and the growth rate is 0.1 to 10 nm / min.

[0065] Further, it may be used after diluted with an inert gas such as, for example, helium Si ₂ H ₆ as a source gas (He), but better to use only Si ₂ H ₆ is the film thickness distribution, It has excellent coverage and is effective against bending.

Although the growth rate increases as the gas flow rate increases, the growth rate tends to saturate from a certain amount, and it is preferable to determine the conditions in consideration of the controllability of the growth film thickness and the throughput. Immediately after the growth of the silicon film, immediately after the ion implantation into the silicon film, or immediately after the formation of the SiO ₂ film thereon, 600 to 7
When annealing is performed at a temperature of about 00 ° C. for 30 to 180 minutes,
The crystal growth of the silicon film during the heat treatment in the subsequent process can be made uniform, that is, the internal stress can be made uniform, which is effective against bending.

It should be noted that, when introducing phosphine (PH ₃ ) at the same time as introducing Si ₂ H ₆ to simultaneously carry out growth and impurity introduction, it is effective against bending. A horizontal CVD apparatus may be used, but a vertical CVD apparatus is more advantageous because the film thickness distribution is better and the process margin for bending increases. (C) Description of Insulating Film Supporting Silicon Film in Storage Electrode Forming Process The silicon film serving as the storage electrode is curved because the mutual stress with the SiO ₂ film formed therebetween is different. That has already been mentioned. Also, this mutual stress is mainly
This is because the thermal expansion coefficients of the SiO ₂ film and the silicon film are different.

For this reason, regardless of whether it is polycrystalline or amorphous,
It is effective to determine the respective growth temperatures so as to minimize the difference in thermal expansion between the silicon film and the SiO ₂ film. Specifically, the growth temperature of the SiO ₂ films 14 and 16 is not 800 ° C., but the same as the silicon growth temperature or 1 ° C.
If the temperature difference is set to 00 ° C. or less, the bending is suppressed.

For example, when forming amorphous silicon films 15 and 18 using Si ₂ H ₆ gas at a temperature of 450 ° C.,
The growth temperature of the SiO ₂ films 14 and 16 formed thereon or below may be 450 ° C.

As a result, if the growth methods of the SiO ₂ films 14 and 16 and the silicon films 15 and 18 are devised and the growth temperatures of these films are made equal or close to each other, the mutual stress can be canceled out, which is effective. (D) Description of Growth of Dielectric Film and Counter Electrode In one embodiment of the above-described manufacturing process, the SiO ₂ films 14 and 1
When the support of the fins is eliminated by removing 6, the silicon films 15 and 18 undergo elastic deformation corresponding to the stress. If the stress is equal to or higher than the yield stress of the silicon film, the silicon film is plastically deformed and curved. Further, the yield stress of the silicon film decreases exponentially with an increase in temperature. Therefore, it is important to suppress the heat treatment temperature from the formation of the dielectric film 23 to the formation of the counter electrode 24.

That is, as shown in FIG. 8, the curvature of the fin greatly affects the heat treatment conditions during the growth of the dielectric film 23 of the capacitor, and the lower the temperature of the formation of the dielectric film 23, the more the curvature can be suppressed. I found it.

The reason why the curvature generation rate depends on the temperature at which the dielectric film 23 is formed is that the yield stress of the silicon films 15 and 18 sharply decreases as the temperature rises. Therefore, in principle, a breakdown stress greater than or equal to the stress applied to the silicon films 15 and 18 from the outside is applied.
If the heat treatment temperature is suppressed below the temperature given to 8, the curvature of the fin can be avoided.

Silicon nitride film 21 to be dielectric film 23
Grows generally at about 700 to 800 ° C.,
At a high temperature of about ℃, the yield stress of the silicon film becomes small, plastic deformation may occur, and the fin may be curved,
Set below this temperature.

Further, the surface of the silicon nitride film 21 is heat-treated in an oxygen atmosphere at a temperature of, for example, about 800 to 850 ° C. to form a SiO ₂ film 22 for preventing leakage current. Since the stress is further reduced, plastic deformation as shown in FIG.
Curving occurs. It can be seen that when the SiO ₂ film 22 is formed at about 700 to 725 ° C., deformation hardly occurs as shown in FIG.

The growth of the silicon nitride film 21 is 6
It is also possible pyrogenic up to 50 ° C., although breakdown stress of the silicon film is increased, there is a disadvantage that <br/> that the growth rate decreases. However, the lower the temperature is, the more advantageous the bending is, and it is effective when the degree of integration is further advanced, that is, when it is desired to make the fin thinner. It is important for the oxidation treatment to grow to a constant film thickness, and a low-temperature treatment can be performed by a wet oxidation atmosphere with a high oxidation rate, a high-pressure oxidation method, or the like, which is effective for bending. (E) Description of the size of the storage electrode Further, the curvature of the storage electrode largely depends on the size in the horizontal direction, and as shown in FIG.
They also found that bending was suppressed. FIG. 9 shows a case of using a polycrystalline silicon film.

The reason for depending on the size of the fin is that the absolute value of the stress is proportional to the size. It is effective to reduce the size of the fins, but this conflicts with the demand for securing a large capacity. It should be noted, however, that miniaturization has an advantageous effect on curvature.

As shown in FIG. 4, if the lengths of the left and right fins are made asymmetrical with respect to the contact hole 17, the longer one is more disadvantageous in controlling the curvature. On the other hand, if the layout is symmetrical with respect to the contact hole 17 as shown in FIG. 5, the length l _{3 of the} fin is reduced even if it has the same area as the storage electrode 20 of FIG. The optimum condition is that the contact hole 17 is located below the center of the storage electrode 20.

This is important for preventing bending, regardless of whether it is polycrystalline or amorphous. (F) Description of Comprehensive Conditions for Realizing Thinning of Storage Electrode As is clear from the above description of the embodiment, the following conditions are required to realize the thinning of the fin while suppressing the occurrence of the bending of the storage electrode. Is required.

A method of growing an amorphous or polycrystalline silicon film and an oxide film to reduce the stress of the storage electrode is devised. If the growth temperatures of the oxide film and the silicon film are made equal, mutual stress can be canceled out, which is effective.

Further, impurities are introduced into the silicon film,
Although it is necessary to lower the resistance, for example, when an ion implantation method is used, the implanted portion on the surface is once made amorphous and then crystallized by a heat treatment thereafter. This also changes the internal stress of the silicon film and requires attention. Generally, it is considered that internal stress increases and curvature is promoted. Therefore, it is desirable to grow a silicon film while introducing impurities.

The yield stress of the silicon film is increased. As described above, it is effective to grow the silicon film of the storage electrode in an amorphous state.

Forming thick fins is also effective in suppressing the curvature, but is contrary to the demand for thinner fins. However, since it is also related to the size of the fin, it is practical to set and apply a certain rule between the two.

It is also effective to suppress the heat treatment temperature from fin formation to filling with a counter electrode, such as formation of a dielectric film. In principle, curving can be avoided if the heat treatment temperature is reduced to a temperature equal to or lower than the stress applied to the silicon film and at which the yield stress is applied.

May be used alone, but it is more effective to combine a plurality of them. FIG. 10 shows the area where the fins can be made thinner with respect to the fin thickness size.

That is, in order for the degree of curvature generated in the storage electrode to be practical, the length of the fin from the contact hole and its film thickness must fall within the range below the straight line shown in FIG. These straight lines indicate the limit value under each film forming and heat treatment condition. (G) Other Descriptions In the above embodiment, the storage electrodes of the type in which a dielectric film is formed above and below the fins have been described as an example. However, as shown in FIG. The above-described film growth technique can be applied to a type in which the lower surface is brought into contact with the silicon nitride film 13 and the dielectric films 32 and 33 are formed only on the upper surface.

In this case, the difference from the above-described process is that no SiO ₂ film is formed immediately above the silicon nitride film 13. Reference numerals 34 and 35 indicate opposing electrodes. Further, in the above-described embodiment, the capacitor in which the side section of the storage electrode has a fin shape has been described. However, when a storage electrode having a box shape, a vertical groove shape, or another shape is formed under the same conditions, deformation may occur. Capacitor with less noise.

[0087]

As described above, according to the first aspect,
Since the storage electrode is composed of a polycrystalline semiconductor film having a larger grain size than a polycrystalline semiconductor film from the beginning of film formation, the grain size semiconductor layer has a good surface condition, Even if the thickness is reduced to about nm, a decrease in capacity can be prevented.

According to the second invention, the first invention is used for a fin-type storage electrode, and since a semiconductor film having a large grain size has a large yield stress, it is difficult for the thinned fin to curve. be able to.

According to the third to fifth aspects of the present invention, since an amorphous semiconductor film is grown and used as a fin-shaped storage electrode of a capacitor, its surface condition is good, and further, in the subsequent steps, When polycrystallization is performed, the yield stress increases, so that the capacity of the storage electrode to be thinned can be increased, and the fin can be less likely to be curved.

According to the sixth invention, the amorphous silicon film is
When growing, use Si as the source gas. _TwoH₆Using that
Set the growth temperature between 400 ° C and 550 ° C, or source
Si as gas_ThreeH₈The growth temperature from 350 ° C. to 5 ° C.
Since the temperature is set to 00 ° C., the amorphous semiconductor film
The growth rate is high and the throughput can be improved.
Wear.

According to the seventh and eleventh aspects, since the impurity is introduced into the amorphous semiconductor film, the resistance of the semiconductor film can be reduced without affecting the crystal stress. Eighth,
According to the tenth aspect, when the semiconductor film forming the storage electrode is formed, the growth temperature of the insulating film laminated thereon is equal to or close to the growth temperature of the semiconductor film. Applied stress can be kept low, and the fin of the storage electrode can be hardly bent.

According to the ninth and tenth aspects, the growth temperature of the dielectric film adhered to the periphery of the storage electrode is adjusted to reduce the decrease in the breakdown stress of the fin of the storage electrode. The curvature of the fin can be suppressed.

According to the tenth and eleventh aspects, since the impurity for lowering the resistance is introduced simultaneously with the growth of the polycrystalline semiconductor film, the internal stress is reduced as compared with the case where the impurity is introduced later. And curving can be suppressed.

According to the twelfth aspect, since the contact hole connected to the impurity-introduced layer is provided at the center of the storage electrode, the curvature of the fin can be suppressed as compared with the case where the position is shifted.

[Brief description of the drawings]

FIG. 1 is a sectional view (1) showing a manufacturing process of an apparatus according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view (part 2) illustrating a manufacturing process of the apparatus according to one embodiment of the present invention.

FIG. 3 is a sectional view (No. 3) showing a step of manufacturing the apparatus according to the embodiment of the present invention;

FIG. 4 is a first plan view showing an apparatus according to an embodiment of the present invention.

FIG. 5 is a second plan view showing the apparatus according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view of a device for examining the capacitance of a capacitor and a characteristic diagram showing a relationship between the capacitance and a film growth condition.

FIGS. 7A and 7B are a characteristic diagram showing a relationship between the occurrence rate of the curvature of the storage electrode and a film growth condition, and a cross-sectional view showing an example of the curvature.

FIG. 8 is a characteristic diagram illustrating a relationship between a growth temperature of an oxide film serving as a dielectric film and a rate of occurrence of fin curvature.

FIG. 9 is a characteristic diagram showing a relationship between the length of the fin of the storage electrode and the curvature occurrence rate.

FIG. 10 is a characteristic diagram showing a relationship between the thickness of a fin of a storage electrode that can be used as a capacitor and the length of the fin.

FIG. 11 is a cross-sectional view showing a device according to another embodiment of the present invention.

FIG. 12 shows a DR having a capacitor utilizing a side effect.
FIG. 3 is a cross-sectional view illustrating an example of an AM cell.

FIG. 13 is a cross-sectional view (part 1) illustrating a conventional method for manufacturing a DRAM cell having a fin-type capacitor.

FIG. 14 is a sectional view (part 2) showing a conventional method of manufacturing a DRAM cell having a fin-type capacitor.

[Explanation of symbols]

Reference Signs List 1 semiconductor layer 2 field oxide film 3 gate oxide film 4 polycrystalline silicon 5 word line 6, 7 source / drain layer 8 interlayer insulating film 9 bit line contact hole 12 bit line 13 silicon nitride film 14, 16 SiO ₂ film 15, 18 Silicon film (semiconductor film) 17 Contact hole 19 Groove 20, 30, 31 Storage electrode (first electrode) 23, 32, 33 Dielectric film 24, 34, 35 Counter electrode (second electrode)

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Kono 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within Fujitsu Limited (72) Inventor Hiroshi Nomura 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP-A-5-67730 (JP, A) JP-A-4-35059 (JP, A) JP-A-3-272165 (JP, A) JP-A-5-90490 (JP, A) ( 58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242

Claims (12)

(57) [Claims] A first electrode formed of a polycrystalline semiconductor film having a larger grain size than a polycrystalline semiconductor film from the beginning of film formation, and having a fin-shaped side section;
A semiconductor device having a stacked capacitor including a dielectric film formed on a surface of the first electrode and a second electrode covering the dielectric film. 2. The semiconductor device according to claim 1, wherein said polycrystalline semiconductor film having a large grain size is a semiconductor film obtained by crystallizing an amorphous semiconductor film. A step of forming an impurity introduction layer of an opposite conductivity type in a semiconductor substrate of one conductivity type; a step of forming a first insulating film on the semiconductor substrate; Patterning to form a contact hole exposing a part of the impurity introduction layer, and laminating an amorphous semiconductor film following the surface of the impurity introduction layer through the contact hole from above the first insulating film. During or after the growth of the amorphous semiconductor film, introducing an impurity into the amorphous semiconductor film; and patterning the amorphous semiconductor film to remain in a region including the contact hole. A step of using the amorphous semiconductor film as a first electrode for a capacitor; a step of forming a dielectric film for the capacitor on a surface of the first electrode; and a step of forming a dielectric film for the capacitor covering the dielectric film. Forming a second electrode. A step of forming an impurity introduction layer of an opposite conductivity type in a semiconductor substrate of one conductivity type; a step of sequentially stacking a first insulating film and a second insulating film on the semiconductor substrate; Patterning the first and second insulating films to form a contact hole exposing a part of the impurity introduction layer; and continuing from the upper surface of the second insulation film through the contact hole to the impurity introduction layer. Laminating an amorphous semiconductor film, introducing an impurity into the amorphous semiconductor film during or after the growth of the amorphous semiconductor film, patterning the amorphous semiconductor film, Using the amorphous semiconductor film left in the region including the contact hole as a first electrode for a capacitor; and supplying an etchant through a side of the first electrode to form the second insulating film. Isotropic d Step of selectively removing the dielectric film for the capacitor, forming a dielectric film for the capacitor on the entire surface of the first electrode above the first insulating film, and covering the dielectric film. Forming a second electrode for a capacitor. 5. A step of forming an impurity introduction layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type; a step of forming a first insulating film on the semiconductor substrate; A step of alternately laminating a first amorphous semiconductor film and a third insulating film on at least one layer in order, either directly or via a second insulating film; and Patterning up to the first insulating film to form a contact hole exposing a part of the impurity introducing layer; and forming a contact hole over the uppermost third insulating film through the contact hole to the upper surface of the impurity introducing layer. Stacking a subsequent second amorphous semiconductor film, and patterning a layer from the uppermost third insulating film to the first amorphous semiconductor film to remain in a region including the contact hole; The first and second amorphous semiconductors Forming a first electrode for side section finned capacitor consisting supplies etching liquid through the side of the first electrode,
A step of selectively removing the insulating film above the first insulating film by isotropically etching; and forming the capacitor for the entire surface of the first electrode above the first insulating film. Forming a second electrode for the capacitor covering the dielectric film. A method for manufacturing a semiconductor device, comprising: 6. The amorphous semiconductor film is an amorphous silicon film, which is grown by a low pressure CVD method using disilane as a source gas at a growth temperature of 400 to 550.degree. 6. The method according to claim 3, wherein the semiconductor device is grown by a low pressure CVD method using trisilane as a source gas in a temperature range of 500.degree. 7. The method according to claim 5, wherein an impurity is introduced into the amorphous semiconductor film after the growth. 8. The method according to claim 1, wherein the insulating film laminated on the amorphous semiconductor film is grown at the same temperature as the growth temperature of the amorphous semiconductor film or at a temperature difference of 100 ° C. or less. 6. The method for manufacturing a semiconductor device according to claim 3, wherein: 9. The semiconductor device according to claim 3, wherein said dielectric film is grown at a temperature lower than a temperature at which a stress applied to said storage electrode from outside is applied to said amorphous semiconductor film. Manufacturing method. 10. A step of forming an impurity introduction layer of an opposite conductivity type on a surface of a semiconductor substrate of one conductivity type; a step of forming a first insulating film on the semiconductor substrate; A step of growing a first semiconductor film and a third insulating film alternately at least one layer at the same temperature directly or via a second insulating film on the third insulating film; Forming a contact hole exposing a part of the impurity-introduced layer by patterning from the first to the first insulating film; and an upper surface of the impurity-introduced layer from the uppermost third insulating film through the contact hole. Laminating a second semiconductor film following, and patterning from the uppermost third insulating film to the first semiconductor film and leaving it in a region including the contact hole, the first and second Side section made of semiconductor film Forming a first electrode for a fin-shaped capacitor; and supplying an etchant through the side of the first electrode to isotropically etch the insulating film above the first insulating film. And selectively removing the capacitor for the capacitor at a temperature at which the semiconductor film does not generate a breakdown stress less than an externally applied stress over the entire surface of the first electrode above the first insulating film. A method of manufacturing a semiconductor device, comprising: forming a dielectric film; and forming a second electrode for the capacitor that covers the dielectric film. 11. The amorphous semiconductor film according to claim 5, wherein impurities are introduced simultaneously during growth.
The manufacturing method of the semiconductor device described in the above. 12. The contact hole according to claim 3, wherein the contact hole is located below a center of an upper surface of the first electrode.
11. The method for manufacturing a semiconductor device according to any one of claims 5 to 10.