JP2931371B2 - Semiconductor capacitive element and method of manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor capacitor and a method for manufacturing the same, and
In particular, the present invention relates to a structure for increasing a capacitance value of a semiconductor capacitor included in a cell of a semiconductor memory device and a method of manufacturing the same.

(B) Conventional technology With the recent high integration of semiconductor memory devices, especially DRAM,
There is a need for a reduction in memory size. However, as the memory size has been reduced, the area of the capacitor portion has been reduced, and as a result, there has been a problem that the amount of memory charge is reduced.

For example, up to 1 Mbit is realized with a planar type capacitor and has been put to practical use. Has been studied.

One such structure is a trench capacitor, which is described in detail, for example, in Japanese Patent Application Laid-Open No. 63-174352. Another structure is a stacked capacitor, which is described in detail in, for example, Japanese Patent Application No. 1-298321.

In the latter technique, for example, as shown in FIG. 4, a field insulating film (2) is provided on a P-type semiconductor substrate (1), and a transistor (3) is provided in a region surrounded by the field insulating film (2). Can be

Si surrounded by the field insulating film (2)
A gate (5) made of poly-Si is provided via an O ₂ film (4). Here, the gates (5) and (6) are formed as word lines.

A capacitor electrode (8) in contact with the source region (7) is provided on the source region (7). Further, on the capacitor electrode (8), a first capacitor insulating film (9) and a cell plate electrode ( 10), a second capacitor insulating film (11) and an electrode (12) composed of a polysilicon layer,
(13) is laminated.

Further, a bit line (15) is provided in contact with the drain region (16) via the BPSG film (14), and a passivation film (17) is formed thereon.

The above configuration is a general stacked capacitor.
On the other hand, a trench capacitor has a trench formed in a semiconductor substrate, a thin capacitor insulating film is formed in the trench, and a polysilicon layer is buried. A capacitor is formed between the substrate and the polysilicon layer. It is something to put.

(C) Problems to be Solved by the Invention In general, in order to increase the capacitance value, it is possible to reduce the thickness of the capacitor insulating films (9) and (11) or increase the electrode area of the capacitor. Of course, it is also possible to form a capacitor insulating film having a large dielectric constant.

However, the electrode area is substantially determined by the chip area and the number of cells, and the film thickness of the capacitor insulating film has also reached its limit, so that it is difficult to further increase the capacitance.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems.
The problem is solved by removing the surface of the electrode (8) from either the polycrystalline silicon or the amorphous silicon to form an uneven shape.

(E) Action The silicon surface state changes near the substrate temperature of about 570 ° C. Above about 580 ° C, it becomes polycrystalline silicon, but about 570 ° C
Below, amorphous silicon and polycrystalline silicon are mixed. Therefore, if one silicon is etched in a mixed state, the silicon surface becomes uneven as shown in FIG. 1, and the area of the capacitor electrode can be increased.

For example, when P is doped on a surface where both silicons are mixed, a large amount of P is diffused into a grain boundary existing between amorphous silicon and polycrystalline silicon, and the etching rate in this portion increases. Therefore, when the etching is performed, the grain boundary is removed, and the polycrystalline silicon can be removed.

(F) Example A method for forming an electrode having a concavo-convex shape, which is a point of the present invention, will be described first.

It is generally known that the surface state of a Si film changes at a certain temperature. For example, when a film is formed by thermally decomposing SiH ₄ using the LPCVD method, the temperature changes substantially from about 570 ° C. to about 580 ° C.

According to experimental results, it is a polysilicon film at about 580 ° C or higher, but amorphous silicon (2
1) and polycrystalline silicon are mixed. FIG. 2 shows the size of the polycrystalline silicon when the deposition temperature was changed from 550 ° C. to 570 ° C.

On the other hand, a grain boundary exists at the boundary between amorphous silicon and polycrystalline silicon, and P is set to about 1 × 10 ²⁰ to
When diffusing by 5 × 10 ²¹ cm ⁻¹ , many impurities are diffused into this grain boundary. Therefore, for example, by etching with an HF-based etching solution, particularly the grain boundary can be selectively removed, so that the polycrystalline silicon on the surface can be removed. Wherein diffusion of P is used Pocl _3, 850 ℃ ~
Diffusing at 950 ° C.

As mentioned above, using the methods and conditions described above,
The surface can be made uneven as in the storage node (8) shown in FIG.

Here, since the polycrystalline silicon grains are removed, the periphery of the concave portion becomes an acute angle. Therefore, HF + HNO ₃ type etchant and
If etching is performed using CF ₄ + O ₂ -based gas, the edge of the concave portion can be rounded, and the step coverage of a film to be subsequently deposited can be improved.

Next, take a stacked capacitor as an example,
The structure method will be described.

First, as shown in FIG. 3A, a LOCOS oxide film (2) is formed on a P-type semiconductor substrate (1), and then word lines (5) and (6) are formed via an SiO ₂ film (4). After forming the P
An N ⁺ type source region (7) and an N ⁺ type drain region (16) are formed on a type semiconductor substrate (1).

Next, a capacitor electrode (8) made of polysilicon containing phosphorus in contact with the N ⁺ type source region (7) is formed as a first conductive layer.

As described above, this capacitor electrode (8) is formed in a state where polycrystalline silicon and amorphous silicon are mixed, and as shown in FIG. 1, the polycrystalline silicon on the surface is removed. Subsequently, as shown in FIG. 3B, a cell plate electrode (10) made of polysilicon containing phosphorus is formed as a second conductive layer on the capacitor electrode (8) via a first capacitor insulating film (9). .

Here, the first capacitor insulating film (9) is formed, for example, by accumulating a silicon nitride film to a thickness of about 120 ° by LPCVD and oxidizing it in a DryO ₂ atmosphere at 900 ° C. for 30 minutes.

Next, a second capacitor insulating film (11) is formed on the cell plate electrode (10) under the same conditions.

Subsequently, as shown in FIG. 3C, the cell plate electrode (1
The polysilicon layer (12) covering 0) is deposited as a third conductive layer to a thickness of about 2,000 mm, and phosphorus is diffused at 900 ° C. to reduce the polysilicon layer (12) to a sheet resistance of about 40Ω / port. Lower.

Next, as shown in FIG. 3D, a contact hole reaching the capacitor electrode (8) is formed on the cell plate electrode (10).
H1 is formed by photoetching.

Subsequently, as shown in FIG. 3E, an SiO ₂ film (22) as an insulating film is deposited on the inside of the contact hole H1 and on the polysilicon layer (12) to a thickness of about 1000 ° by LPCVD.

Thereafter, as shown in FIG. 3F, the SiO ₂ film (22) is subjected to an anisotropic etching treatment so that the SiO ₂ film (22) is formed on the capacitor electrode (8) at the bottom of the contact hole H1 and on the polysilicon layer (12). The SiO ₂ film (22) is selectively removed.

In this case, the SiO ₂ film (22) remains on the side wall in the contact hole H1, thereby insulating the cell plate electrode (10).

Next, as shown in FIG. 3G, a polysilicon layer (13) buried in the contact hole H1 and connected to the polysilicon layer (12) is formed as a fourth conductive layer to a thickness of about 1000 ° by LPCVD. Stack. Subsequently, the resistance of the polysilicon layer (13) is reduced by performing phosphorus diffusion under the same conditions, and an ohmic contact is made with the capacitor electrode (8) and the polysilicon layer (12).

Next, unnecessary portions are removed by photo-etching the polysilicon layer (12) and the polysilicon layer (13), and an SiO ₂ film (23) is formed on the surface by block oxidation.

Subsequently, as shown in FIG. 4, BPSG is deposited on the entire surface to form a BPSG film (14), and the surface thereof is flattened, and then a contact hole reaching the N ⁺ type drain region (16) is formed.

Next, after tungsten polycide is deposited and the contact hole is buried, a bit line (15) is formed by photoetching, and PSG is deposited thereon to form a passivation film (17). Complete the DRAM cell.

As described above, since the electrode surface can be made uneven, the electrode area can be increased and the capacitance value can be increased.

Although the present invention has been described by taking a stacked capacitor as an example, it goes without saying that the present invention can also be applied to a trench type capacitor or a normal MOS type capacitor.

Further, depending on an etching solution or an etching gas, it is possible to remove amorphous silicon.

(G) Effects of the Invention As is clear from the above description, the electrode surface of the semiconductor capacitor can be made uneven, so that the capacitance of the capacitor can be increased.

Furthermore, since the size of the polycrystalline silicon can be controlled by controlling the deposition temperature, the capacitance value of each cell can be formed with good reproducibility.

[Brief description of the drawings]

FIG. 1 is an embodiment of the present invention, and is a perspective view for explaining a storage node of a semiconductor capacitor, FIG. 2 is a diagram for explaining the size of polycrystalline silicon depending on a deposition temperature, and FIG. FIGS. 3G and 4 are cross-sectional views for explaining a method of manufacturing a semiconductor capacitor.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27 / 108,21 / 8242 H01L 27 / 04,21 / 822

Claims (7)

(57) [Claims] In a MOS-type semiconductor capacitor formed on a semiconductor substrate, a lower electrode of the capacitor is formed at a temperature lower than a temperature at which polycrystalline silicon is formed. Characterized in that one of the silicon is removed and the surface thereof has an uneven shape. 2. The electrode of the semiconductor capacitor element has an irregular shape with the polycrystalline silicon removed, and the periphery of the concave portion from which the polycrystalline silicon is removed is rounded. The semiconductor capacitor according to claim 1, wherein: 3. A semiconductor capacitor provided adjacent to a transistor in an element region surrounded by a LOCOS oxide film on a semiconductor substrate, wherein a lower electrode constituting the semiconductor capacitor is made of polycrystalline silicon. In a state where polycrystalline silicon and amorphous silicon are mixed by being formed at a temperature lower than
In addition, the surface of the semiconductor capacitor element has an uneven shape by removing one silicon. 4. The electrode of the semiconductor capacitor element has an irregular shape with the polycrystalline silicon removed, and the periphery of the concave portion with the polycrystalline silicon removed is rounded. 4. The semiconductor capacitor according to claim 3, wherein: 5. A method of manufacturing a semiconductor capacitor in which a MOS-type semiconductor capacitor is formed on a semiconductor substrate, wherein the electrode of the semiconductor capacitor is formed at a temperature lower than a temperature at which polycrystalline silicon is formed. A semiconductor formed by mixing polycrystalline silicon and amorphous silicon in a mixed state, removing one of the polycrystalline silicon and amorphous silicon present on the surface of the electrode, and forming the surface of the electrode in an uneven shape. A method for manufacturing a capacitor. 6. The method according to claim 5, wherein said electrode is formed by removing said polycrystalline silicon and rounding the periphery of said removed region. 7. An impurity is introduced into an electrode of the semiconductor capacitor constituted by a mixture of polycrystalline silicon and amorphous silicon by forming a film at a temperature lower than a temperature at which polycrystalline silicon is formed. 6. The method according to claim 5, wherein the etching rate of the grain boundary is varied.