JP4714373B2 - Read circuit for semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a read circuit of a semiconductor memory device, and more particularly to a technique for reducing power consumption in a read circuit of a ROM that reads data written in a memory cell by detecting a current supplied from the memory cell.
[0002]
[Prior art]
A configuration of a read circuit of a conventional semiconductor memory device will be described with reference to the drawings.
[0003]
FIG. 3 shows a read-only memory (ROM) in which a plurality of memory cells are arranged in parallel, and reads data stored in each memory cell by detecting a current supplied from the memory cell. 3 is a circuit configuration of a semiconductor memory device of the type.
[0004]
That is, each drain electrode of a plurality of memory cells (in this embodiment, memory cells M11, M12, M13, and M14 including four N-channel type MOS transistors are illustrated) as switches SW11, SW12, It is formed to be connectable to the bit line BL1 via SW13 and SW14. In FIG. 3, only the bit line BL1 is shown for the sake of convenience, but a plurality of memory cells are similarly arranged on other bit lines (not shown).
[0005]
The source voltage VDD is always applied to the source electrode side. The gate electrodes of the memory cells M11, M12, M13, and M14 are connected to word lines WL1, WL2, WL3, and WL4, respectively.
[0006]
Further, the bit lines BL1,... Are connected to the source electrodes of the selection transistors M15, M16, M17, etc., and are connected to the data read line 1 via the drain electrodes of the selection transistors M15, M16, M17, etc. Has been.
[0007]
Reference numeral 2 denotes a read circuit connected to the data read line 1 via a data input line (IN). The read circuit 2 includes P-channel MOS transistors M2 and N-channel having source electrodes connected to the power supply voltage VDD. An n-channel MOS transistor M1, an n-channel MOS transistor M3 having a source electrode connected to the ground voltage VSS is connected in series, and a p-channel is supplied to the gate electrode of the n-channel MOS transistor M1 for supplying a reference voltage (VREF). The type MOS transistor M4 and the N-channel type MOS transistor M5 are connected in series, and their intersections are connected.
[0008]
Then, a read result from each memory cell is output (OUT) through the data output line 3 from the intersection of the P-channel MOS transistor M2 and the N-channel MOS transistor M1.
[0009]
Hereinafter, the read operation by the read circuit 2 will be described.
[0010]
First, when the selected memory cell is connected to the bit line BL1 (when the selected memory cell is M12, M13, M14), for example, a current is supplied from the memory cell M12 to the transistor M3 of the read circuit 2. The potential of the data input line (IN) rises, and the transistor M1 is turned off as the gate-source voltage Vgs of the transistor M1 decreases. Therefore, “1” is output (OUT) through the data output line 3.
[0011]
Further, when the selected memory cell M11 is not connected to the bit line BL1 (when the selected memory cell is M11), for example, no current is supplied from the memory cell M11 to the transistor M3 of the read circuit 2. Therefore, the potential of the data input line (IN) does not change, and “0” is output (OUT) via the data output line 3.
[0012]
The advantage of the read method for detecting the current supplied from such a memory cell is that the speed can be increased and the read speed does not greatly depend on the capacity of the bit line, so that the capacity can be increased.
[0013]
[Problems to be solved by the invention]
However, the read circuit 2 is at a constant voltage level even during the precharge period, and a constant current flows, which hinders low power consumption.
[0014]
That is, in the above circuit configuration, the ground voltage Vss is applied to the gate electrodes of the P-channel MOS transistor M2 and the P-channel MOS transistor M4 during the precharge period so that the P-channel MOS transistors M2 and M4 are turned on. The power supply voltage VDD is constantly applied to the gate electrode of the N-channel MOS transistor M3 and is always on, so that a current constantly flows through the readout circuit 2.
[0015]
[Means for Solving the Problems]
Accordingly, in view of the above problems, the read circuit of the semiconductor memory device of the present invention is formed such that each drain electrode of a plurality of memory cells can be connected to a bit line via a switch, and each source electrode side always has a power supply. A voltage is applied, and each gate electrode of each memory cell is connected to a corresponding word line, and the memory cell is detected by detecting a current supplied from the memory cell via a data read line in the read circuit of the semiconductor memory device for reading written data in a first transistor having a reference voltage is the gate input, is connected to the first transistor in series, the second of its source electrode connected to the power supply voltage and transistors, connected in series to said first transistor, its source electrode connected to a ground voltage, a gate electrode A third transistor the power supply voltage is constantly applied to the first transistor and the second is connected to the intersection of the transistor data output lines,
A data read line connected to the intersection of the first transistor and the third transistor, a source electrode connected to a power supply voltage, and a drain electrode connected to the gate electrode of the first transistor. and fourth transistor, its source electrode connected to a ground voltage, a fifth transistor whose drain electrode and a gate electrode connected to a gate electrode of the first transistor, comprises a, in the precharge period, the A signal for turning off the transistor is applied to the gate electrode of the second transistor, and a signal for turning off the transistor is applied to the gate electrode of the fourth transistor .
[0017]
Further, a sixth transistor for applying a signal for turning off the transistor is connected to the gate electrode of the fifth transistor during the precharge period.
[0018]
In addition, a seventh transistor having a source electrode connected to the ground voltage and a drain electrode connected to the data output line is applied, and a signal for turning on the seventh transistor is applied during the precharge period. It is characterized by that.
[0019]
Further, it has an eighth transistor whose source electrode is connected to the ground voltage and whose drain electrode is connected to the data read line, and applies a signal for turning on the eighth transistor during the precharge period. It is characterized by that.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a semiconductor memory device of the present invention will be described with reference to the drawings. In addition, about the structure equivalent to a conventional structure (shown in FIG. 3), in order to avoid duplication description, the same code | symbol is attached | subjected and description is simplified.
[0021]
In FIG. 1, in a ROM (read only memory) in which a plurality of memory cells are arranged in parallel, data stored in each memory cell is read by detecting a current supplied from the memory cell. 3 is a circuit configuration of a semiconductor memory device of the type.
[0022]
Here, the circuit configuration which makes the feature of the present invention the read circuit 2 in the precharge period in the ROM structure in which a plurality of memory cells are arranged in parallel on the bit lines BL1... As shown in FIG. This is the addition of a mechanism to turn it off.
[0023]
That is, each drain electrode of a plurality of memory cells (in this embodiment, memory cells M11, M12, M13, and M14 including four N-channel type MOS transistors are illustrated) as switches SW11, SW12, It is formed to be connectable to the bit line BL1 via SW13 and SW14. In FIG. 1, only the bit line BL1 is shown for convenience, but a plurality of memory cells are similarly arranged on other bit lines (not shown).
[0024]
Then, data contents to be written in the memory cells M11, M12, M13, and M14 are determined through the switches SW11, SW12, SW13, and SW14. That is, the memory cell to which “1” data is to be written is connected to the switch, and the memory cell to which “0” data is to be written is not connected to the switch, thereby completing the data writing to each memory cell. In addition, this process is arbitrarily set by the mask switching by the metal mask in a production stage. That is, for example, it is possible by connecting the second layer metal wiring and the third layer metal wiring.
[0025]
The gate electrodes of the memory cells M11, M12, M13, M14 are connected to word lines WL1, WL2, WL3, WL4, respectively.
[0026]
Further, the bit lines BL1... Are connected to the respective source electrodes of the selection transistors M15, M16, M17, etc., and the data read lines are connected through the respective drain electrodes of the selection transistors M15, M16, M17. 1 is connected. Although not shown in the figure, a signal generated inside the circuit is input to each gate electrode of the selection transistors M15, M16, M17... And a read operation is performed in response to the signal. A bit line is selected. Further, before performing a read operation, the data read line 1 is connected with a pre-discharge transistor M8 for setting the potential of the data read line 1 to a predetermined potential (low “L” level in this embodiment). Yes.
[0027]
Reference numeral 2 denotes a current sense type read circuit connected to the data read line 1, and the read circuit 2 includes a P-channel MOS transistor M2, an N-channel MOS transistor M1, whose source electrode is connected to the power supply voltage VDD. An N-channel MOS transistor M3 having a source electrode connected to the ground voltage VSS is connected in series, and a P-channel MOS transistor M4 is supplied to the gate electrode of the N-channel MOS transistor M1 in order to supply a reference voltage (VREF). , N-channel MOS transistors M5 are connected in series, and their intersections are connected.
[0028]
Further, the / CLK signal obtained by inverting the clock (CLK) signal generated inside the circuit through the inverter 4 is supplied to the gate electrodes of the P-channel MOS transistor M2 and the P-channel MOS transistor M4. The gate electrode of the channel type MOS transistor M5 is connected to the drain electrode of an N channel type MOS transistor M6 to which the / CLK signal is input to the gate electrode. Further, the drain electrode of the N-channel MOS transistor M7 to which the / CLK signal is input to the gate electrode is connected to the data output line 3. Furthermore, the / CLK signal is input to the gate electrode of the pre-discharge transistor M8.
[0029]
Then, a read result from each memory cell is output (OUT) through the data output line 3 from the intersection of the P-channel MOS transistor M2 and the N-channel MOS transistor M1.
[0030]
In the semiconductor memory device configured as described above, both the P-channel MOS transistors M2 and M4 are turned off during the precharge period (because the / CLK signal is at the high “H” level) as shown in FIG. When the N-channel MOS transistors M6 and M7 are both turned on, the read circuit 2 can be turned off. At this time, no current flows because the pre-discharge transistor M8 to which the / CLK signal of the “H” level is gate-input is turned on and the precharge voltage becomes the ground voltage VSS.
[0031]
Therefore, the semiconductor memory device of the present invention realizes a circuit configuration in which no current flows during the precharge period, and thus can reduce power consumption as compared with the conventional circuit configuration.
[0032]
Finally, at the time of reading, as shown in FIG. 2, both the P-channel MOS transistors M2 and M4 are turned on and the N-channel MOS transistors M6 and M7 are both turned off based on the “L” level / CLK signal. Thus, a normal read operation by the read circuit 2 is performed. That is, for example, data (A0data) at address A0 specified by address data (ADDR) is output from the data output line 3. The same applies hereinafter.
[0033]
In this embodiment, the ROM is configured by arranging a plurality of N-channel MOS transistors in parallel. However, a plurality of P-channel MOS transistors may be arranged in parallel. First, a plurality of memory cells are connected in parallel to a bit line via a source electrode, and a power supply voltage VDD is applied to each drain electrode of the plurality of memory cells to detect a current supplied from each memory cell. Thus, a read circuit for reading data written in the memory cell is provided.
[0034]
【The invention's effect】
According to the present invention, by realizing a circuit configuration in which no current flows during the precharge period, it is possible to reduce power consumption compared to a conventional circuit configuration.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a timing chart for explaining a data read operation according to the present invention.
FIG. 3 is a circuit diagram for explaining a conventional semiconductor memory device;
[Explanation of symbols]
M1 N-channel MOS transistor (first transistor)
M2 P-channel MOS transistor (second transistor)
M3 N-channel MOS transistor (third transistor)
M4 P-channel MOS transistor (fourth transistor)
M5 N-channel MOS transistor (fifth transistor)
M6 N-channel MOS transistor (sixth transistor)
M7 N-channel MOS transistor (seventh transistor)
M8 pre-discharge transistor (8th transistor)
M11 Memory cell M12 Memory cell M13 Memory cell M14 Memory cell BL1 Bit line 1 Data read line 2 Read circuit 3 Data output line

Claims (4)

Each drain electrode of a plurality of memory cells is formed so as to be connectable to a bit line via a switch, and a power supply voltage is always applied to each source electrode side, and each gate electrode of each memory cell is In a read circuit of a semiconductor memory device that is connected to a corresponding word line and reads data written in the memory cell by detecting a current supplied from the memory cell via a data read line,
A first transistor gated to a reference voltage;
A second transistor connected in series with the first transistor, the source electrode of which is connected to a power supply voltage;
A third transistor connected in series to the first transistor, whose source electrode is connected to a ground voltage, and whose power supply voltage is constantly applied to its gate electrode ;
A data output line connected to an intersection of the first transistor and the second transistor;
A data read line connected to an intersection of the first transistor and the third transistor;
A fourth transistor having its source electrode connected to the power supply voltage and its drain electrode connected to the gate electrode of the first transistor;
A fifth transistor having its source electrode connected to the ground voltage, its drain electrode and gate electrode connected to the gate electrode of the first transistor , and
A signal for turning off the transistor is applied to the gate electrode of the second transistor and a signal for turning off the transistor is applied to the gate electrode of the fourth transistor during a precharge period. A reading circuit of a memory device.   6. The read circuit of the semiconductor memory device according to claim 1, wherein a sixth transistor that applies a signal for turning off the transistor is connected to a gate electrode of the fifth transistor during a precharge period.   It has a seventh transistor having its source electrode connected to the ground voltage and its drain electrode connected to the data output line, and applying a signal for turning on the seventh transistor during the precharge period. 2. The read circuit of the semiconductor memory device according to claim 1, wherein   It has an eighth transistor having its source electrode connected to the ground voltage and its drain electrode connected to the data read line, and applying a signal for turning on the eighth transistor during the precharge period. 2. The read circuit of the semiconductor memory device according to claim 1, wherein

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