JP2853359B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
More particularly, the present invention relates to a semiconductor integrated circuit having a logic circuit including a Schottky junction field effect transistor formed on a gallium arsenide substrate.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit including an input circuit having an input logic level conversion circuit formed on a semiconductor substrate and including a field effect transistor (hereinafter abbreviated as FET) and a diode, an input logic level conversion circuit is provided. The output voltage of the internal logic circuit is always equal to the input logic threshold value of the internal logic circuit connected to this circuit. It always holds well against fluctuations.

Conventionally, this type of semiconductor integrated circuit (hereinafter referred to as Ga
In an As IC), a single-ended logic circuit is widely used because a circuit margin is relatively easily secured due to the simplicity of the circuit and a high voltage gain.

[0004] Typical circuits are shown in FIGS. 5 (a) and 5 (b). The internal logic circuit 9 in FIG.
And is composed of a depletion-type load FET Q1a and an enhancement-type drive FET Q2a. The internal logic circuit 9b in FIG. 5B is called a BFL,
Depletion type FETs all having the same threshold voltage
Q1b, Q2a, Q3a, Q4a and a level shift diode D2.

Usually, an input logic level conversion circuit 10a is provided because the logic level inside the GaAs IC does not match the external logic level. Generally, an ECL level is often used in a high-speed digital signal processing system. Therefore, in this circuit, the power supply voltage VD
D is the ground voltage, and the source power supply voltage is VSS1 = −2.
V, VSS2 = −5.2V.

The level matching with the external logic level is GaAs
s Indispensable for realizing the ultra-high speed of the IC.
In particular, at the ECL level, the voltage between the peaks of the logical amplitude is 0.7 to 0.8V. Therefore, it is necessary to suppress the level matching error within a range of about ± 100 to 200 mV. In other words, the input logic level conversion circuit needs to have some adjustment function to maintain logic level matching with respect to power supply voltage fluctuation or device parameter fluctuation due to temperature.

However, the input logic level conversion circuit 10a shown in FIGS. 5A and 5B does not have such a function. For example, the allowable range of the first source power supply voltage VSS1 is ± (100 to 1).
50) mV or less, and furthermore, there is a problem that the temperature dependence (about -1 mV / .degree. C.) of the level shift amount Vf of the level shift diode D1 is weak against temperature fluctuation.
In the above ultra-high-speed region, the maximum operating speed of the GaAs IC is often determined by the level consistency of the input logic level converter, which is a problem. In general, large-scale integrated circuits tend to improve FET performance and reduce logic amplitude in order to simultaneously achieve low power consumption and high speed. In this case, the problem of the level matching becomes particularly remarkable, which is a large barrier in practical use of the GaAs IC.

On the other hand, in the BFL circuit shown in FIG. 5B, when the gate widths and threshold voltages of the FETs Q1b and Q2a are equal, the logic threshold value of the BFL inverter is equal to the first source voltage VSS1. In this case, although the temperature fluctuation of the logical threshold is removed, the above-described problem of the level matching cannot be solved due to the temperature dependency of the level shift diode D1. In this case, the diode Vf
Japanese Patent Application No. 1-167922 proposes an input logic level conversion circuit having a function of adjusting the temperature characteristics of the first embodiment and the fluctuation of the first source power supply voltage VSS1.

FIG. 6 shows this conversion circuit. By imposing the condition of the following equation (1) between the numbers of the respective diode groups, the internal output terminal voltage V3 becomes the equation (2).

N1 + (N2−n2) − (N3−n3) = 0 (1) V3 = VSS1 + (VIN−Vref) (2) Here, the input signal VIN is the reference signal voltage Vref. V3 becomes equal to VSS1. By connecting 9b to the internal logic circuit which is a BFL when the gate widths of the FETs Q1b and Q2a are set equal, the deviation of the input logic level due to the fluctuation of the first source power supply voltage VSS1 and the temperature fluctuation can be completely eliminated. Compensation and adjustment are possible, and the maximum operating speed of the GaAs IC can be improved, the operating temperature range can be expanded, and the power supply fluctuation allowable range can be expanded.

However, the input logic level conversion circuit 10 shown in FIG.
a, the input logic threshold of which is equal to the first source voltage VSS1
For a circuit not equal to the above, the above-mentioned compensation function is inadequate, and the power supply tolerance and the temperature dependency of the level matching cannot be adjusted.

Therefore, in order to realize high integration and high speed,
GaAs I composed of single-ended logic circuit
Regarding the input circuit of C, regardless of the type of the internal logic circuit,
It has a compensation / adjustment function for always maintaining good level matching between the external logic level and the internal logic circuit logic level against fluctuation factors such as power supply voltage (VSS1) fluctuation, temperature fluctuation, and device parameter fluctuation due to manufacturing fluctuation. Things are necessary.

[0013]

However, in the conventional semiconductor integrated circuit, there is no input circuit having the above-described compensation / adjustment function for combinations with all kinds of internal logic circuits, and the fluctuation tolerance of level matching is improved. There was no circuit to improve.

An object of the present invention is to provide an input circuit capable of maintaining a logical level matching between an external input signal level and an internal logic circuit with respect to power supply voltage fluctuations and temperature fluctuations for all kinds of internal logic circuits. Another object of the present invention is to provide a semiconductor integrated circuit having a low logic amplitude.

[0015]

According to a semiconductor integrated circuit of the present invention, an internal logic circuit and an external input signal are supplied to a predetermined reference voltage.
Logic level conversion to convert to and input to internal logic circuit
Circuit and input logic level conversion circuit for generating a predetermined voltage
Has a reference voltage generation circuit for giving a reference voltage to the
The logic level conversion circuit has a drain connected to the drain power supply
, Second and third upper field effect transistors
And the first, second and third upper field effect transistors
, Second and third diodes connected to the sources of
Group, said first, second and third upper field effect transistors
Through the first, second, and third diode groups, respectively.
And the upper field-effect transistor connected to the drain
First, second, and third lower field effect transistors having the same configuration
And second and third lower field effect transistors at one end.
The other end of which is connected to the second source power supply
And a fifth diode group.
Diode group is from lower field effect transistor to upper field
N1, n2, n
Four forward diodes are connected in series.
The fifth diode group is a lower field-effect transistor, respectively.
N2 and N3 in order from
Direction diodes are connected in series, and the first to fifth
All diodes in the group are the same electric
It has characteristics and the number thereof satisfies the relationship of the above-mentioned formula (1).
The first lower field-effect transistor has a gate and a source.
Is connected to a second source power supply and the drain is connected to a second
Connected to the gate of the lower field-effect transistor,
The drain of the lower field effect transistor is the third lower field
Connected to the first, second, and third effect transistors.
The gate of the upper field-effect transistor has a reference voltage
The reference voltage, reference signal, and external signal are input from the voltage generation circuit.
And a drain of said third lower field effect transistor
The logic-level-converted signal is output from the
Internal logic circuit and reference voltage generation circuit
Both have one field-effect transistor and internal logic
Circuit element commonly included in circuit and reference voltage generation circuit
Have the same electrical characteristics and are output by the reference voltage generation circuit
Reference voltage is equal to logic threshold in internal logic circuit
Is a potential.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. Field effect transistors Q11 and Q12, Q13 and Q14 of the input logic level conversion circuit 10, and FET Q
The three pairs of upper and lower pairs of FETs 15 and Q16 have the same gate length and gate width, are formed of the same active layer, and are set to exhibit exactly the same electrical characteristics. Further, first to fifth diode groups n1 to n3 and N
2 and N3 are set so as to show exactly the same forward voltage Vf. Usually, the active layer of the diode and the active layer of each FET are formed by the same process, so that the above-described pairing can be easily realized. Further, the number of each diode is set so as to satisfy the above equation (1).

Next, the operation of the present invention will be described. Here, each symbol is set as follows. V1 is the internal output terminal 1
4, V2 is the voltage of the internal output terminal 15, V3 is the voltage of the internal output terminal 16 (internal logic circuit input voltage), Vre
f is the reference signal voltage, VIN is the input signal voltage, VS is the reference voltage, and the negative direction of the potential difference when the power supply VDD is the ground voltage (0 V) is positive. In this case, Q1
When all FETs of 1, Q12, Q13, Q14, Q15, Q16 are set to be always in the saturation region,
The relationship of the expressions (3) to (5) is established, and the expression (6) is obtained from the setting conditions of the above expression (1).

V1 = VS + n1Vf (3) V2 = Vref + (VSS2-V1)-(N2-n2) Vf (4) V3 = VIN-Vref + (N2-n2) Vf + V1- (N3-n3) Vf = VS + ( VIN-Vref) + [n1 + (N2-n2)-(N3-n3)] Vf (5) V3 = VS + (VIN-Vref) (6) Here, when the input signal is at the logical threshold, Since VIN and Vref are equal, V3 and VS are also equal.

As described above, the output voltage V3 of the output terminal 16 input to the internal logic circuit 9 in the IC is equal to the reference voltage VS as long as all the FETs Q11 to Q16 are in the saturation region and exhibit a constant current characteristic. , Other elements are not included. Therefore, when the reference voltage VS is equal to the logic threshold value VLth of the internal logic circuit, ie, VS = VLth,
The two problems of the prior art can be improved simultaneously for all types of internal logic circuits. Specifically, first,
The input potential of the internal logic circuit is always equal to the input logic threshold value, and the resistance to power supply voltage fluctuation is improved. Second,
Immunity to device parameter temperature fluctuations and manufacturing variations, including diode forward voltage, is improved.

A reference voltage generating circuit 19 for supplying a reference voltage VS to a reference voltage terminal 20 of the same input logic level conversion circuit 10 comprises a depletion FET Q1, an enhancement type FET Q2, a series negative feedback resistor Rf, and a parallel capacitance. Cf. The FETs Q1 and Q2 are set so as to have the same structure and performance as the load FET Q1a and the drive FET Q2a that constitute the internal logic circuit 9 (referred to as an E / D configuration DCFL circuit). First stage F
The gate of ET Q2 is connected to the source electrode of Q1 via a feedback circuit including a series negative feedback resistor Rf and a parallel capacitor Cf for preventing oscillation.

In this case, the output potential VS of the reference voltage terminal 20 is obtained from the operating point P shown in FIG. Since Q1 and Q2 are set to exactly the same FETs as Q1a and Q2a in the internal logic circuit 9, the output potential VS with respect to the operating point P is always the logic threshold VL of the internal logic circuit.
equal to th. Although the reference voltage generating circuit 19 forms a negative feedback circuit, the ring oscillation operation is shown because the gain in the high frequency range is attenuated by a kind circuit of the series negative feedback resistor Rf and the parallel capacitance Cf. And generates the reference voltage VS stably.

In this case, the reference voltage VS automatically becomes equal to VLth irrespective of VSS1 or device parameter fluctuation. Therefore, as described in the description of FIG. 1, according to the present embodiment, the input logic level matching of the semiconductor integrated circuit in which the internal logic circuit 19 is formed by the E / D configuration DCFL circuit depends on the power supply voltage fluctuation or the temperature fluctuation. Is always kept good.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. The resistance RL of the reference voltage generation circuit 19a and the first-stage drive transistor Q2 are connected to the internal resistance RL of the internal logic circuit 9a.
And the same manufacturing process so that the same electrical characteristics as those of the FET Q2a can be obtained. Resistance RL and FET Q
The output terminal of the ER-configured DCFL inverter 2a is connected to the gate of an inverter input FET Q2 via a feedback circuit including a series resistor Rf and a parallel capacitor Cf. Therefore, in this case, the reference voltage terminal output voltage VSa
Is basically (ER) as described in the circuit operation of FIG.
It becomes equal to the logic threshold value VLth in the internal logic circuit 9a of the configuration DCFL). Therefore, according to the present embodiment, E
The input logic level matching in the semiconductor integrated circuit composed of the R-configuration DCFL circuit is caused by power supply voltage fluctuation or temperature fluctuation.
Irrespective of manufacturing variations, etc., it is possible to always keep good.

FIG. 4 is a circuit diagram of a specific embodiment of the present invention with respect to the case where the internal logic circuit 9b is constituted by BFL. FETs Q1 and Q in reference voltage generation circuit 19b
2, Q3, Q4 and the diode D2 are connected to the internal logic circuit 9
It is formed by the same manufacturing process so that its electric characteristics are the same as those of the FETs Q1b, Q2a, Q3a, Q4a and the diode D2a that constitute b. Therefore FET
The reference voltage generating circuit 19b including Q1 to Q4 and the diode D2 functions as the same BFL inverter as the BFL inverter forming the internal logic circuit 9b, and its output terminal 20 has a negative feedback circuit including a series resistor RL and a parallel capacitor Cf. , Is connected to the gate of the first-stage FET Q2 which is the inverter input.

The reference voltage VSb in this case is also the logical threshold value VLt in the internal logic circuit 9b as described with reference to FIG.
h. Therefore, according to the present embodiment, the input logic level matching in the semiconductor integrated circuit constituted by the BFL circuit can always be maintained satisfactorily irrespective of the power supply voltage or temperature fluctuation.

The present invention is effective for all types of internal logic circuits other than the single-ended type. Further, by improving the level matching margin, the internal logic amplitude can be further reduced. Therefore, the present invention is extremely effective for reducing the power consumption and increasing the speed of the GaAs IC.

[0027]

As described above, according to the present invention, in an input level conversion circuit composed of an FET and a diode group, a specific restriction is imposed on the number of diodes in the diode group to cause a temperature change or the like in the level conversion. The following effects can be obtained by providing a function of completely compensating and canceling device parameter variations that occur and using the output of a reference voltage generation circuit that automatically generates an internal logic threshold as one reference input of the input level conversion circuit. Is generated.

As a result, first, it is possible to improve the power supply fluctuation tolerance in matching the external input signal level with the logic level of the internal logic circuit. Second, it is possible to completely eliminate the influence of device parameter fluctuations due to temperature fluctuations or manufacturing fluctuations on the level matching. Third, the first and second improvements can be simultaneously realized for all types of internal logic circuits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram for explaining an operation of the reference voltage generating circuit of FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

FIGS. 5A and 5B are circuit diagrams of two examples of a conventional semiconductor integrated circuit, respectively.

FIG. 6 is a circuit diagram of an example of a conventional input logic level conversion circuit.

[Explanation of symbols]

Q1, Q1a Load field effect transistor Q2, Q2a Driving field effect transistor Q3, Q3a, Q4, Q4a Field effect transistor Q11, Q13, Q15 Upper field effect transistor Q12, Q14, Q16 Lower field effect transistor Rf Negative feedback resistor Cf Capacitive element VS Reference voltage V3 Internal logic circuit input voltage VIN External signal voltage Vref Reference signal voltage 11, 12, 13 Power supply terminal 14, 15, 16 Internal output terminal 17 Reference signal input terminal 18 External signal input terminal 19, 19a Reference voltage generation circuit 20 Reference voltage terminal

Claims (4)

(57) [Claims] 1. An internal logic circuit, an input logic level conversion circuit for converting an external input signal into a predetermined reference voltage and inputting it to the internal logic circuit, and a predetermined voltage for generating a predetermined voltage to the input logic level conversion circuit A reference voltage generation circuit for providing a reference voltage, wherein the input logic level conversion circuit includes first, second, and third upper field-effect transistors each having a drain connected to a drain power supply; A first, a second, and a third diode group connected to the source of a third upper field-effect transistor; and the first, second, and third diodes from the first, second, and third upper field-effect transistors, respectively. A first, a second, and a third lower field-effect transistor having the same configuration as the upper field-effect transistor connected to the drain via a third diode group; Fourth and fifth diode groups each having the other end connected to a second source power supply at the source of the transistor, wherein the first, second, and third diode groups are connected from an upper field-effect transistor to a lower field-effect transistor. N1, n2, and n3 forward diodes are respectively connected in series toward the transistor, and the fourth and fifth diode groups are respectively N2, N3 from the lower-stage field-effect transistor toward the source power supply. Are connected in series, and all the diodes included in the first to fifth diode groups have the same electrical characteristics and the number is n1 + (N2-n2)-(N3-n3 ) = 0, the first lower-stage field-effect transistor has a gate and a source connected to the second source power supply and a drain connected to the second lower-stage power supply. The drain of the second lower-stage field-effect transistor is connected to the gate of the field-effect transistor, and the drain of the second lower-stage field-effect transistor is connected to the gate of the first, second, and third upper-stage field-effect transistors. Each receives a reference voltage, a reference signal, and an external signal from the reference voltage generation circuit,
A logic-level-converted signal is output from the drain of the third lower-stage field-effect transistor; the internal logic circuit and the reference voltage generation circuit each include at least one field-effect transistor; Circuit elements commonly included in the internal logic circuit and the reference voltage generation circuit have the same electrical characteristics, and the reference voltage output from the reference voltage generation circuit is equal to a logic threshold in the internal logic circuit A semiconductor integrated circuit having a potential. 2. The internal logic circuit includes a depletion type load field effect transistor having a drain connected to a drain power supply and a gate connected to a source, a drain connected to a source of the load field effect transistor, and a source connected to the source. An output signal from the input logic level conversion circuit is input to a gate of the driving field effect transistor, and a logic signal is input from a drain of the driving field effect transistor to a gate of the driving field effect transistor. A reference voltage generating circuit, wherein the reference voltage generating circuit has a drain connected to a drain power supply and a gate connected to a source; and a drain connected to a source of the load field effect. And the source connected to the first source power supply A driving field effect transistor, wherein a negative feedback resistor for connecting the drain and gate of the drive field effect transistor, the parallel connected between the gate and the drain power supply or the first source power supply of the driving electric field effect transistor A driving element for outputting a reference voltage from a drain of the driving field effect transistor via a negative feedback resistor, and a driving field effect transistor for the internal logic circuit and a driving field effect transistor for the reference voltage generation circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the load field-effect transistor of the internal logic circuit and the load field-effect transistor of the reference voltage generation circuit have the same electrical characteristics. 3. An enhancement-type drive field effect device comprising: a load resistor having one end connected to a drain power supply; and a drain connected to the other end of the load resistance and a source connected to a first source power supply. An output signal from the input logic level conversion circuit is input to a gate of the driving field effect transistor, and a logic signal is output from a drain of the driving field effect transistor. A load resistor having one end connected to a drain power supply, an enhancement type drive field effect transistor having a drain connected to the other end of the load resistor and a source connected to the first source power supply, and a drain of the drive field effect transistor. A negative feedback resistor connecting the gate and the gate; and a gate and the drain of the driving field effect transistor. And a parallel capacitance element connected between the power supply and the first source power supply, and outputs a reference voltage from the drain of the drive field effect transistor. 2. The driving field effect transistor of the reference voltage generation circuit, the load resistance of the internal logic circuit, and the load resistance of the reference voltage generation circuit have the same electrical characteristics, respectively. Semiconductor integrated circuit. 4. The internal logic circuit includes a first field-effect transistor having a drain connected to a drain power supply and a gate connected to a source, a drain connected to a source of the first field-effect transistor, and a source connected to the first field-effect transistor. a second field effect transistor connected to the first source power, and the third field effect transistor whose gate is connected drain to drain power supply is connected to the drain of the second field effect transistor, one end of the A diode connected to the source of the third field-effect transistor and directed in the forward direction toward the other end, and a fourth field-effect transistor having the drain connected to the other end of the diode and the gate and the source connected to the second source power supply A transistor, and an output signal from the input logic level conversion circuit is input to a gate of the second field-effect transistor; Outputting a logic signal from the drain of the fourth field-effect transistor, wherein the reference voltage generation circuit includes a first field-effect transistor having a drain connected to a drain power supply and a gate connected to a source. A second field effect transistor having a drain connected to a source of the first field effect transistor and a gate and a source connected to a first source power supply; and a second field effect transistor having a drain connected to a drain power supply and having a gate connected to the second field effect transistor A third field-effect transistor connected to the drain of the third field-effect transistor, a diode connected at one end to the source of the third field-effect transistor and directed toward the other end, and a gate connected at the other end of the diode to the drain. And a fourth field-effect transistor having a source connected to a second source power supply; and a second field-effect transistor. A negative feedback resistor connecting the source of the transistor and the drain of the fourth field-effect transistor; and a parallel connection connected between the gate of the second field-effect transistor and the drain power supply or the first source power supply. A capacitive element,
Outputting a reference voltage from the drain of the fourth field-effect transistor; first, second, third, and fourth field-effect transistors and diodes of the internal logic circuit; 2. The semiconductor integrated circuit according to claim 1, wherein the second, third, and fourth field-effect transistors and the diode have the same electrical characteristics.