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JP2857439B2 - Wiring capacity calculator - Google Patents
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JP2857439B2 - Wiring capacity calculator - Google Patents

Wiring capacity calculator

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Publication number
JP2857439B2
JP2857439B2 JP2001928A JP192890A JP2857439B2 JP 2857439 B2 JP2857439 B2 JP 2857439B2 JP 2001928 A JP2001928 A JP 2001928A JP 192890 A JP192890 A JP 192890A JP 2857439 B2 JP2857439 B2 JP 2857439B2
Authority
JP
Japan
Prior art keywords
wiring
capacitance
wiring capacitance
unit
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2001928A
Other languages
Japanese (ja)
Other versions
JPH03206646A (en
Inventor
弘樹 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP2001928A priority Critical patent/JP2857439B2/en
Publication of JPH03206646A publication Critical patent/JPH03206646A/en
Application granted granted Critical
Publication of JP2857439B2 publication Critical patent/JP2857439B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔概要〕 半導体集積回路の配線パターンの設計時に各配線の配
線容量を算出する配線容量算出装置に関し、 設計段階での計算上の配線容量と実際の集積回路上で
の配線容量との間で誤差を生じさせることのない配線容
量算出装置を提供することを目的とし、 配線層及び配線の位置座標データを入力する入力装置
と、配線が他の配線層と重ならないで形成された場合の
単位配線容量と配線が他の配線層と重なって形成された
場合の単位配線容量とを予め記憶した単位配線容量記憶
装置と、前記入力装置からのデータと前記配線容量記憶
装置からのデータとに基づいて、配線を他の配線層と重
ならない部分と他の配線層と重なる部分とに分割すると
共に、該配線の他の配線層と重ならない部分の配線容量
と該配線の他の配線層と重なる部分の配線容量とを各々
計算して総和を算出する配線容量演算装置とを備えて構
成する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a wiring capacitance calculating device that calculates a wiring capacitance of each wiring when designing a wiring pattern of a semiconductor integrated circuit, and relates to a calculated wiring capacitance in a design stage and an actual wiring capacitance in an integrated circuit. An object of the present invention is to provide a wiring capacitance calculating device that does not cause an error between the wiring capacitance and an input device for inputting position coordinate data of a wiring layer and a wiring, and that the wiring does not overlap with another wiring layer. A unit wiring capacitance storage device in which a unit wiring capacitance when formed and a unit wiring capacitance when wiring is overlapped with another wiring layer are stored in advance, and data from the input device and the wiring capacitance storage device Based on the data from, the wiring is divided into a part that does not overlap with another wiring layer and a part that overlaps with another wiring layer, and the wiring capacitance of the part that does not overlap with the other wiring layer and the wiring Other distribution And a wiring capacitance calculating device for calculating a wiring capacitance of a portion overlapping the line layer and calculating a total sum.

〔産業上の利用分野〕[Industrial applications]

この発明は半導体集積回路の配線パターンの設計時に
各配線の配線容量を算出する配線容量算出装置に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring capacitance calculating device that calculates a wiring capacitance of each wiring when designing a wiring pattern of a semiconductor integrated circuit.

近年の半導体集積回路ではその高集積化に基づいて多
層配線構造が採用されたり、あるいは各配線間の距離が
益々近接した状態で設計されている。このような半導体
集積回路では各配線間に生ずる配線容量がその動作に大
きな影響を及ぼすため、配線パターンは各配線間の配線
容量が所定値を満足するか否かがあらかじめ計算された
上で設計されている。
2. Description of the Related Art In recent years, a semiconductor integrated circuit has adopted a multi-layer wiring structure based on its high integration, or has been designed in a state in which the distance between wirings is becoming increasingly closer. In such a semiconductor integrated circuit, the wiring capacitance generated between the wirings has a great effect on its operation. Therefore, the wiring pattern is designed after calculating in advance whether the wiring capacitance between the wirings satisfies a predetermined value. Have been.

〔従来の技術〕[Conventional technology]

第5図に示すような集積回路パターンの配線容量を配
線容量演算装置で算出する為の従来の手順を説明する
と、同図において多数の記憶素子が形成されるメモリ部
1にはX−Y方向(紙面において縦方向をX方向、横方
向をY方向とする)に矩形に折れ曲がる第一及び第二の
配線2,3が接続され、同メモリ部1の近傍にはY方向に
直線状の第三の配線4が設けられる。このような各配線
2,3,4のX方向の配線部分とY方向の配線部分とは上下
方向において別々の配線層に形成されてそれぞれコンタ
クトホール10で接続されている。また、同図に鎖線のハ
ッチングで示すようにメモリ部1の上層には同メモリ部
1に電源を供給するための電源配線層5がメモリ部1と
ほぼ同一面積で形成される。
A conventional procedure for calculating a wiring capacitance of an integrated circuit pattern as shown in FIG. 5 by a wiring capacitance calculating device will be described. In FIG. First and second wirings 2 and 3 which are bent in a rectangular shape (the vertical direction is defined as the X direction and the horizontal direction is defined as the Y direction in the drawing) are connected to each other. Three wirings 4 are provided. Each such wiring
2, 3, and 4 wiring portions in the X direction and the wiring portion in the Y direction are formed in separate wiring layers in the vertical direction, and are connected to each other by contact holes 10. Further, as shown by hatching in the figure, a power supply wiring layer 5 for supplying power to the memory unit 1 is formed in substantially the same area as the memory unit 1 above the memory unit 1.

このような各配線2,3,4の配線容量は算出装置の入力
装置から各配線2,3,4のX−Y座標データを入力する
と、同算出装置により各配線2,3,4のX方向及びY方向
の配線長に基づいてその配線容量が算出される。すなわ
ち、例えば第一の配線2ではX方向の配線部分の単位長
当たりの単位配線容量及びY方向の配線部分の単位長当
たりの単位配線容量とX方向及びY方向の配線長との積
によりその配線容量が算出され、例えば第三の配線4で
はY方向の配線の単位配線容量と配線長との積によりそ
の配線容量が算出される。
When the XY coordinate data of each of the wirings 2, 3, and 4 is input from the input device of the calculating device, the wiring capacity of each of the wirings 2, 3, and 4 is calculated by the calculating device. The wiring capacitance is calculated based on the wiring lengths in the direction and the Y direction. That is, for example, in the first wiring 2, the unit wiring capacitance per unit length of the wiring part in the X direction and the unit wiring capacitance per unit length of the wiring part in the Y direction are multiplied by the product of the wiring lengths in the X and Y directions. The wiring capacitance is calculated. For example, the wiring capacitance of the third wiring 4 is calculated by the product of the unit wiring capacitance of the wiring in the Y direction and the wiring length.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上記のような算出装置による配線容量の算出手順では
第一及び第二の配線2,3において電源配線層5に重なる
位置での単位配線容量の増大を全く考慮していないが、
電源配線層5の面積が狭く、その電源配線層に重なる配
線長が比較的短いため、各配線2,3の計算上の配線容量
と実際の配線容量とに大きな誤差は生じなかった。
Although the calculation procedure of the wiring capacitance by the above-described calculating device does not consider the increase of the unit wiring capacitance at the position overlapping the power supply wiring layer 5 in the first and second wirings 2 and 3,
Since the area of the power supply wiring layer 5 was small and the wiring length overlapping the power supply wiring layer was relatively short, there was no large error between the calculated wiring capacitance of each of the wirings 2 and 3 and the actual wiring capacitance.

ところが、近年のメモリ部1の高速化の要請により、
第6図に示すように電源配線層5がメモリ部1の上層に
おいて広い範囲に拡大されると、前記各配線2,3,4にお
いて電源配線層5に重なって単位配線容量が大きくなる
部分が増大するため、計算上の配線容量と実際の配線容
量とに大きな誤差が生じてこの集積回路の正常な動作を
妨げることがあるという問題点があった。
However, due to the recent demand for faster memory units 1,
As shown in FIG. 6, when the power supply wiring layer 5 is expanded in a wide range in the upper layer of the memory section 1, a portion where the unit wiring capacity becomes large in each of the wirings 2, 3, and 4 overlaps with the power supply wiring layer 5. Due to the increase, a large error occurs between the calculated wiring capacitance and the actual wiring capacitance, which hinders the normal operation of the integrated circuit.

この発明の目的は、設計段階での計算上の配線容量と
実際の集積回路上での配線容量との間で誤差を生じさせ
ることのない配線容量算出装置を提供するにある。
An object of the present invention is to provide a wiring capacitance calculating apparatus which does not cause an error between a calculated wiring capacitance at a design stage and a wiring capacitance on an actual integrated circuit.

〔課題を解決するための手段〕[Means for solving the problem]

第1図は本発明の原理説明図である。すなわち、配線
容量算出装置は入力装置7、単位配線容量記憶装置8及
び配線容量演算装置6を備えている。入力装置7は、配
線層及び配線の位置座標データを入力するものである。
単位配線容量記憶装置8は、配線が他の配線層と重なら
ないで形成された場合の単位配線容量と、配線が他の配
線層と重なって形成された場合の単位配線容量とを予め
記憶したものである。配線容量演算装置6は、前記入力
装置7からのデータと前記配線容量記憶装置8からのデ
ータとに基づいて、配線を他の配線層と重ならない部分
と他の配線層と重なる部分とに分割すると共に、該配線
の他の配線層と重ならない部分の配線容量と該配線の他
の配線層と重なる部分の配線容量とを各々計算して総和
を算出するものである。
FIG. 1 is a diagram illustrating the principle of the present invention. That is, the wiring capacitance calculation device includes the input device 7, the unit wiring capacitance storage device 8, and the wiring capacitance calculation device 6. The input device 7 is for inputting position coordinate data of the wiring layer and the wiring.
The unit wiring capacitance storage device 8 previously stores a unit wiring capacitance when a wiring is formed without overlapping with another wiring layer and a unit wiring capacitance when the wiring is formed with overlapping another wiring layer. Things. The wiring capacitance calculating device 6 divides the wiring into a portion not overlapping with another wiring layer and a portion overlapping with another wiring layer based on the data from the input device 7 and the data from the wiring capacitance storage device 8. At the same time, the sum of the wiring capacitance of a portion not overlapping with another wiring layer of the wiring and the wiring capacitance of a portion overlapping with another wiring layer of the wiring is calculated.

〔作用〕[Action]

配線が他の配線層領域に重なって形成される場合には
その配線が他の配線層領域と重なる部分と重ならない部
分とに分割され、各分割部分は記憶装置8にあらかじめ
記憶された当該単位配線容量に基づいてそれぞれ配線容
量が算出され、各分割部分の配線容量が総計されて当該
配線の配線容量が算出される。
When the wiring is formed so as to overlap with another wiring layer area, the wiring is divided into a part overlapping with the other wiring layer area and a part not overlapping with each other, and each divided part is stored in the storage unit 8 in advance. The wiring capacitance is calculated based on the wiring capacitance, and the wiring capacitance of each divided portion is summed up to calculate the wiring capacitance of the wiring.

〔実施例〕〔Example〕

以下、この発明を具体化した一実施例を第2図〜第4
図に従って説明する。なお、前記実施例と同一構成部分
は同一番号を付してその説明を省略する。
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
Description will be made with reference to the drawings. Note that the same components as those of the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted.

第2図において本実施例の配線容量算出装置の基本的
構成を説明すると、コンピュータ6には入力装置7が接
続され、自動配線処理装置からその入力装置7を介して
種々の配線層あるいは多数の配線のX−Y座標上におけ
る位置データが入力される。コンピュータ6に接続され
たライブラリ8は電源配線層あるいはその他の配線層に
重なって配設される配線の単位長当たりの単位配線容量
が多数格納されている。また、同じくコンピュータ6に
接続されるメモリ9はコンピュータ6による演算結果を
一時格納するものである。
Referring to FIG. 2, an input device 7 is connected to a computer 6, and various wiring layers or a large number of wiring layers are connected to the computer 6 via the input device 7 in FIG. Position data on the XY coordinates of the wiring is input. The library 8 connected to the computer 6 stores a large number of unit wiring capacities per unit length of wiring that is provided so as to overlap the power supply wiring layer or another wiring layer. Further, a memory 9 similarly connected to the computer 6 temporarily stores a calculation result by the computer 6.

次に、このように構成された配線容量算出装置で自動
配線処理装置により作成された配線パターンの配線容量
を算出する場合を第3図及び第4図に従って説明する。
自動配線処理装置により第4図に示すような配線パター
ンが形成されてその配線パターンが入力装置7から入力
されると、コンピュータ6はその配線パターンをメモリ
9に格納し(STEP1、以下STEPはSとする)、ライブラ
リ8から各配線2,3,4の単位配線容量、すなわち各配線
2,3,4のX方向及びY方向の単位配線容量と、各配線2,
3,4が電源配線層5に重なった場合の単位配線容量とを
読み出してメモリ9に格納する(S2)。
Next, a case where the wiring capacity of the wiring pattern created by the automatic wiring processing apparatus is calculated by the wiring capacity calculating apparatus having the above configuration will be described with reference to FIGS. 3 and 4. FIG.
When the wiring pattern as shown in FIG. 4 is formed by the automatic wiring processing device and the wiring pattern is inputted from the input device 7, the computer 6 stores the wiring pattern in the memory 9 (STEP1, hereinafter referred to as S ), The unit wiring capacity of each wiring 2, 3, 4 from the library 8, ie, each wiring
2, 3, and 4 unit wiring capacitances in the X and Y directions, and each wiring 2,
The unit wiring capacity when 3 and 4 overlap with the power supply wiring layer 5 is read and stored in the memory 9 (S2).

次いで、コンピュータ6は電源配線層5と各配線2,3,
4のX−Y座標に基づいて第3図に示すように各配線2,
3,4と電源配線層5の境界との交点の座標データD1〜D4
を演算する(S3)。そして、その座標データD1〜D4で各
配線2,3,4を分割し、各分割部分の配線容量をその配線
長と当該の単位配線容量とに基づいて算出し、かつ各分
割部分の配線容量を総計して各配線2,3,4の配線容量を
算出する(S4)。
Next, the computer 6 connects the power supply wiring layer 5 to each of the wirings 2, 3,.
As shown in FIG. 3, each wiring 2,
Coordinate data D1 to D4 of intersections between 3, 4 and the boundary of power supply wiring layer 5
Is calculated (S3). Then, each of the wirings 2, 3, and 4 is divided by the coordinate data D1 to D4, the wiring capacity of each divided part is calculated based on the wiring length and the unit wiring capacity, and the wiring capacitance of each divided part is calculated. To calculate the wiring capacitance of each of the wirings 2, 3, and 4 (S4).

以上のようにこの配線容量算出装置では、各配線2,3,
4が電源配線層5に重なる部分と重ならない部分ではあ
らかじめ格納された単位配線容量に基づいてそれぞれ配
線容量が算出されるため、各配線2,3,4の配線容量の計
算値と、実際に製造した集積回路における各配線2,3,4
の配線容量との誤差の発生を防止することができる。従
って、各配線2,3,4の計算上の配線容量と実際の配線容
量との誤差による集積回路の動作不良を防止することが
できる。
As described above, in this wiring capacitance calculating apparatus, each of the wirings 2, 3, and
In the portion where 4 overlaps the power supply wiring layer 5 and in the portion where it does not overlap, the wiring capacitance is calculated based on the unit wiring capacitance stored in advance, so that the calculated values of the wiring capacitances of the wirings 2, 3, and 4 are actually calculated. Each wiring 2,3,4 in manufactured integrated circuit
The occurrence of an error with the wiring capacitance can be prevented. Therefore, it is possible to prevent an operation failure of the integrated circuit due to an error between the calculated wiring capacitance of each of the wirings 2, 3, and 4 and the actual wiring capacitance.

〔発明の効果〕〔The invention's effect〕

以上詳述したように、この発明は設計段階での計算上
の配線容量と実際の集積回路上での配線容量との誤差を
生じさせることのない配線容量算出装置を提供すること
ができる優れた効果を発揮する。
As described above in detail, the present invention provides an excellent wiring capacitance calculating apparatus that does not cause an error between the calculated wiring capacitance at the design stage and the actual wiring capacitance on an integrated circuit. It is effective.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の原理説明図、 第2図は本発明の一実施例の配線容量算出装置を示すブ
ロック図、 第3図は一実施例の配線容量算出手順を示す説明図、 第4図は一実施例の動作を示すフローチャート図、 第5図及び第6図は従来の配線容量算出装置による算出
手順を示す説明図である。 図中、 6は配線容量演算装置(コンピュータ)、7は入力装
置、8は単位配線容量記憶装置(ライブラリ)である。
FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a block diagram illustrating a wiring capacitance calculating apparatus according to one embodiment of the present invention, FIG. 3 is an explanatory diagram illustrating a wiring capacitance calculating procedure according to one embodiment, FIG. 5 is a flowchart showing the operation of one embodiment, and FIGS. 5 and 6 are explanatory diagrams showing a calculation procedure by a conventional wiring capacitance calculation device. In the figure, 6 is a wiring capacity calculation device (computer), 7 is an input device, and 8 is a unit wiring capacity storage device (library).

フロントページの続き (56)参考文献 特開 平1−128543(JP,A) 特開 平3−196548(JP,A) 特開 平2−287885(JP,A) 特開 昭63−69289(JP,A) 特開 昭64−32385(JP,A) 特開 昭61−144040(JP,A) 特開 平3−194659(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/82 G06F 17/50Continuation of the front page (56) References JP-A-1-128543 (JP, A) JP-A-3-196548 (JP, A) JP-A-2-287885 (JP, A) JP-A-63-69289 (JP) JP-A-64-32385 (JP, A) JP-A-61-144040 (JP, A) JP-A-3-194659 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB (Name) H01L 21/82 G06F 17/50

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】配線層及び配線の位置座標データを入力す
る入力装置(7)と、 配線が他の配線層と重ならないで形成された場合の単位
配線容量と配線が他の配線層と重なって形成された場合
の単位配線容量とを予め記憶した単位配線容量記憶装置
(8)と、 前記入力装置(7)からのデータと前記単位配線容量記
憶装置(8)からのデータとに基づいて、配線を他の配
線層と重ならない部分と他の配線層と重なる部分とに分
割すると共に、該配線の他の配線層と重ならない部分の
配線容量と該配線の他の配線層と重なる部分の配線容量
とを各々計算して総和を算出する配線容量演算装置
(6)と、 を有することを特徴とする配線容量算出装置。
An input device for inputting position coordinate data of a wiring layer and a wiring; a unit wiring capacitance and a wiring when the wiring is formed so as not to overlap with another wiring layer; A unit wiring capacitance storage device (8) storing beforehand a unit wiring capacitance when formed, and data based on data from the input device (7) and data from the unit wiring capacitance storage device (8). The wiring is divided into a portion not overlapping with another wiring layer and a portion overlapping with another wiring layer, and a wiring capacitance of a portion not overlapping with another wiring layer of the wiring and a portion overlapping with another wiring layer of the wiring And a wiring capacitance calculating device for calculating the sum of the wiring capacitances.
JP2001928A 1990-01-09 1990-01-09 Wiring capacity calculator Expired - Lifetime JP2857439B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001928A JP2857439B2 (en) 1990-01-09 1990-01-09 Wiring capacity calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001928A JP2857439B2 (en) 1990-01-09 1990-01-09 Wiring capacity calculator

Publications (2)

Publication Number Publication Date
JPH03206646A JPH03206646A (en) 1991-09-10
JP2857439B2 true JP2857439B2 (en) 1999-02-17

Family

ID=11515270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001928A Expired - Lifetime JP2857439B2 (en) 1990-01-09 1990-01-09 Wiring capacity calculator

Country Status (1)

Country Link
JP (1) JP2857439B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315450A (en) * 1992-05-12 1993-11-26 Nec Corp Lsi layout device
JP5345098B2 (en) * 2010-04-05 2013-11-20 日本アビオニクス株式会社 Projector with increased resistance to electrostatic noise

Also Published As

Publication number Publication date
JPH03206646A (en) 1991-09-10

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