JP2903908B2 - Bipolar ELC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.
And a bipolar ECL circuit .

[0002]

2. Description of the Related Art Semiconductor integrated circuits are required to have low power consumption due to high integration. On the other hand, as the size of a chip increases, the length of wiring connected to a gate increases, and the load due to wiring capacitance and resistance tends to increase. It is in.

On the other hand, in recent ECL circuits, a system has been considered in which the emitter follower section is an active pull-down circuit as shown in FIG. 4 in order to obtain a sufficient driving capability. In this circuit, the output OU
When T falls from the high level to the low level, the falling waveform of the collector output CB of the current changeover switch is charged to the base of the current control transistor QDR1 of the emitter follower through the differentiating circuit including the capacitor C _X and the resistor R _X. As a result, the emitter-follower current is increased by the transition time of the fall of the output OUT, and a current sufficient to discharge the charged electric charge to the load at the time of the fall of the output OUT is supplied. Realize.

A bias terminal V _CP is connected to a control transistor Q
This is for biasing DR1 and is biased so that a small current flows through the transistor QDR1 when the output out is stable. More constant τ = C _X R _X when differentiating circuit comprised of capacitor C _X and resistance R _X as an increase of the emitter follower current shown in FIG. 5 (a) at the time of the fall of the output out is large, the transistor Since the amount of charge for charging the base of the QDR1 is large and the time is long, the amount of increase in the emitter follower current is large and the fall of the output out is fast, and conversely, when the time constant τ = C _X R _X becomes small, the emitter follower current becomes small. Is small, and the fall time of the output out becomes long. QS1, QR1, QCS and QEF are transistors, and R1 and R2 are resistors.

[0005]

[Problems that the Invention is to Solve In the emitter-follower circuit of a conventional active pull-down scheme, variations in the bias terminal VCP capacity C _x and resistor R _x, no correction function for variations, for example, small capacitance C _x What
Time, the time constant C _x R _x becomes small and the output
The fall time of out becomes longer (see FIG. 5D).
), The disadvantage of increasing the propagation delay of the ECL gate
was there.

An object of the present invention is to provide a semiconductor integrated circuit in which the variation in fall time of an ECL gate is reduced.

[0007]

In order to achieve the above-mentioned object, a bipolar ECL circuit according to the present invention is incorporated in a base.
A first transistor to which a force signal is applied and the first transistor;
Second transistor forming a differential pair with a transistor
And a first power supply terminal at the collector and an output terminal at the emitter
However, the differential output of the second transistor is connected to the base.
A first emitter follower transistor,
A first capacitor connected to a differential output on the first transistor side
A differentiating circuit comprising a series circuit of a quantity and a first resistor;
Connected between the power terminal and the second power supply terminal,
Active pulldown where the output of the circuit is connected to the base
Transistor and the active pull-down transistor.
A bias terminal connected to the base of the transistor.
The clock is input to the base in the bipolar ECL circuit
A second emitter follower transistor and the second
The emitter of the emitter follower transistor and the second
The first capacitor connected between the power supply terminal and the first capacitor;
A second capacitance and a second capacitance substantially equal to
A time constant monitor circuit comprising a parallel circuit of
Time constant for comparing the output of the time constant monitor circuit with the reference potential
Number detection circuit, and a first resistor connected to the base via a third resistor.
The power supply terminal is connected, and the bias terminal is connected to the emitter.
Consisting of a third emitter follower transistor connected
The bias circuit is detected by the time constant detection circuit.
Given by the product of the first capacitance and the first resistance
As the time constant is smaller, the third emitter of the bias circuit is smaller.
The current drawn from the base of the
And a bias control circuit for reducing the bias . Further, the bias control circuit includes an output of the time constant detection circuit.
Is connected to the base, and the third transistor
Fourth transistor forming a differential pair with a transistor
And the collector of the fourth transistor is
The third emitter follower transistor of the ias circuit;
Is connected to the base.

[0008]

[Function] The time constant due to the capacitance and resistance used in the active pull-down circuit is monitored by the time constant monitor circuit .
The output potential of the bias circuit is adjusted based on the information detected by the time constant monitor circuit .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In FIG. 1, the active pull-down circuit has an ECL gate, and this configuration is the same as that of the conventional one.

The present invention relates to a current control transistor QDR
It has a bias circuit 6 connected to one base and a bias adjustment circuit.

Time constant monitor circuit 1 for bias adjustment circuit
Is a form of capacitance C _y to the emitter follower is connected as a load, capacitance C _y are those capacitance C _X of the active pull-down circuit combines one or a plurality. The resistor _Ry is a single or a combination of the resistors _Rx . There is no relative error or variation between the capacitors _Cx and _{Cy and} between the resistors _Rx and _Ry .

A clock signal CLK is externally inputted to the time constant monitor circuit 1 by the frequency dividing circuit 2 after sufficiently dividing the frequency of the actual clock cycle. At this time, the waveform of the time constant monitor output CKY at the rising time as shown in FIG.
Strongly driven but rises rapidly, during the time of falling of the charge charged in the capacitor C _y is through a resistor R _y constant C _y R _y by
, The falling waveform becomes gentle.

At the design stage, the clock time divider, the capacitance _Cy and the resistance _Ry are adjusted so that the voltage change in the falling waveform can be easily detected by the time constant detection circuit 3 at the next stage.

At the gate U11 of the time constant detecting circuit 3, the voltage level of the time constant monitor output is set to the reference level CM.
As compared with P1, the output signal of 1.0 is output to the output OT1 depending on the level. Gates U12 and U1 of detection circuit 3
3 as well as the gate U11, the reference levels CMP2 and CM
By performing detection by changing the detection level to P3, it is possible to know from the output information of the blocks U11 to U13 how far the voltage level of the time constant monitor output has fallen, thereby estimating the time constant.

The information of the outputs OT1 to OT3 of the time constant detection circuit 3 is stored in a register 4 and becomes a gate input in a bias control circuit 5 in the next stage to adjust the bias level of the bias circuit 6.

For example, as shown in FIG. 2B, if the output waveform of the time constant monitor circuit is such that the capacitance _Cy is large, only the gate U11 outputs a high level (0) in the time constant detection circuit 3 and the gate U12 , U13 go to low level (1),
If the capacitance C _y varies small, the time constant C _y R _y is small, and the output of the time constant monitor circuit 1 falls in a short time and falls below the reference level CMP2.
Of the gates U11 and U12 output a high level (0) and the gate U13 outputs a low level (1), and these are stored in the register 4 and input to the gate of the bias control circuit 5.

When the capacitance _Cy is large, the transistor Q
1, Q2 and Q3 each have a gate U of the detection circuit 3
The detection information at 11, U12, and U13 is input, the transistor Q1 is turned on, the transistors Q2 and Q3 are turned off, and the current I _B = j ₂ + j ₃ drawn into the bias adjustment from the bias circuit 6 corresponds to the capacitance C _y There when small is conducting transistor Q1, Q2 is, I _B = j _3, and when a small capacity C _y, the voltage drop at the resistor R _B in the bias circuit 6 is small, the bias voltage V _CP is Get higher.

The operation of the active pull-down circuit in this state, as shown in FIG. 3, because the bias voltage V _CP has risen, the emitter follower current in a stable state increases as shown in FIG. When the collector terminal CB of the current switch QS1 rises, an increment of the differential wave shape via the capacitor CX is superimposed, so that the amount of charge for charging the base of the emitter-follower current control transistor QDR1 is changed to the capacitance C
It becomes possible to do the same as when _X is large, and output out
In the falling waveform of, the variation of the delay time due to the variation of the capacitance C _X and the resistance R _X of the active pull-down circuit can be reduced.

[0020]

The present invention described above, according to the present invention means a constant monitoring circuit is provided when monitoring the time constant is the product of the resistance and capacitance used in active pull-down circuit, when the
It is intended to adjust the output voltage of the bias circuit on the basis of the information detected by constant monitoring circuit, active pull
Time constant given by product of capacitance and resistance used in down circuit
Even if the number fluctuates in the decreasing direction, the
ECL gate without falling time
This can prevent the propagation delay from becoming worse.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an ECL gate and a bias adjustment circuit according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an operation of the bias adjustment circuit shown in FIG.

FIG. 3 is an explanatory diagram showing an operation of the ECL gate shown in FIG.

FIG. 4 is a conventional ECL gate circuit diagram.

FIG. 5 is an explanatory diagram showing the operation of the ECL gate shown in FIG.

[Explanation of symbols]

1 time constant monitor circuit 2 frequency divider 3 time constant detector 4 register 5 bias control circuit 6 bias circuit QS1, QR1, QDR1, QO11, Q1, Q2, Q
3, QCS, QEF transistor _{R1, R2, R B, R} x, R y resistance C _x, C _y capacitor U11, U12, U13 gates F1, F2, F3 flipflop V _CS constant voltage source terminal V _CP bias terminal

Claims (2)

(57) [Claims] A first transistor to which an input signal is applied to a base.
A differential pair is formed with the transistor and the first transistor.
A second transistor to be formed, and a first power supply terminal connected to the collector.
The second transistor has an output terminal connected to the emitter,
The first emitter for which the differential output on the side is connected to the base
A lower transistor and a differential on the first transistor side.
Whether a series circuit of a first capacitor and a first resistor connected to the output
A differentiating circuit comprising the output terminal and the second power supply terminal.
And the output of the differentiating circuit is connected to the base.
Active pull-down transistor and
Connected to the base of active pull-down transistor
A bipolar ECL circuit having a bias terminal
And a second emitter follower in which the clock is input to the base.
Transistor and second emitter follower transistor
Connected between the second power supply terminal and the emitter of
The first capacitance and the first resistance are substantially equal to each other.
When a new second capacitor and a second resistor are connected in parallel
A constant monitor circuit, and the output and base of the time constant monitor circuit.
A time constant detection circuit for comparing with a quasi-potential, and a third
The first power supply terminal is connected via a resistor, and the
A third emitter follower to which the bias terminal is connected
A bias circuit comprising a transistor and
The first capacitance detected by the output circuit and the first capacitance
The smaller the time constant given by the product of the resistance and the
Of the third emitter follower transistor of the
Bias control circuit to reduce current drawn from source
And a bipolar ECL circuit. 2. The method according to claim 1, wherein the bias control circuit detects the time constant.
A third transistor whose output is connected to the base of the output circuit
And a fourth transistor forming a differential pair with the third transistor.
And a transistor of the fourth transistor.
A third emitter follower of the bias circuit.
A transistor connected to the base of a transistor
The bipolar ECL circuit according to claim 1.