JP2907189B2 - Automatic layout device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout apparatus for designing a layout of a semiconductor chip, and more particularly to a layout design of a bonding pad.

[0002]

2. Description of the Related Art FIG. 4 shows a peripheral structure of a semiconductor chip provided inside an IC package.

A chip 10 mounted on an island 9
Is provided with a plurality of bonding pads 11 for connecting a bonding wire 12, and is provided on a circuit and a package formed in the chip 10 by connecting the inner lead 13 and the bonding pad 11 with the bonding wire 12. Is connected to the terminal.

An automatic layout device is used to design the layout of the chip 10.

Conventionally, this type of automatic layout apparatus has been disclosed in, for example, Japanese Patent Laid-Open No. 2-140967.
The layout of the chip has been designed based on the assembly diagram and the circuit diagram of the IC.

FIG. 5 is a diagram showing a flow of a conventional automatic layout apparatus.

The assembling design standard 1 includes a distance between the island 9 and the chip 10, a distance between the bonding pad 11 and the inner lead 13, a distance between the bonding wires 12 connecting the bonding pad 11 and the inner lead 13,
This is a criterion for restricting the assembling of the chip 10, such as the bonding portion 16 between the bonding wire 12 and the inner lead 13.

Here, the limitation on the size of the extracted chip 10 means the maximum chip size and the minimum chip size that can be mounted.

FIG. 19 is a diagram showing the shape of the island 9 and the shape of the inner lead 13.

The restrictions 20 on pad coordinates and chip size are as follows:
These are restrictions on the arrangement position of the bonding pads 11 and restrictions on the size of the chip 10 that can be mounted on the island 9, which are extracted from the assembly design standard 1 and the package assembly drawing 19.

FIG. 3 shows circuit diagram information of the chip 10.

The layout design criterion 5 is a criterion for imposing restrictions when designing the layout of the chip 10.

The automatic layout tool 27 includes a limit 20 for pad coordinates and chip size and a layout design standard 5.
Is a tool for performing a layout design that satisfies the following conditions based on the IC circuit diagram 3.

A chip layout 8 is a layout result of a chip produced by the automatic layout tool 27.

Next, the operation of the conventional automatic layout device will be described. When the package on which the chip 10 is mounted is determined, a restriction on the arrangement position of the bonding pad 11 is required from the assembly design standard 1 and the package assembly drawing 19. Also, the assembly design standard 1 and the package assembly drawing 19
Therefore, the size of the chip 10 that can be mounted on the package is required, and the limitation of the chip size is determined. Then, using the automatic layout tool 27, the pad coordinates and
A layout design that satisfies the chip size limit 20 and the layout design standard 5 is performed based on the IC circuit diagram 3. Finally, a chip layout 8 that satisfies the pad coordinate / chip size limit 20 and the layout design standard 5 is created.

In the conventional automatic layout apparatus described above,
Each time the package is changed, the pad coordinates and the chip size limit must be determined from the assembly design standards and the package assembly drawing.Therefore, it takes time to determine the pad coordinates, which are the positions of the bonding pads. there were.

An object of the present invention is to provide an automatic layout apparatus capable of shortening a period until pad coordinates are determined.

[0018]

In order to achieve the above object, an automatic layout apparatus according to the present invention provides an automatic layout apparatus for designing a layout of a semiconductor chip according to the structure of a package to be mounted. Is input, a plurality of bondings for connecting bonding wires are obtained from a package database in which information on the structure of the package is stored for each package and an assembly design standard which is a design standard for the package. It is characterized in that the coordinates of the pads and the arrangement range of each of the bonding pads are extracted, and the change range of the coordinates of the bonding pads is limited to the specified arrangement range.

According to the present invention, when a package on which a semiconductor chip is mounted is determined at the time of layout design of a semiconductor chip, information on the structure of the package stored in a package database and a design standard for the package are provided. The coordinates at which the bonding pads can be arranged are extracted from the assembling reference, and the coordinates of the bonding pads are restricted so as not to be changed outside the possible arrangement range.

Therefore, even when the package on which the semiconductor chip is mounted is changed, information on the structure of the package is stored for each package in the package database, so that the arrangement corresponding to the new package can be performed simply by inputting the package name. The layout design of the bonding pad can be performed by extracting the range, and the period of the layout design can be shortened.

Further, according to the automatic layout apparatus of the present invention, in the automatic layout apparatus for designing the layout of a semiconductor chip in accordance with the structure of the package to be mounted, when the information of the package on which the semiconductor chip is mounted is inputted, The coordinates of a plurality of bonding pads for connecting bonding wires and mounting on the package are determined from a package database in which information regarding each package is stored and an assembly design standard which is a design standard in the package. The maximum and minimum chip sizes that can be extracted are extracted, and the layout design of the semiconductor chip is limited to only within the extracted chip size.

According to the present invention, when a package on which a semiconductor chip is mounted is determined at the time of layout design of a semiconductor chip, information on the structure of the package stored in a package database and a design standard for the package are provided. The maximum and minimum chip sizes that can be mounted on the package are extracted from the assembly standard, and the layout design of the semiconductor chip is limited only to the chip size.

Therefore, even when the package on which the semiconductor chip is mounted is changed, information on the structure of the package is stored in the package database for each package. Therefore, only by inputting the name of the package, the maximum chip corresponding to the new package can be obtained. The size can be extracted, and the period of layout design can be shortened.

[0024]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
It is a figure showing the flow of the automatic layout device of the embodiment. The package database 2 having the same reference numerals as in FIG. 5 indicates the same components, and is a database containing information on assembly for all available packages.

Pad coordinate / chip size extraction tool 6
Is a tool for extracting, based on the assembly design standard 1 and the package database 2, the coordinates of the bonding pad 11 with respect to the package on which the chip 10 is mounted, the range in which the bonding pad 11 can be arranged, and the size of the mountable chip 10.

Here, the limitation on the size of the extracted chip 10 means the maximum chip size and the minimum chip size that can be mounted.

Next, a method for obtaining the range in which the bonding pads can be arranged will be described with reference to FIG. Here, the bondable range 15 is a range where the bonding wire 12 can be bonded, calculated from the assembly design standard 1. The pad arrangement possible range 14 is an arrangement possible range of the bonding pad corresponding to the bonding possible range 15. The pad arrangement possible range 14 is the inner lead 13
Is calculated from the bondable range 15 of the above, and satisfies the assembly design standard 1.

In the automatic layout tool 7, the bonding pad 11 can be arranged at an arbitrary position in the pad arrangement possible range 14. As a result of the arrangement of the internal cells such as the input / output buffer, a problem occurs in the pad coordinates. Even in such a case, the arrangement position can be easily corrected.

The package name 4 is the name of the package on which the chip 10 is mounted.

The automatic layout tool 7 calculates pad coordinates and
This is a tool for performing layout design based on the IC circuit diagram so as to satisfy the pad coordinates and chip size extracted by the chip size extraction tool 6 and the layout design standard 5.

The chip layout 8 is a layout of a chip created by the automatic layout tool 7.

Next, the operation of this embodiment will be described with reference to FIG.

When the package name 4 which is the name of the package on which the chip 10 is mounted and the layout design standard 5 are input to the automatic layout tool 7, the automatic layout tool 7 converts the package name 4 and the layout design standard 5 into the pad coordinates The information is transmitted to the chip size extracting tool 6. Then, the pad coordinate / chip size extraction tool 6 calculates pad coordinates, an arrangement possible range thereof, and a designable chip size with reference to the assembly design standard 1 and the package database 2. Then, the information calculated by the pad coordinate / chip size extraction tool 6 is taken into the automatic layout tool 7 again. Then, the designer determines the final position of the pad in the arrangable range of the acquired pad coordinates and the optimum chip size within the range of the chip size that can be designed, and lays out the pad layout on the automatic layout tool 7. Then, the chip layout 8 is output.

(Second Embodiment) Next, a second embodiment of the present invention will be described.

In the first embodiment, the chip is mounted on one package, but in this embodiment, one type of chip is mounted on two types of packages A and B. is there.

This embodiment has the same configuration as that of the first embodiment shown in FIG. 1 and differs only in the method of calculating the possible pad arrangement range.

A method of calculating the possible pad arrangement range according to the present embodiment will be described with reference to FIG.

Here, the pad arrangement possible range 17 for the package A is a range of coordinates where the bonding pads 11 can be arranged for the package A, and the pad arrangement possible range 18 for the package B is
This is a range of coordinates where the bonding pads 11 can be arranged for the package B.

Next, the operation of this embodiment will be described with reference to FIGS. When one type of chip is mounted on several types of packages, all of the packages must satisfy Assembly Design Standard 1. First, the pad arrangement possible range 17 for the package A is extracted by the pad coordinate / chip size extraction tool 6 from the assembly design standard 1 corresponding to the package A. Similarly, package B
Is extracted by the pad coordinate / chip size extraction tool 6 from the assembly design criterion 1 corresponding to. The overlapping portion of the two arrangement possible ranges is the arrangement possible range 14 of the bonding pad. The bonding pad 11
Lays out both the packages A and B, which satisfies the assembly design standard 1 for the lead frame, so that one type of chip 10 can be mounted on two types of packages A and B. Become. Here, the case where one type of chip is mounted on two types of packages has been described. However, the number of packages is not limited to two types, and the present invention is also applicable to the case where one type of chip is mounted on three or more types of packages. can do.

[0041]

As described above, according to the present invention, since the package database is searched and the pad coordinates and the chip size satisfying the assembly design standard can be limited,
A layout design satisfying the assembly design standard can be performed on the automatic layout tool, and the layout design period can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of an automatic layout device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of calculating a possible pad arrangement range in the automatic layout apparatus of FIG. 1;

FIG. 3 is a diagram illustrating a method of calculating a pad arrangement possible range in an automatic layout device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a peripheral structure of a chip in an IC package.

FIG. 5 is a diagram showing a flow of a conventional automatic layout device.

[Explanation of symbols]

 1 Assembly Design Standard 2 Package Database 3 IC Circuit Diagram 4 Package Name 5 Layout Design Standard 6 Pad Coordinate / Chip Size Extraction Tool 7 Automatic Layout Tool 8 Chip Layout 9 Island 10 Chip 11 Bonding Pad 12 Bonding Wire 13 Inner Lead 14 Pad Arrangement Possible Range 15 Bondable range 16 Adhesive part 17 Pad layout possible range for package A 18 Pad layout possible range for package B 19 Package assembly drawing 20 Restriction of pad coordinates and chip size 27 Automatic layout tool

Claims (2)

(57) [Claims] In an automatic layout apparatus for designing a layout of a semiconductor chip in accordance with a structure of a package to be mounted, when information on a package on which a semiconductor chip is mounted is input, information on the structure of the package is stored for each package. Extracting the coordinates of a plurality of bonding pads for connecting bonding wires and the disposable range of each bonding pad from the package database and the assembly design standard that is a design standard in the package; An automatic layout device, wherein a change range of the coordinates of a pad is limited to the specified arrangement possible range. 2. An automatic layout apparatus for designing a layout of a semiconductor chip in accordance with a structure of a package to be mounted, wherein information on a package on which a semiconductor chip is mounted is input and information on the structure of the package is stored for each package. The coordinates of a plurality of bonding pads for connecting bonding wires, and the maximum and minimum chip sizes that can be mounted on the package, based on the package database and the assembly design standard that is a design standard for the package. Wherein the layout design of the semiconductor chip is limited to only within the extracted chip size.