JP2911038B2 - Multi-value drive circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilevel drive circuit that can be used, for example, in an IC test apparatus.

"Prior art" Some ICs require a third voltage _VTT to be applied as shown in FIG. 4, for example, in addition to H logic and L logic.

Conventionally, a multi-value drive circuit as shown in FIG. 5 is used to provide such a ternary waveform to the IC under test.

This conventional multi-valued driving circuit comprises two pairs of transistors Q ₁ , Q ₂ and Q ₃ , Q ₄ connected so as to perform differential ON / OFF operation, one resistor R, Constant current circuits 1 and 2 for controlling the currents flowing through the transistors Q ₁ and Q ₂ and Q ₃ and Q ₄ to the values of I ₁ and I ₂ , and a constant bias voltage V _B at the bases of the transistors Q ₂ and Q _4. And a bias voltage source 3.

The base of the transistor Q _1, Q ₃ are providing a control signal V _in1 and V _in2 from the input terminal 4 and 5.

Control signal V _in1, V _in2 to the relationship between the bias voltage V _B is V _in1
> V _B , V _in2 > V _B , the transistors Q ₂ and Q ₄ are both turned off, and no current flows through the resistor R;
Voltage V ₀ which power is output to.

Control signal V _in1, V _in2 to the relationship between the bias voltage V _B is V _in1
<V _B, V _in2> When the V _B transistor Q ₂ is turned on, the transistor Q ₄ is turned off. In this case the voltage drop RI ₁ occurs in the resistor R current I ₁ of the constant current circuit 1 flows through the resistor R. Therefore, the voltage of the output terminal 6 at this time is V ₁ = V ₀ −RI
It becomes ₁ .

Control signal V _in1, V _in2 to the relationship between the bias voltage V _B is V _in1
> V _B, if a V _in2 <V _B is the transistor Q ₂ is turned off, the transistor Q ₄ is turned on. At this time, current I ₂ of the constant current circuit 2 flows through the resistor R, the voltage drop RI ₂ is generated in the resistor R. Therefore, at this time, the voltage of the output terminal 6 is V ₂ =
V ₀ −RI ₂ . When a constant current I ₁ and I ₂ are assumed to be set in relation I ₁ <I _2, the multi-level signal having three values as shown in FIG. 6 is outputted by the logic of the control signal V _in1 and V _in2 The multi-level signal is supplied to, for example, an IC under test.

[Problems to be Solved by the Invention] The conventional multi-value drive circuit shown in FIG. 5 generates a waveform by using the voltage drop of the resistor R, and therefore consumes a large amount of current and is inefficient.

When the resistance value of the resistor R is increased to obtain a large amplitude, the stray capacitance formed between the output terminal 6 and the common potential and the time constant formed by the resistor R increase, and There is a disadvantage that the rise time of the waveform is delayed.

An object of the present invention is to provide a multi-value drive circuit that can eliminate these disadvantages.

According to the present invention, a plurality of switch circuits constituted by diode bridges are connected to respective anode common contacts and cathode common connection points of the plurality of switch circuits, and are simultaneously turned on and off by a drive signal,
A plurality of switch control circuits that separately control the switch circuits in a conductive state in an on state, and are connected to one of the other connection points other than the anode common connection point and the cathode common connection point of the switch circuit to apply different voltages to each other. A plurality of voltage sources to be generated, an output terminal derived by commonly connecting the other of the connection points other than the anode common connection point and the cathode common connection point of the switch circuit, and a voltage applied to the anode common connection point of the switch circuit. A first clamp circuit for providing a voltage equal to or lower than the lowest voltage generated by the source;
And a second clamp circuit for applying a voltage equal to or higher than the highest voltage generated by the voltage source to the common cathode connection point of the switch circuit.

As described above, according to the present invention, a plurality of DC voltage sources that output mutually different voltages are prepared, and the voltages of the plurality of voltage sources are selectively extracted by the switch circuit to generate a multi-valued waveform. As a result, it is more efficient than a method of generating a multi-level signal by generating a voltage drop in a resistor.

Moreover, the rising and falling of the waveform are not delayed by the time constant because of the structure in which the generated voltage is taken out by the switch. Therefore, it is possible to obtain a multi-level waveform in which the rise and fall sharply change.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 10, 11, and 12 shows a voltage source for outputting a DC voltage V _1, V _2, V _3, which is set in advance. This example shows a case where three voltage sources are provided to generate a ternary multi-valued waveform.

Voltages V ₁ of the voltage source 10,11,12, V _2, V ₃ and the switch circuit
13, 14, 15 selectively output to the output terminal 6 to generate a multi-valued waveform. This example shows a case where a switch circuit is configured by a diode bridge circuit.

These switch circuits 13, 14, and 15 are generally clamp circuits 16
And controlled off by 24. The clamp circuit 16 applies the potentials at the points B, F, and J of the switch circuits 13, 14, and 15 to the voltage sources 10, 11, and 1.
An operation of clamping to a voltage lower than any of the voltages V ₁ , V ₂ , and V ₃ is performed. For this purpose, the voltages V ₁ ,
A voltage source 17 for generating a V _2, V ₃ lower than the voltage _{V 4 (V 4 <V 1} , V 2, V 3), to connect the voltage source 17 and the switch circuits 13, 14, 15 to each other insulating Constant current circuit that draws current I through diodes 18, 19, and 20, and insulated diodes 18, 19, and 20
21, 22, and 23.

Therefore, when the transistors constituting the upper switch control circuit 41 are not controlled to be turned on, each of the switch circuits 13, 1
The points B, F, and J at ₄ , 15 are clamped to the voltage V4 of the voltage source 17.

On the other hand, C points lower switch circuits 13, 14, 15, G, K is the voltage V _1, V _2, V ₃ is greater than the throat of the voltage the voltage V ₅ of the voltage source 10, 11, 12 by the clamp circuit 24 Is clamped to. That the voltage V ₅ is set to satisfy the relationship of _{V 5> V 1, V 2} , V 3, constant current circuit
By sucking the current through the insulating diodes 29, 30, 31 from the 26, 27, 28 to clamp C, G, the potential of each point K to the voltage V _5.

Thus, the clamp voltages V ₄ and V ₅ of the clamp circuits 16 and 24 are
Are set to V ₄ <V ₅ , the switch circuits 13, 14, and 15 configured by the diode bridges are controlled to be in the off state.

Here, assuming that the transistors 41A and 42A constituting the upper switch control circuit 41 and the lower switch control circuit 42 are turned on, the constant current circuit 4
The current of 3 to 21 flows into the switch circuit 13.

The lower transistor 42A is connected to the lower transistor 42A by the constant current circuit 44.
Current is drawn.

As a result, half of the current I flowing from the upper transistor 41A flows into the constant current circuit 21, and the other half of the current I passes through the switch circuit 13 and the lower transistor 42A
Flow into The current of I further flows into the lower transistor 42A from the constant current circuit 26, and the current of 21 flows in total.

As described above, the currents of the constant current circuits 21 and 26 do not flow into the clamp voltage sources 17 and 25, but switch to a state of flowing through the transistors 41A and 42A, and the current I flows through the switch circuit 13. Therefore, at this time, all the diodes constituting the switch circuit 13 are turned on, and the voltage of the voltage source 10 is taken out to the output terminal 6.

In this way, the upper switch control circuit 41 and the transistors 41A and 42A and 41B and 4B of the lower switch control circuit 42
By turning on one of the sets 2B, 41C and 42C, one of the switch circuits 13, 14, 15 is turned on. At this time, the voltage source connected to the switch circuits 13, 14, 15 is turned on. One of the voltages V ₁ , V ₂ , and V ₃ of 10, 11, and 12 is selected by the output terminal 6 and output. The output voltage is supplied to, for example, an IC under test (not shown) through a buffer amplifier 45 as necessary.

50A, 50B and 50C denote drive circuits for controlling the transistors 41A to 41C and 42A to 42C of the switch control circuits 41 and 42, respectively.

50A is the transistors 41A and 42A of the switch control circuits 41 and 42
A drive circuit for driving the transistors 41B and 42B of the switch control circuits 41 and 42 on and off; and 50C a transistor for the switch control circuits 41 and 42.
The drive circuits for driving the 41C and 42C on and off, respectively, are shown.

Each of these drive circuits 50A, 50B, 50C is composed of two pairs of transistors A, B, C, D that are differentially connected.
Transistors A and B use NPN transistors, and transistors C and D use PNP transistors.

These two pairs of differentially connected transistors A, B and C, D
Connect the bases of transistors A and C and B and D in common, and connect the bases of transistors A and C in common to input terminals 51 and
Connect to 52,53.

The bases of the transistors B and D are all connected in common, and a bias voltage _VBB is applied to this common connection point.

Thus transistors A and D is inverted to the ON state to the input terminal 51, 52, and 53 by constructing by providing a positive pulse with greater than a bias voltage V _BB, turns on the transistor of the switch control circuit 41 and 42 Can be driven.

This is shown in FIG. A switch control circuit 41 in the section of the rectangular wave VP ₁ is given (Fig. 2 A) to the input terminal 51
42 transistors 41A and 42A are turned on and the voltage source 10
And it outputs the voltages V ₁ to the output terminal 6.

To an input terminal 52 rectangular wave VP ₂ is given intervals (Fig. 2 B), the transistor 41B of the switch control circuit 41 and 42, 42
B is turned on, and as shown in FIG.
And it outputs the voltage V ₂ to the output terminal 6.

Section rectangular wave VP ₃ is applied to the input terminal 53 (FIG. 2 C) In a transistor 41C of the switch control circuit 41 and 42 4
2C is turned on, and the voltage of the voltage source 12 as shown in FIG.
And it outputs the V ₃ to the output terminal 6.

Thus, the rectangular wave V given to the input terminals 51, 52, 53
Voltages V _{1 to} V ₃ having values corresponding to the inputs of P ₁ , VP ₂ , and VP ₃ are selected and output to the output terminal 6 to generate a multi-valued voltage signal having an arbitrary waveform.

FIG. 3 shows a modified embodiment of the present invention. In this example, the clamp voltage sources 17 and 25 described in FIG. 1 are omitted, and the voltages of the voltage sources 10, 11, and 12 are replaced with diodes D _A , D _B , and D _C.
Through the diodes 18,1 constituting the clamp circuits 16 and 24
Give to 9,20 and 29,30,31, and select the highest voltage H (Fig. 4) and the lowest voltage L (Fig. 4) among the voltage sources 10, 11, 12 and use them automatically as clamp voltage An example is shown below. The drawing omits the drive circuit.

In the embodiment shown in FIG. 1, a case where a ternary signal is output has been described. However, the present invention is not limited to the ternary signal, but may be configured to generate more multi-level signals.

[Effects of the Invention] As described above, according to the present invention, each of the voltage sources 10, 1
The voltages V ₁ , V ₂ , V ₃ of 1,12 are turned on by the switch circuits 13,14,15,
The configuration is such that the voltage is taken out to the output terminal 6 by the OFF operation, and the multi-valued voltage is not generated by the voltage drop of the resistor, so that the current consumption can be reduced.

Further, since a multi-level signal is not generated by utilizing the voltage drop of the resistor, even if a stray capacitance exists at the output terminal 6,
No time constant circuit is formed.

As a result, it is possible to obtain a multilevel signal having a fast rising and falling speed.

Further, since the voltages are separately output from the voltage sources, the change of the voltage setting of one voltage source does not affect the other. Therefore, the voltage can be set independently. Further, the dynamic characteristics in the transition state between voltages are not affected.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation thereof, FIG. 3 is a connection diagram showing a modified embodiment of the present invention, and FIG. FIG. 5 is a waveform diagram for explaining the operation of FIG. 5, FIG. 5 is a waveform diagram for explaining the conventional technique, and FIG. 6 is a waveform diagram for explaining the operation of FIG. 6: output terminal, 10, 11, 12: voltage source, 13, 14, 15: switch circuit, 16, 24: clamp circuit, 41, 42: switch control circuit, 50
A, 50B, 50C: drive circuit, 51, 52, 53: input terminals.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 G01R 31/26-31/27

Claims (2)

(57) [Claims] A. A plurality of switch circuits each constituted by a diode bridge; and B. A plurality of switch circuits connected to respective anode common connection points and cathode common connection points, and are simultaneously turned on and off by a drive signal. A plurality of switch control circuits that are controlled and control the switch circuits separately in a conductive state in an on state; and C. one of the other common connection points other than the anode common connection point and the cathode common connection point of the switch circuit. A plurality of voltage sources connected to each other and generating different voltages, D. an output terminal derived by connecting the other of the other connection points other than the anode common connection point and the cathode common connection point of the switch circuit, and E. A first clamp for applying a voltage equal to or lower than the lowest voltage generated by the voltage source to the common node of the switch circuit. And a second clamp circuit for applying a voltage equal to or higher than the highest voltage generated by the voltage source to the common cathode connection point of the switch circuit. Value drive circuit. 2. The multi-level drive circuit according to claim 1, wherein a buffer amplifier is connected to said output terminal, and said multi-level signal is taken out through said buffer amplifier.