JP2915944B2 - Coverage measurement method and microcomputer - Google Patents

Description

The present invention relates to a technique for software debugging of a microcomputer application system, a method for measuring the coverage of instructions executed by a microcomputer, and an implementation of the method. It relates to a microcomputer used.

[Conventional technology]

In the development of microcomputer application equipment, an in-circuit emulator is used to debug the application system and to evaluate the system in detail. Such an in-circuit emulator is connected between a system development device such as a parent computer (host computer) for software development and an application device under development, and includes a microprocessor (target microprocessor) included in the application device. It acts as a debugger while acting on behalf of the function, and supports detailed system debugging.

An example of a document describing the in-circuit emulator is "Hitachi Maiko Technical Report (Vol. 2, No. 2)" issued by Hitachi Microcomputer Engineering Co., Ltd. on October 1, 1988. .

Incidentally, among such in-circuit emulators, there is an in-circuit emulator having a coverage tracing function in addition to a real-time tracing function as a means capable of evaluating a program (a target program) on an application device side. According to this coverage trace function, predetermined information such as a flag is sequentially stored in a single coverage trace memory in accordance with a passing address of a program executed by a target microprocessor. With this information, it is possible to measure what percentage of the instructions in the target program could be tested.

[Problems to be solved by the invention]

However, the inventor has found the following problems according to the related art.

In the prior art, in order to detect the execution state of an instruction branch instruction, for example, whether or not a branch was taken by the branch instruction, it is necessary to trace by hardware arranged outside the microcomputer. However, in microcomputers that have been enhanced by incorporating a peripheral circuit such as an instruction cache and memory management unit into a system-on-chip, a signal sufficient to detect the execution status of a branch instruction is output to the outside of the microcomputer. Since the output cannot be performed, it is difficult to trace the execution status of the branch instruction with hardware arranged outside the microcomputer.
Even if such a signal can be output to the outside of the microcomputer, the internal processing is performed at a high speed, which makes it difficult to detect the execution state of the branch instruction by external hardware. Further, when a single memory is used in a time-sharing manner by a plurality of programs as in a virtual memory system, etc., a coverage trace memory is prepared for each type of program, and the corresponding coverage trace memory is prepared so as to correspond to the currently executed program. Control of memory switching must be performed, and it is very difficult to perform such memory switching control in external hardware.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an advanced function in which an internal operation state is not reflected in a signal exchanged with an external device, or even if an internal operation state is reflected, an execution state of a branch instruction cannot be detected because internal processing is performed at high speed. It is an object of the present invention to provide a technique capable of accurately measuring the coverage of a program despite the fact that the microprocessor is used.

The above and other objects and novel features of the present application are:
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, the state of a specific bit of the branch instruction code is changed, an information area is added to the instruction code, the microcomputer executes a program including the branch instruction to which the information area is added, and the execution status of the branch instruction is changed. The information is recorded in the information area, and the coverage analysis of the branch instruction is performed based on the recorded contents of the information area. Here, the execution status of the branch instruction includes information as to whether or not a branch condition determined by referring to a condition code register holding an operation result of an arithmetic unit included in the microcomputer is satisfied.

Further, a coverage instruction having an information area is inserted into both the branch path and the passing path of the branch instruction, and when the coverage instruction is fetched, the number of times of execution of the coverage instruction is recorded in the information area. Then, based on the recorded contents of the information area, the execution state of the branch instruction is indirectly grasped and the coverage analysis is performed.

Here, the state change of a specific bit of the branch instruction code, the addition of an information area to the branch code, or the insertion of the coverage instruction can be performed at the stage of translating the source program into a machine language.

The microcomputer used for the above-described coverage measurement is configured as follows.

That is, when a state of a specific bit of a branch instruction code is changed and a branch instruction in which an information area is added to the instruction code is fetched, an instruction control unit that generates an information recording control signal for the information area; A microcomputer that includes an execution unit that records the execution status of the branch instruction code in an information area according to a control signal. An instruction control unit for generating an information recording control signal for the information area when the coverage instruction including the information area is fetched; and an execution unit for recording the execution number of the coverage instruction in the information area in accordance with the information recording control signal. And a microcomputer is formed.

[Action]

According to the above means, it is possible to perform a coverage analysis based on the contents recorded in the information area when a branch instruction or a coverage instruction is fetched, and this enables accurate coverage irrespective of the performance of the microcomputer. Acts to allow measurement. At this time, the microcomputer generates an information recording control signal when the branch instruction or the coverage instruction is fetched, and sets the execution status of the branch instruction or the coverage instruction in the information area according to the information recording control signal. Works.

Embodiment 1 FIG. 1 shows a microcomputer development system to which the method of the first embodiment of the present invention is applied.

The microcomputer development system shown in FIG. 1 is not particularly limited, but includes a user development device 10 as a microcomputer application device, an in-circuit emulator 17 capable of debugging a user program, an assembler and a linkage editor, and furthermore, a coverage analysis software. Host computer 11 on which operating environment is formed
including.

The user development device 10 includes a random access memory (RAM) in which programs and other necessary data can be written / read.
An access memory) 12, a ROM (read only memory) 13 holding an initial setting program of the user development device 10, and an I / O (input / output) for exchanging data with an external device. G) has 14. Further, the user development device 10 has an IC for mounting a microcomputer for controlling the operation of the device 10 and performing arithmetic processing.
A socket 11 is provided. In software debugging, a plug 25 provided at the end of the interface cable 26 of the in-circuit emulator 18 is connected to the IC socket 11. This interface cable
A pod 23 is arranged in the middle of 26, and in this pod 23,
A microcomputer for evaluation (hereinafter referred to as an evaluation chip) 24 having the same function as the microcomputer to be mounted on the user development device 10 is mounted. The in-circuit emulator 18 is arranged between the user development device 10 and the host computer 19, and supports software debugging by a trace function and a break function. The in-circuit emulator 18 and the host computer 19 are connected by a serial line bus line, and the bus line enables data exchange between the two. The program to be debugged is supplied from the host computer 19 via the I / O 14 or the in-circuit emulator 18 and stored in the RAM 12. The program stored in the RAM 12 is translated into a machine language, and the translation into the machine language is performed by executing assembler software in the host computer 19. In this translation process, as will be described later in detail, the state of a specific bit, for example, the most significant bit of the branch instruction is changed so that the branch instruction can be recognized as a coverage measurement target, and the instruction code is An information area for recording the execution status of the branch instruction is formed. The formation of the information area is not particularly limited, but is performed by extending the branch instruction by one word. The instructions in the program stored in the RAM 12 are sequentially executed by the evaluation chip 24. In this program execution, when the branch instruction is fetched, the execution status of the instruction is recorded in the information area of the branch instruction. The execution status is recorded by writing the execution status in the RAM 12 at an address corresponding to the information area of the branch instruction.

After the execution of the program to be debugged is completed in this way, the program in the RAM 12 is subjected to a coverage analysis performed later by the host computer 19.

Although there is no particular limitation on the program transfer path from the RAM 12 to the host computer 19, there are three types as shown by broken lines in the figure. That is, when the user development device 10 has a floppy disk device (not shown), the floppy disk device is connected to the RAM via the I / O 14.
The program stored in the host computer 19 is transferred to the floppy disk 16 on which the program is written.
A first transfer path L1 that enables a program transfer by being mounted on the in-circuit emulator 18. If the in-circuit emulator 18 is provided with a floppy disk device (not shown), the evaluation chip 24 and the in-circuit emulator 18 are used. The program in the RAM 12 is transferred to the floppy disk device, and the floppy disk 17 storing the program is loaded in the host computer 19 to enable the program transfer. Third, a program is directly transferred to the host computer 19 via the evaluation chip 24 and the in-circuit emulator 18 without using a disk.
Is the transfer path L3. The result of the coverage analysis by the host computer 19 is displayed on the display device 22 and is stored in the flop-flop disk 21 or printed out by the printer 20 as necessary.

FIG. 2 shows an example of a detailed configuration of the evaluation chip 24. Although not particularly limited, the evaluation chip 24 shown in FIG. 1 includes various caches to enable high-speed execution at the basic instruction level, and can execute high-speed pipeline processing.

The instruction prefetch unit 30 incorporates an instruction cache 30a and fetches an instruction to be executed in advance. It also has four branch windows 30b for speeding up the branch instruction system. If this is hit, the fetch of the branch destination instruction is simplified. I / O unit 35 is a user-developed device
10 and an in-circuit emulator 18 for controlling the input and output of instructions and operands. The instruction decode unit 31 decodes the fetched instruction. This decoding result is output to the control unit that contains the microprogram.
It is transmitted to the control unit 32 and controls the execution unit 33 including the arithmetic unit 33a and the various register groups 33b to perform the processing of the operand.
The processed operand is transferred to the input / output control unit 35 again and stored in the store buffer 35b. In the case of stack information, it is also stored in the stack cache 35a.
At the stage when the operand is stored in the store buffer 35b,
Processing of the next instruction is started. Further, access to the external memory is performed through checking of protection conditions and address conversion by the memory management unit 34. This processing is performed in parallel with the instruction execution processing.

The execution of the microprogram in the control unit 32 enables generation of control signals corresponding to various instructions including a branch instruction. The instruction control unit according to the present invention is realized including the control unit 32 and the instruction decode unit 31.

Here, the register group 33b in the execution unit 33
Although not particularly limited, as shown in FIG.
Accumulator (ACCA), index register (Index Register: IX), program counter (P
rogram Counter: PC), Stack Pointer (Stack Point)
er: SP), condition code register (Condition C
odes Register). The accumulator is A, B
As shown in FIG. 2, two 8-bit units are provided. The index register, the program counter, and the stack pointer have a 16-bit configuration, and the condition register has an 8-bit configuration. In particular, the condition code register holds the operation result of the arithmetic unit 33a in the execution unit 33. The register includes negative (Negative: N), zero (Zero: Z), overflow (Overflow: V), bit 7 From Carr
y: C), and half carry (Half Carry) flags from bit 3 exist. In execution of the conditional branch instruction, a predetermined flag is referred to among these flags to satisfy the condition of the branch instruction. It is possible to determine whether or not to perform.

As described above, the evaluation chip 24 in this embodiment is highly functionalized by various distributed caches and parallel processing.
In order to enable software debugging of a system including such a microcomputer, particularly accurate coverage measurement of a conditional branch instruction, the present embodiment uses the following branch instruction dedicated to coverage measurement.

FIG. 6 shows the relationship between various branch instructions executable by the evaluation chip 24 in this embodiment and their branch conditions.

For example, the conditional branch instruction BEQ is usually expressed in machine language as "67FE" as shown in FIG. Of these, "67" indicates that the instruction is a branch instruction, and "FE" indicates a relative address up to the branch destination. In this embodiment, "67FE" is a branch instruction in the normal mode. On the other hand, in the coverage measurement mode, this instruction code is not particularly limited, but is set to “E7FE”, and the most significant bit of the instruction code in the normal mode is changed to 1. "E7" in Fig. 3
Means this. At the same time, word expansion is performed, and an information area 40 having a 16-bit configuration is formed. The information area 40 is further divided into three areas 40a, 40b, 40c. When the branch is taken by the branch instruction, the first
A flag is set in the area 40a of the second area 40a, and when the branch instruction is passed without branching, the flag is set in the second area 40b. Therefore, the first and second areas 40a,
By checking the flag state of 40b, it is possible to determine whether or not the branch has been taken in accordance with the branch instruction. Further, in the present embodiment, not only the determination as to whether or not the branch is taken, but also the type of the branch condition when the branch is taken is recorded. This recording is performed by setting a flag at a corresponding location in the third area 40c.

The above-described branch instruction format is formed in the host computer 19 shown in FIG. 1 in accordance with the mode designation at the stage of translating a program described in a high-level language into a machine language by an assembler. In other words, in the case of the above branch instruction BEQ, if the normal mode is specified, “67F
When translated to "E", when the coverage measurement mode is designated, it is translated to "E7FE", and almost simultaneously with this, an information area 40 is added to the instruction code.

Then, when such a branch instruction in the coverage measurement mode is fetched in the evaluation chip 24, the control unit
32 recognizes that the branch instruction is a BEQ in the coverage measurement mode by “E7” of the branch instruction,
An information recording control signal for the information area is generated. Then, the execution unit 33 determines a branch condition under the control of the control unit 32, and in this determination, sets a flag “1” in the information area 40a when branching is performed when the branch condition is satisfied. When passing, a flag "1" is set in the second area 40b. Further, when the branch is taken due to the establishment of the branch condition, a flag “1” is set in the corresponding condition bit in the third area, which has a correspondence with the branch condition in advance. Therefore, according to the contents recorded in the information area, it is possible to determine whether or not the branch condition is satisfied and whether the type of the branch condition is satisfied by the presence or absence of the flag “1”.

For example, the branch condition in the case of the above-described branch instruction BEQ is the sixth
As shown in the figure, Z = 1, which indicates that the zero flag (see FIG. 5) of the condition code register is "1", and the operation result immediately before the branch instruction BEQ is zero. Means that Therefore, it is possible to determine whether or not the condition of the branch instruction BEQ is satisfied by determining the state of the zero flag of the condition code register.

The branch condition of the branch instruction BEQ is only Z = 1. For example, the branch condition of the branch condition BLE is Z + (NV) = 1, as shown in FIG. There is a street. That is, when Z = 1, (Z = 0) · (N = 1) · (V =
0) and (Z = 0). (N = 0). (V = 1). Although the present embodiment is not particularly limited in order to make it possible to determine which of the conditions has been satisfied and the branch has occurred, the bits b8, b9, and b10 in the third area 40c in the information area 40 indicate the above three conditions. Is assigned, and a flag “1” is set to the corresponding bit. Therefore, even when there are a plurality of cases where the condition is satisfied as in the case of the branch instruction BLE, it is possible to accurately grasp the type of the branch condition by the set contents of the third area 40c.

In the system of the present embodiment, the coverage measurement is performed as follows.

FIG. 4 shows the RAM 1 transferred from the host computer 19 via the I / O 14 or the in-circuit emulator 18.
The relationship between the arrangement of the instruction words stored in 2 and the corresponding machine language code is shown. In the figure, the branch instruction BEQ
When the coverage measurement mode is selected in the translation process by the host computer 19, the most significant bit of the instruction code is set to "1", and the information area 40 is added by word expansion. In this information area, hexadecimal (0000) is set as an initial value as shown in FIG.

When the instructions in the RAM 12 are sequentially executed by the evaluation chip 24 and the branch instruction BEQ or BNE is fetched,
The execution status of the instruction is recorded in the information area 40 of the instruction according to the branch condition for the instruction. The recording of the execution status is performed by writing the execution status at an address corresponding to the information area 40 of the instruction in the RAM 12. In addition, the recording of the execution status is performed by ORing the status at the time of the current execution and the status at the time of the previous execution in order to save the status at the time of the previous execution of the instruction.

After one test of the program in the RAM 12 is completed, information analysis of the coverage measurement result is performed in the host computer 19 based on the program in the RAM 12. When data is transferred from the RAM 12 to the host computer 19 via the second route L2 or the third route L3, the host computer 19 uses a branch instruction file as shown in FIG. Can be extracted. The branch instruction file shown in the figure is a file created by extracting only a branch instruction from a test target program by an assembler / linkage editor, and includes items of an address, an instruction word, a jump destination, and a branch condition. I have. Further, the host computer 19 analyzes the coverage measurement result using the branch instruction file, and obtains a coverage analysis result as shown in FIG. The coverage analysis result includes items such as branch, pass, executed branch condition, and test completion instruction. Such an analysis result is displayed on the display device 22, and is hard-copied by the printer 20 as necessary.

In the case where the data transfer from the RAM 12 to the host computer 19 is performed via the first route L1, if the program for the coverage analysis is loaded on the user development device 10, the above-mentioned branch instruction file is stored in the host computer.
The coverage information can be transferred from the user development device 10 to the user development device 10, and the user development device 10 can extract only the coverage information and store it on the floppy disk 16 to transmit the coverage information to the host computer 19. If the user development device 10 includes a display device and a printer, the coverage analysis and the output of the analysis result can be performed by the user development device 10.

According to the system of the present embodiment, the following effects can be obtained.

(1) The state of a specific bit of the branch instruction code is changed,
In addition, the branch instruction to which the information area is added is
When the branch instruction is fetched, the execution status of the branch instruction is recorded in the information area, so that the coverage analysis of the branch instruction can be performed based on the set contents of the information area. By clarifying the branch instruction and the branch condition, more sophisticated software management becomes possible.

(2) Due to the effect of the above (1), after a complete coverage measurement is completed for the test target program, the recorded contents of the information area 40 of all branch instructions are extracted, and the condition is satisfied for each branch instruction. Can be used to determine whether or not a branch has been taken, and when a branch has been taken due to a condition being satisfied, the condition for the branch to be taken. Can support software development.

(3) Since the host computer 19 can switch between the coverage measurement mode and the normal operation mode, after the debug of the test target program is sufficiently performed in the coverage measurement mode, particularly, Can easily return the branch instruction code to the normal mode when the operation is shifted to the actual operation, so that the word length of the branch instruction is reduced from that at the time of the coverage measurement, and the program is executed when the operation is shifted to the actual operation. Efficiency can be suppressed.

(4) Further, the effects of the above (1) and (2) can be obtained by using the branch instruction formed in the coverage measurement mode, and cannot be obtained by external hardware. Thus, the coverage of the program to be debugged can be accurately measured, even though the evaluation chip has a higher function. In other words, according to the coverage measuring method in the present embodiment, the test can be performed in the execution environment itself of the test target program without requiring special hardware, so that even if the microcomputer is sophisticated, , Can deal with it.

Second Embodiment FIG. 7 shows an example of application to a virtual storage system. As shown in the figure, this system is not particularly limited, but includes a microcomputer 50 that has been enhanced by various distributed caches and parallel processing, a RAM 51 that stores a test target program and the like, and a system according to the present embodiment. ROM52 in which a program for initial setting and the like are stored,
I / O 53 that enables input and output of data to and from storage device 54
And The basic configuration of the microcomputer 50 is the same as that shown in FIG. For example, a floppy disk device is applied to the storage device 54, and a plurality of programs are stored so as to be distinguished by A, B, and C. By selectively transferring the programs A, B, and C to the RAM 51 via the I / O 53, the plurality of programs A, B, and C can be used in a time-division manner. In such a system, even when all of the plurality of programs A, B, and C in the external storage device 54 are to be tested, the state of the specific bit of the branch instruction, for example, the state of the most significant bit is changed as in the above embodiment. By adding an information area for setting the execution status of the branch instruction to the instruction code (see FIG. 3), it is possible to accurately measure the coverage of the branch instruction.
For example, when the program A is transferred to the RAM 51 and executed by the microcomputer 50, the execution status of the instruction is recorded in the information area of the branch instruction by the above-described branch instruction fetch. The information area and the recording of the execution status in the area are the same as in the first embodiment, and will not be described in detail here. When the program A is shifted to the execution of another program, for example, the program C, the program C is stored in the RAM 51. However, before the program C is transferred to the RAM 51, the program in the RAM 51 is executed. A is saved in the storage device 54. As a result, it is possible to prevent the coverage measurement result for the program A from disappearing. After that, the program C is transferred to the RAM 51, and the microcomputer 50 performs the transfer in the same manner as the program A.
The program C in the RAM 51 is executed, and the execution status of the branch instruction is recorded in the information area of the branch instruction. still,
When the program is shifted to another program, the program is saved as described above. When the same branch instruction is executed a plurality of times, the logical sum of the execution status already recorded in the information area and the current execution status is obtained, as in the case of the above-described embodiment. The execution status is recorded in the information area.

When a series of tests for all the test target programs are completed in this way, by extracting a branch instruction from the program saved in the storage device 54, the branch instruction is extracted in the same manner as in the above embodiment. Can be accurately analyzed. Note that this coverage analysis is performed in the same manner as in the above embodiment.
(See FIG. 1) or by the microcomputer 50.

Third Embodiment FIG. 8 shows a format of a CVR (coverage) instruction used in another embodiment. Although not particularly limited, the CVR instruction shown in the figure includes an instruction code indicated by 60 and an information area indicated by 61. This instruction code (5555) indicates that the instruction is a CVR instruction, but may have any value as long as it indicates a CVR instruction. When this instruction is executed by the microcomputer, the information area 61 records the number of times the instruction is executed.

FIG. 9 shows a basic flow of an ordinary program including a branch instruction, and FIG. 10 shows a flow of a program including the above CVR instruction.

When performing coverage measurement using the above CVR instruction,
As shown in FIG. 10, CVR instructions 64 and 65 are inserted into a branch instruction passing path 62 and a branch instruction branch path 63. Such CVR instruction insertion can be performed at the assembler stage of the test target program. The number of executions of the CVR instruction is recorded in the CVR information area 61, and its initial value is 1
Hexadecimal (0000). The execution count of the CVR instruction is
This is done by a microcomputer executing the R instruction. For example, when using the system shown in FIG.
It is not necessary to form an information area in the branch instruction, but the CVR instruction is inserted in the host computer 19 immediately after the branch instruction, that is, in the passing path 62 and the branch path 63 of the branch instruction. Then, the program including the CVR instruction is transferred to the RAM 12, and the evaluation chip 24 executes the program. In the execution of this program, the branch instruction in FIG. 10 is fetched, and when the branch instruction is passed because the condition of the branch instruction is not satisfied, the value of the information area 61 in the CVR instruction 64 is incremented by 1 and the branch condition is satisfied. Information area 61 in CVR instruction 65 when branching
Is incremented by one. Such an increment is performed by the execution unit 33 under the control of the control unit 32. This increment is terminated by hexadecimal (FFFF). The value of the information area indicates the number of times the branch instruction has passed or the number of branches, whereby the execution status of the branch instruction can be indirectly grasped, and the same effect as in the above embodiment can be obtained.

Note that the CVR instruction is unnecessary after the coverage measurement is completed, and thus is deleted.

Fourth Embodiment FIG. 11 shows a format of a CVR instruction used in another embodiment. The CVR instruction shown in the figure is a code (555) indicating the CVR instruction, as in the third embodiment.
5), but the most significant bit of this code is used as an information area. That is, when the CVR instruction is executed by the microcomputer, the most significant bit of the instruction code (5555) of the CVR is set to "1" and is set to a hexadecimal number (D555). However, at the time of the second or subsequent CVR instruction fetch, a write cycle to the most significant bit is not generated.

The CVR instruction in the present embodiment is inserted into both the passing path and the branch path of the branch instruction in the same manner as in the third embodiment, and is executed by the evaluation chip 24 in the same manner as in the above embodiment. The execution status of the branch instruction can be recorded by 1-bit information corresponding to the branch. Therefore, also in this embodiment, the same effect as in the above embodiment can be obtained. In particular, in the present embodiment, in the second and subsequent CVR instruction fetches in the coverage measurement, a write cycle to the information area (the most significant bit of the instruction code) is not generated, so that even when testing a high-speed system, program execution caused by the coverage measurement is performed. A decrease in speed can be prevented.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, various instructions including a branch instruction are executed by the evaluation chip 24, but an actual chip mounted on the actual user machine may be used. Further, in the above embodiment, the test target program is stored in the RAM 12 in the user development device 10, but a lending memory in the in-circuit emulator 18 or another writable / readable external memory may be used. .
Further, in the first embodiment, the third area 40c for recording the type of the branch condition may be omitted in order to simplify the coverage measurement.

In the above description, mainly the case where the invention made by the present inventor is applied to a microcomputer development system or a virtual storage system which is a utilization field as the background has been described, but the present invention is not limited thereto. For example, it can be widely applied to all medium and large computer systems and their development systems. The present invention can be applied to at least a condition requiring software debugging.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the state of a specific bit of the branch instruction code is changed so that the instruction code can be recognized as a coverage measurement target, and an information area is added to the instruction code, or the coverage instruction to which the information area is added is a branch instruction. By inserting it immediately after the information area, the execution status of the branch instruction is recorded in the information area, and by analyzing the recorded contents of the information area, accurate coverage measurement can be performed. In addition, the detection of the branch instruction execution status in such a coverage measurement method can be performed by writing the execution status in the microcomputer instead of using a signal output to the outside of the microcomputer. In this case, the execution state of the branch instruction can be detected directly or indirectly based on the execution state of the coverage instruction, which greatly contributes to the improvement of software quality.

Further, when a branch instruction or a coverage instruction to which an information area is added as described above is fetched, a microcomputer capable of recording a branch instruction execution state or a coverage instruction execution state in the information area,
The above-described coverage measurement can be accurately performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer development system to which the method of the first embodiment of the present invention is applied, FIG. 2 is a detailed block diagram of the microcomputer (evaluation chip) shown in FIG. 1, and FIG. FIG. 4 is a view for explaining the relationship between the instruction word arrangement in the RAM and the machine language code of the instruction in the system shown in FIG. 1, and FIG. 5 is a diagram showing the main registers in the microcomputer and their bit configuration. FIG. 6 is an explanatory diagram of various branch instructions and corresponding branch conditions. FIG. 7 is a block diagram of a system of another embodiment. FIG. 8 is a block diagram of a coverage instruction according to a method of another embodiment. Format explanation diagram, FIG. 9 is a flowchart showing a basic flow of a program including a branch instruction, and FIG. 10 shows a basic flow of a program in which a coverage instruction is inserted. Flowcharts, FIG. 11 is the format explanatory diagram of a coverage instruction according to another embodiment the method, FIG. 12 is an explanatory view of a branch instruction file 13 is an explanatory diagram of the coverage analysis results. 10 ... User development device, 12,51 ... RAM, 13,52 ... ROM, 14,53
... I / O, 16,17,21 ... Floppy disk, 18 ... In-circuit emulator, 19 ... Host computer, 20 ... Printer, 22 ... Display device, 23 ... Pod, 24,50 ... Microcomputer, 30 ... Instruction prefetch unit 31 instruction decoding unit, 32 control unit, 33 execution unit, 34 memory management unit, 35 input / output control unit, 40,61 information area, 40a first area, 40b second area , 40c ... third area, 54 ... storage device, 60 ...
Instruction code, 62: passing path, 63: branching path, 64, 65: CVR
order.

Claims (5)

(57) [Claims] A step of changing a state of a specific bit of a branch instruction code so that the instruction code can be recognized as an object of coverage measurement, adding an information area to the instruction code, and adding the information area to the instruction code. Causing a microcomputer to execute a program including a branch instruction,
A coverage measurement method including a step of recording the execution status of the branch instruction in the information area, and a step of performing a coverage analysis of the branch instruction based on the recorded contents of the information area, wherein the information area is A storage area corresponding to a branch condition determined with reference to a condition code register holding an operation result of an arithmetic unit included in the microcomputer, and whether the branch condition determined by execution of the branch instruction is satisfied A method of measuring coverage, wherein information on whether or not the data is written is stored in the corresponding storage area. 2. A step of inserting a coverage instruction including an instruction code indicating a coverage instruction and an information area for recording the number of times of instruction execution into both a branch path and a passing path of a branch instruction. The program in which the coverage instruction is inserted is executed by the microcomputer, and each time the corresponding coverage instruction is executed by the microcomputer in the branch path or the passing path of the branch instruction, the program is recorded in the information area of the coverage instruction. Incrementing the number of executed instructions, and performing a coverage analysis of the branch instruction based on the number of executed instructions in the information area of the coverage instruction. 3. Changing the state of a specific bit of the branch instruction code and adding an information area to the branch instruction code or inserting the coverage instruction at the stage of translating a source program described in a high-level language into a machine language. Claim 1 to be performed
Or the coverage measuring method according to 2. 4. A microcomputer comprising: an arithmetic unit for performing a predetermined operation; and a condition code register for storing an operation result of the arithmetic unit, wherein a branch condition determined with reference to the condition code register is An instruction control unit that, when fetching a branch instruction to which an information area including a corresponding storage area is added, generates an information recording control signal for the information area; An execution unit for recording in the information area of the branch instruction, the execution unit writes information on whether or not the branch condition determined by execution of the branch instruction is satisfied into the corresponding storage area. A microcomputer comprising the means of (1). 5. A program in which a coverage instruction including an instruction code indicating a coverage instruction and an information area for recording the number of executed instructions is inserted into both a branch path and a passing path of a branch instruction. A microcomputer that executes, each time a corresponding coverage instruction is executed in a branch path or a passing path of the branch instruction, an execution unit that increments an instruction execution number recorded in an information area of the coverage instruction. A microcomputer characterized by including: