JP2953405B2 - Method for speeding up logic simulation and logic simulation apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for logic simulation, and more particularly to a method and apparatus for speeding up logic simulation.

[0002]

2. Description of the Related Art Conventionally, as a logic simulator of this type, in addition to a binary simulator which handles only "0" and "1" as signal values, for example, X values other than "0" and "1" as signal values are used. (Indefinite), a multi-value simulator that handles Z (high impedance state) is used. Among them, the binary simulator simulates the entire logic circuit with binary values, and the multi-value simulator simulates with multi-values.

[0003]

In the above-described conventional logic simulator, the multi-value simulator simulates a logic circuit in consideration of multi-values.
Compared to a value simulator, it has problems such as slow processing. On the other hand, a binary simulator has a fast simulation speed, but cannot handle multi-values other than “0” and “1”. There is a problem that a simulation of a logic circuit in which a value other than “0” or “1” is generated cannot be accurately performed, and therefore, its application range is narrowed.

[0004] By the way, most of the logic simulation is a binary operation, but if there is a multi-value in a part, the multi-value operation must be performed, and the value that can be handled by a general processor is up to a binary value. In order to speed up the multi-valued simulation, for example, (1) hardware-based multi-valued operation, (2) switching between two-valued / four-valued by a circuit,
And other methods have been proposed.

The method (1) described in, for example,
Japanese Patent Publication No. 174,407 discloses that a multi-valued coded logical operation is executed by a single instruction so that it is possible to flexibly cope with various coding rules and definitions of operations, without reducing precision. There has been proposed a configuration of a vector processing device that enables high-speed logic simulation. Japanese Patent Application Laid-Open No. 62-195570 discloses that, when a simulation is performed using three or more multi-valued signal state values, a dedicated arithmetic unit performs basic bit operation processing of a plurality of signals obtained by vectorizing signals. There has been proposed a configuration of a processing device that efficiently simulates a logical operation of a logic circuit.

However, each of these conventional systems requires a special hardware device for exclusive use.

On the other hand, as the method (2), for example, Japanese Patent Laid-Open Publication No. Hei 3-163666 discloses that a logic circuit to be simulated includes an element which generates only binary values "0" and "1". , "0", and elements that also generate values other than "1". Elements that generate only two values "0" and "1" are simulated using a high-speed binary simulator. A method has been proposed in which a device that also generates a value other than "1" and "1" is simulated using a multi-value simulator. Japanese Patent Application Laid-Open No. 4-107681 discloses that a table for storing state values is expressed in such a manner that a state value is expressed by two bits in a quaternary mode and a state value is expressed by one bit in a binary mode. Mode and 4 for normal-scale logic circuits.
A logic circuit simulation apparatus that performs a simulation in a value mode and performs a simulation in a binary mode for a large-scale logic circuit, thereby enabling a simulation up to twice as large as a normal logic circuit. Has been proposed.

However, these conventional methods switch between binary / multi-valued simulation for each element (Japanese Patent Laid-Open No. 3-163666) or for a large-scale / normal-scale circuit (Japanese Patent Laid-Open No. 4-107681). Therefore, there is a problem that the applicable range is narrow.

SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above circumstances, and has as its object to speed up logic simulation and suppress deterioration in accuracy without requiring special dedicated hardware. A method and apparatus for speeding up a logic simulation, which shortens the simulation time required for a large-scale logic circuit and takes a long time, and consequently shortens the time required for logic verification and improves productivity. Is to provide.

[0010]

Means for Solving the Problems] To achieve the above object, the fast method of logic simulation of the present invention, Starring
Binary / multi-valued judgment indicating whether the calculated value is binary or multi-valued
And (a) refer to the binary / multi-value determination flag during execution of the logic simulation .
To determine whether the input value is binary or multi-valued.
Includes a-up, the steps of: controlling switching between (b) in response to said determination result, the binary arithmetic unit and the multi-level calculation unit, logical
During the execution of the physical simulation
It is characterized in that a binary operation and a multi-value operation are dynamically switched in operation units .

[0011] The logic simulation apparatus of the present invention, logical
The operation means of the logical simulation is
To judge binary / multi-valued operation value generated during execution of
Determining means, and a binary operation according to the determination result of the determining means
And a control means for switching control between the unit and the multi-value arithmetic unit.
To respond to the operation value during the execution of the logic simulation.
In the meantime, binary / multi-valued operation is dynamically switched to the operation unit.
And features .

In the present invention , the operation value is binary.
A flag indicating whether the value is multivalued or multivalued;
However, referring to the flag, whether the operation value is binary or not
It is determined whether the value is a value .

[0013]

Embodiments of the present invention will be described below. According to a preferred embodiment of the present invention, in the preferred embodiment, the operation means of the logic simulation determines a binary / multiple value of an operation value generated during the execution of the logic simulation (2 in FIG. 1). Means (5 in FIG. 1) for switching between the binary operation unit (3 in FIG. 1) and the multi-value operation unit (4 in FIG. 1) in response to the operation value during execution of the logic simulation. It is characterized in that the binary / multi-valued operation can be dynamically switched in the operation unit.

Further, in the embodiment of the present invention, preferably, a binary / multi-value judgment flag (7 in FIG. 1) is provided for the operation value, and a multi-value judgment is performed for the operation value of the operation means. By means (8 in FIG. 1), a binary / multi-value determination flag (FIG. 1)
10) is added.

According to the preferred embodiment of the present invention, in order to speed up the multi-valued simulation, it is possible to use the logic simulation by software without using special hardware as in the above-described conventional method. This is to increase the speed.

In a preferred embodiment of the present invention,
In order to speed up the operation, a part of the operation is specialized to binary. Then, while performing the binary calculation, the calculation is dynamically switched to the multi-value during the simulation from the determination result of the multi-value determination means (2 in FIG. 1) based on the calculated value at a necessary place.

As described above, in the embodiment of the present invention, preferably, binary / multi-value switching is performed in units of operation, so that the speed of binary simulation can be increased.

In the embodiment of the present invention, 2
Since the value / multi-value calculation is dynamically switched, the logic simulation can be switched to the multi-value simulation during execution, and the range of application is wide.

In the logic simulation,
Only two values result from a binary operation. In addition, since the multi-value simulation also tends to be binarized gradually, according to the embodiment of the present invention, as a result, the speed of the multi-value simulation can be increased.

Further, the embodiment of the present invention has an advantage that special hardware is not required and can be implemented on a computer system by software.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the above-mentioned embodiment of the present invention in more detail, an embodiment of the present invention will be described below. The present invention is to speed up the operation unit of the logic simulator. Hereinafter, the operation unit of the logic simulator will be described as one embodiment of the present invention.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. The calculation unit that has been speeded up determines whether the input operation value (operated value) 6 is binary or multi-valued by a flag indicating whether the operation value is binary or multi-valued (operated value multi-valued judgment). The multi-value determination unit 2 in the calculation unit 1 of the logic simulator that receives the calculated value as an input and makes a binary / multi-value determination using the flag 7.

If all the input values are binary according to the determination by the multi-value determination section 2, the arithmetic control section 5 performs an arithmetic operation in the binary arithmetic section 3 and sets the arithmetic result as an arithmetic value 9 in a predetermined storage area. To be stored. At this time, the multi-value determination flag 10 is stored as binary.

If the input value is partly multi-valued, the operation control unit 5 calls the multi-valued operation unit 4 to perform the operation, stores the operation result in the operation value 9, and judges the result value as multi-valued. The result is 2
Whether it is a value or a multi-value is stored in the multi-value judgment flag 10.

FIG. 2 is a diagram schematically showing a processing flow according to an embodiment of the present invention.

The value holding table 20 in FIG. 2 corresponds to the operand value 6, the operand value multi-value judgment flag 7, the operation value 9, and the operation value multi-value judgment flag 10 in FIG. Among them, the multi-value determination flags 7 and 10 are the binary / multi-value flags 21 of the value holding table 20.

The flag 21 is provided in one-to-one correspondence with one state value 22.

Referring to FIG. 2 and FIG. 1, phase 1
Then, the input value to the arithmetic unit 1 is determined, and the binary arithmetic unit 3 or the multi-level arithmetic unit 4 respectively determines the binary value and the multi-value case depending on the determination result. (Phase 2).

In the next phase 3, the result of the operation is 2
It is determined whether the value is multi-valued or multi-valued.
Since multi-values do not occur from a binary operation of only “1”, multi-value determination is unnecessary in the case of binary values.

Then, in the phase 4, the value holding table 20
To store the value of the operation result.

As described above, although there is a change from multi-value to binary, there is no change from binary to multi-value, so that the binary simulation is mainly performed in the whole simulation. Also in the case of multi-valued arithmetic,
Since there is a tendency to gradually binarize, as a result, multi-value simulation is also speeded up.

[0032]

As described above, according to the present invention,
This has the effect of speeding up multi-value simulation. Therefore, the present invention shortens the simulation time required for a large-scale logic circuit, which requires a long time, and reduces the time required for logic verification.

The reason is that, in the present invention, a part of the operation of the multi-valued simulation is performed in binary, and this switching can be dynamically performed during the simulation operation in units of operation. Most of the operations in the multi-value simulation are binary operations.

According to the present invention, the logic simulation is sped up without the need for special dedicated hardware, and the switching between binary and multi-valued operations can be performed in units of operation. Avoids deterioration of accuracy due to, for example, calculating the part to be simulated with binary values,
Good simulation accuracy can be achieved.
Therefore, according to the present invention, it is possible to shorten the time required for logic verification and to improve productivity.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Operation part of logic simulator 2 Multi-value judgment part 3 Binary operation part 4 Multi-value operation part 5 Operation control part 6 Operand value 7 Operand value multi-value judgment flag 8 Multi-value operation part 9 Operation value 10 Operation value multi-value Judgment flag

Claims (4)

(57) [Claims] 1. A method for accelerating a logic simulation.
And a binary / multi-value determination indicating whether the operation value is binary or multi-valued.
A regular flag is prepared in advance . (A) During the execution of the logic simulation, the binary / multiple
Referring to the value determination flag, the input value is binary or multi-valued
And determining whether there are, (b) in response to said determination result, the binary arithmetic unit and the multi-level calculation unit
Anda controlling switching the door, the operation during logic simulation
Dynamically switch between binary and multi-valued operations in operation units according to the value
A method for speeding up a logic simulation. 2. A logic simulation operation means comprising: a binary operation unit for performing a binary logic simulation; a multivalued operation unit for performing a multivalued logic simulation; and a binary / arithmetic operation value generated during execution of the logic simulation. determining means for determining the multi-level, in accordance with the determination result of said determination means, before and the binary arithmetic unit
A multi-valued operation unit, and control means for controlling switching between the two-valued operation unit, wherein during the execution of the logic simulation, a binary / multi-valued operation is dynamically switched in operation units according to the operation value. Simulation device . A flag indicating whether the operation value is binary or multi-valued, wherein said judging means refers to said flag to determine whether the operation value is binary or multi-valued. determines whether it is, logic simulation instrumentation of claim 2 wherein the
Place . 4. The operation means of the logic simulation,
According to whether the operation result is binary or multi-valued ,
3. The logic simulation apparatus according to claim 2, wherein the operation result is output and stored in a flag indicating whether the operation result is binary or multi-valued.