JP2963501B2 - Automatic delay time adjustment delay circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal delay circuit capable of automatically adjusting a delay time.

2. Description of the Related Art In an apparatus having both an analog section and a digital section, a timing signal between the two sections needs to be delayed by an appropriate time in order to take timing between the two sections. The delay time at this time is generally several tens of ns (nanosecond)
To generate such a short time using the system clock, to a small extent, it is necessary to use a very fast system clock. However, this is often difficult in terms of cost, and a method of delaying a signal by a necessary time using a delay circuit including a plurality of delay elements has been widely used.

Problems to be Solved by the Invention In a circuit for delaying a signal using a delay element, there is a problem that the delay time varies due to variations of the individual delay elements, fluctuations in the use environment temperature, power supply voltage, and the like. For this reason, conventionally, the delay time characteristic is inspected for each delay circuit (normally integrated on one substrate), and adjusted by a dip switch or the like so as to obtain a predetermined delay time (delay element). Selection).

The present invention eliminates such troublesome manual adjustment,
An object of the present invention is to provide a delay circuit capable of automatically adjusting a delay time.

Means for Solving the Problems To achieve the above object, in a delay circuit according to the present invention, as shown in FIG. 1, one of a plurality of different delay times according to an external switching signal is provided. A signal delay circuit 10 for delaying an input signal by two delay times, a delay time measuring means 14 for measuring a delay time of the signal delay circuit, and a switching signal to be input to the signal delay circuit 10 based on the measured delay time. And a selecting means 12 for generating the image.

The selection means selects one of the plurality of delay times of the signal delay circuit based on the delay time of the signal delay circuit obtained by the measurement by the delay time measurement means.
Thereby, for example, even if the delay time characteristic of the signal delay circuit 10 fluctuates due to factors such as environmental temperature and power supply voltage,
It becomes possible to select a delay time such that the delay time of the output signal is closest to the desired value.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 shows a configuration of a delay circuit according to the present invention used in a part of a digital copying machine. This delay circuit is used to time a signal between the digital control unit and the analog control unit of the digital copying machine, and to obtain a delay signal b obtained by delaying the input pulse signal a from the analog control unit by a predetermined time dt. (FIG. 3 (a)). In this circuit, a delay circuit DLY composed of four delay elements is used to delay the input signal a. However, there is an individual difference between the delay elements, and even in use, due to fluctuations in environmental temperature and power supply voltage. Delay times can vary. Therefore,
In this circuit, first, the delay time of the delay circuit DLY is measured, and the combination of the delay elements is automatically selected based on the result. Hereinafter, the operation will be described. Note that, as shown in FIG. 3A, the following automatic adjustment (delay set) operation is performed only during the period in which the delay set signal c is input, during the normal operation of this circuit. FIG. 3B is an enlarged view of the period B within the dotted line in FIG. 3A.

After passing through the first OR circuit OR1, the input signal a is input to a delay circuit DLY composed of four serially connected delay elements DLY1, DLY2, DLY3 and DLY4. Terminals are output immediately after each delay element DLY1, DLY2, DLY3, DLY4 of the delay circuit DLY.
These four terminals are four AND circuits AND4, AND5, AND6, AND7
Is input to each of. A signal from the decoder DEC is input to the other input terminal of each of the AND circuits AND4, AND5, AND6, and AND7.
The H signal is sent to only one of AND4, AND5, AND6, and AND7. The outputs from the four AND circuits AND4, AND5, AND6, AND7 are combined by a second OR circuit OR2 to become a delayed output b.

With the above circuit, four delay elements DLY1, DLY2, DLY3 and DLY4 are used in accordance with the output signal of the decoder DEC.
Species combinations (DLY1), (DLY1 + DLY2), (DLY1 + DL
The input signal a delayed by any one of (Y2 + DLY3) and (DLY1 + DLY2 + DLY3 + DLY4) is output as the delay signal b. In this embodiment, the delay elements DLY1, DLY2, DLY3, and DLY4 of the delay circuit DLY have the same delay time d1 because they are formed with the same configuration on one substrate. Therefore, in this circuit, d1, 2 · d1,
One of the four delay times of 3 · d1 and 4 · d1 is automatically selected.

On the other hand, the delay set signal c is sampled by the first D flip-flop DFF1 by the system clock signal d, and its Q output is input to the first AND circuit AND1. First
The Q ^- output of the flip-flop DFF1 is sampled by the second D flip-flop DFF2 and input to the first AND circuit AND1. As a result, the output signal e of the first AND circuit AND1
Is a pulse having a width of one cycle of the system clock signal d in a period when the delay set signal c is H, as shown in FIG. 3 (b). Since this signal e is used to determine the period of delay time measurement as described below, it is called a measurement period signal.

The output (measurement period signal e) of the first AND circuit AND1 is divided into two, one of which is output to the third AND circuit AND3 as it is, and the other is inverted, and then the third signal is output via the delay element DLY0.
Input to the ND circuit AND3. Therefore, the output f of the third AND circuit AND3 becomes a pulse having the width of the delay time d0 of the delay element DLY0, as shown in FIG. 3B. This signal f is called a test pulse.

The test pulse f is supplied to the first OR circuit OR1 and the delay circuit DLY (4
After passing through all of the delay elements DLY1, DLY2, DLY3, and DLY4), they are input to the second AND circuit AND2. 2nd AND circuit AND2
Then, an AND operation is performed between the test pulse f delayed by the delay circuit DLY and the measurement period signal e, and the result is referred to as a first OR circuit OR.
Enter 1 That is, the test pulse f is [OR1 → (DLY1 + DLY2 + DLY3 + DLY4) while the measurement period signal e is H.
→ AND2 → OR1] loop 1 is continuously repeated (FIG. 3 (b)). Here, the time required for the test pulse f to loop once is the delay time dl of the delay circuit DLY.
(= 4 · d1).

The output g of the fourth delay element DLY4 and the measurement period signal e are input to the counter CTR.
The number of loops of the test pulse f during the measurement period signal e is counted by the (counter clock signal). Note that a clear pulse h is input to the counter CTR just before the delay set signal c is input, and the previous count value is reset to 0. In the example of FIG. 3B, the test pulse f is counted as looping three times during the current measurement period e. The counting result is output to the decoder DEC as a 3-bit signal. Based on this loop count data, the decoder DEC combines four types of delay elements (DLY1), (DLY1 + DLY2), (DLY1
+ DLY2 + DLY3) or (DLY1 + DLY2 + DLY3 + DLY4) is determined, and the corresponding AND circuit AND4, AND5, AND
6, Send H signal only to AND7.

As described above, in the above-described circuit, the test pulse f is looped for a predetermined time (measurement period signal e) through a delay circuit including four delay elements DLY1, DLY2, DLY3, and DLY4, and the number of loops is counted. The delay circuit
The delay time of DLY is measured. (Note that in the above embodiment, the relative delay time due to the number of loops is measured instead of measuring the absolute delay time dl of the delay circuit. It is also possible to calculate the value of the time dl.)
Based on the delay time thus measured (more precisely, the number of loops of the test pulse f), an optimal combination of delay elements is determined by the decoder DEC and the four AND circuits AND4, AND5, and AN.
Selected by D6 and AND7. Therefore, by appropriately setting the decoding program of the decoder DEC in advance, even if the delay time characteristics of the individual delay elements are different for each delay circuit DLY, it is compensated and the closest to the desired delay time is obtained. A combination of delay elements can be automatically selected. Moreover, since this delay set operation can be performed in a short time between normal operations as shown in FIG. 3 (a), it is also possible to correct a change in delay time of the delay element due to a change in environmental temperature or power supply voltage. Can be.

As described above, in the above circuit, the delay times of the delay elements DLY1, DLY2, DLY3, and DLY4 included in the delay circuit DLY are all equal, and the delay times are d1, 2, d1, 3, d1,
Although only four types could be selected from the four types of 4.d1, the delay circuit DLY can be configured as shown in FIG. 4 to make it possible to further finely adjust the delay time.

In FIG. 4, the delay circuit DLY includes five delay element units 22a, 22b, 22c, 22d, and 22e, and each delay element unit has one (22a), two (22b), four (22c), 8
(22d) and 16 (22e) identical delay elements 20. That is, assuming that the delay time of the unit delay element 20 is d2, the delay times of these delay element units are d2, 2 · d2, 4 · dd, 8 · d2, and 16 · d2, respectively. From 32 ・ d2
A delay circuit DLY having an arbitrary delay time up to the above can be configured.

In the circuit of FIG. 4, the circuit up to creation of the measurement period signal e and the test pulse f is the same as the circuit shown in FIG. In this circuit, an inverter INV11, an AND circuit AND11, and an OR circuit OR11 are provided in each of the five delay element units 22a, 22b, 22c, 22d, and 22e constituting the delay circuit DLY. When the measurement period signal e enters the OR circuit OR11, the output of the OR circuit OR11 becomes H throughout the measurement period. Thereby, each delay element unit 22a, 22b, 22c, 22d, 22
e, three-state buffers B6, B7, B8,
B9, B10 are ON, inverting buffers B1, B2, B3, B provided in parallel
4 and B5 are turned off, and the test pulse f passes through all the delay element units 22a, 22b, 22c, 22d and 22e and the second AND circuit A
Return to ND2. While the test pulse f goes around this loop, the number of times is counted by the counter CTR, and is delivered to the decoder DEC when the measurement period ends. Based on this count data (the number of loops, that is, data representing the total delay time of the delay circuit DLY), the decoder DEC follows a predetermined program and sets the delay element units 22a, 22b, and 22c closest to the predetermined delay time. , 22d, and 22e are selected. The result of this selection is terminal Y
The H signal is output from 1, Y2, Y3, Y4, Y5 and supplied to the AND circuit AND11 corresponding to the selected delay element unit. As a result, the buffer (one or more of B6, B7, B8, B9, B10) of the selected delay element unit is turned on, and the inversion buffers (B1, B2, B3, B4, B5) are turned off.
Becomes F. Conversely, the buffer of the unselected delay element unit is turned off, and the inversion buffer is turned on.
Thus, during the normal operation period, the input signal a
After passing through the 1OR circuit OR1, only the delay element unit selected by the decoder DEC is passed, and the delay element units not selected bypass the inverting buffer side and are output as the delay signal b.

As described above, according to the present invention, the actual delay time of the signal delay circuit is measured, and the optimum delay time is selected from a plurality of delay time options of the signal delay circuit according to the measurement result. Accordingly, it is possible to always correct the delay time closest to the desired value by correcting the individual differences of the delay circuits and the fluctuation factors such as the environmental temperature and the power supply voltage.

[Brief description of the drawings]

1 is a diagram corresponding to claims of the present invention, FIG. 2 is a circuit diagram of an automatic adjustment type signal delay circuit according to an embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are timings of various signals in the circuit. FIG. 4 is a circuit diagram showing another example of the configuration of the delay circuit.

Claims (1)

(57) [Claims] 1. A signal delay circuit for delaying an input signal by one of a plurality of different delay times according to an external switching signal, and a delay time for measuring a delay time of the signal delay circuit An automatic delay time adjusting delay circuit comprising: a measuring means; and a selecting means for generating a switching signal to be input to a signal delay circuit based on the measured delay time.