JP2982656B2 - Transmission system clock synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission system clock synchronizer for synchronizing transmission and reception sampling clock frequencies in a digital transmission system having independent sampling and transmission line clock frequencies.

[0002]

2. Description of the Related Art FIG . 9 shows, for example, Japanese Patent Publication No. 61-30456.
Configuration of a conventional transmission system clock synchronizer disclosed in
It is. On the transmitting side in FIG. 9A, the A / D converter 1 converts a transmission analog signal 1 such as a television or facsimile signal.
01 to transmit the sampling clock 103 from the transmission sampling clock generator 5 into a slave Ide digital signal. The transmission buffer memory 2 once writes the digital signal from the A / D converter 1 and sequentially reads out the digital signal in accordance with the transmission line clock 104 from the frame generation means 4. The multiplexing / synthesizing unit 3 applies the transmission relative frequency information 10 from the transmission relative clock counting unit 6 to the digital signal from the transmission buffer memory 2.
5 are multiplexed. Frame generation means 4, and outputs to the transmission path as a multiplexed signal and converted to channel coding transmission frame signal 102 from the multi-synthesizer 3, it generates a line clock 104 to determine in advance by the transmission system. The transmission sampling clock generator 5 generates a desired transmission sampling clock 103 with a voltage controlled oscillator (VCO) that controls the oscillation frequency according to the transmission analog signal 101. When it is determined independently of the transmission analog signal 101, it may be a simple oscillator. Transmission relative clock counting means 6 is a 1 / N frequency division pulses generated for the transmission sampling clock 103 from the transmit sampling clock generator 5 as shown in FIG. 9 (c), the period from the frame generation unit 4 N / f _s (f _s transmission sampling clock frequency) according to the free Murrell line clock 104 to
Counting Te generated to transmit the relative frequency information 105ΔS = N ·
f _l / f _s (f _l is a transmission line clock frequency) to the capture. Figure 9 frame termination unit 11 at the receiving side (b)
Establishes frame synchronization with the transmission frame signal 102 from the transmission line and reproduces the transmission line clock 104. The demultiplexer 12 receives the signal from the frame terminating unit 11
The transmission frame signal to that release multiple content and the digital signal and the transmission relative frequency 105. Reception buffer memory 13 is one <br/> Dan writes the digital signal from the demultiplexer 12 sequentially reads according to the received sampling clock 107 from the receiver sampling clock generator 15. The first D /
A converter 14 converts according to the received sampling clock 107 of the digital signal from the receive sampling clock generator 15 from the receiving buffer memory 13 to the received analog signal 106. The reception sampling clock generator 15 outputs the second D
VCO controlling the oscillation frequency according to control voltage signal 111 from A / A converter 19
7 is generated. The reception relative clock counting means 16 is configured as shown in FIG.
In 1 / N frequency division pulses generated for receiving <br/> signal sampling clock 107 from the receiver sampling clock generator 15 as shown in (c), the period N / f _r (f from frame termination section 11 _r generates counts to free Murrell line clock 104 to receive sampling clock frequency) receiving the relative frequency information 108
ΔR = Nf _l / f _r uptake to output. The subtractor 17
Transmission relative frequency information 105 from the demultiplexer 12 and reception relative frequency information 1 from the reception relative clock counting means 16
08 is subtracted. The integrator 18 integrates the difference signal 109Δ from the subtractor 17, and obtains an integrated signal 110V = V
_{0 + k∫ (f s -f r} ) dt (∵Δ = ΔS-ΔR = N · f l
_{(F s -f r) / (} f s · f r), k outputs a constant).
Second D / A converter 19 outputs the integrated signal 110 from the integrator 18 as a D / A conversion by the control voltage signal 111.

[0003] The transmission system clock synchronizer of the above-mentioned conventional example includes:
Transmission line by controlling the f _r as relative relationship information ΔS and ΔR coincides with the clock frequency f ₁ and transmits the sampling clock frequency f _s and receive sampling clock frequency f _r, and f _s for any f ₁ It takes the system to synchronize the f _r.

Transmission and reception relative clock counting means 6 and 16
FIG. 9C shows the transmission and reception relative frequency information 105 and 108Δ based on the frequency deviation δ when the transmission and reception sampling clocks 103 and 107 have a relatively high frequency accuracy.
Determine S and ΔR. For example send and select 1 / N dividing the frequency of the reception sampling clock 103 and 107 to the frame frequency 30Hz television signal First, when the 30MHz frequency f ₁ of the line clock 104, [Delta] S = delta
Required number of bits of the counter and the register becomes ^{R = 30 × 10 6/30} = 10 6 ≒ 2 20 becomes 20 bits. Therefore, since the circuit scale becomes large, the variable range of the transmission and reception sampling clock frequencies f _s and f _r is limited as follows,
The range of ΔS and ΔR is limited. _{f 0 (1-δ) <} f s <f 0 (1 + δ) f 0 (1-δ) <f r <f 0 (1 + δ) Nf 1 / (f 0 (1 + δ)) <ΔS <Nf 1 / (f ₀ (1−δ)) Nf ₁ / (f ₀ (1 + δ)) <ΔR <Nf ₁ / (f ₀ (1−δ)) Next, for example, δ = 10 ppm (1
0 ⁻⁵ ), the transmission / reception relative frequency information difference signal 109Δ = ΔS−ΔR from the subtractor 17 is given by the following equation: −20 <Δ
<20. Therefore, in general, when the number is limited to | Δ | <n, it is necessary to set the number of K bits satisfying 2 ^K > 2n to ΔS and ΔR. Therefore, the required number of bits for the counter and the register is determined to be 6 bits. −2Nf ₁ δ / (f ₀ (1−δ ₂ )) <Δ <2Nf ₁ δ / (f ₀ (1−δ ₂ )) The remainder value to be transmitted and detected as ΔS on the transmission side and ΔR on the reception side Normal control can be performed by performing subtraction from the calculated remainder value.

The receiving side of the conventional example shown in FIG. 9 (b) shows that when power is first turned on at time t ₀ , for example, the transmission relative frequency information 105 input to the subtractor 17 is “00000 000”.
0 ”and the input pattern of the integration signal 110 is“ 00 010 ”.
When it is set to 0 ", the output control voltage becomes V ₁ in FIG. 10A showing the input / output characteristics of the second D / A converter 19,
FIG. 10B showing the frequency modulation sensitivity characteristic of the reception sampling clock generator 15, in which the output frequency deviation (δ) of the reception sampling clock 107 becomes 10 ppm and the input / output characteristic of the reception relative clock counting means 16. At 10 (c), the received relative frequency information 108 (ΔR) becomes “00 1010”. Here, the result of subtraction between the subtractor 17 and the integrator 18 is referred to as a second
When feedback control is performed on the D / A converter 19 of
In FIG. 10A, the control voltage signal 111 is controlled in the direction from V ₁ to V ₀ , and in FIG. 10B, the reception sampling clock 107 converges to δ = 0 ppm, and in FIG. 108 becomes ΔR = “00 0000”. Therefore, the transmission relative frequency information 105 of ΔS = “00 0000”
, And the transmission and reception sampling clock frequency is synchronized. Then the input pattern of the integration signal 110 when turning on the power again at time t _1, for example, "01 1100"
10A, the control voltage signal 111 becomes V ₂ in FIG. 10A, and the reception sampling clock 107 in FIG.
Becomes δ = 74 ppm, and in FIG. 10C, the reception relative frequency information 108 becomes ΔR = “00 1010”. Here, if feedback control is performed in the same manner as when δ = 10 ppm, the control voltage signal 111 becomes V _{2 in} FIG.
It is controlled to a pressurized et V ₀ direction, receiving the sampling clock 107 of the time V ₃ in FIG. 10 (b) converges to [delta] = 64 ppm, 10
In (c), the received relative frequency information 108 is ΔR = “00 0”
000 ". Accordingly, although the transmission relative frequency information 105 of ΔS =“ 00 0000 ”matches, the frequency deviation δ between the transmission and reception sampling clocks 103 and 107 is 0 ppm.
Since the clock frequency pull-in operation cannot be started, the transmission / reception sampling clock frequency becomes asynchronous and malfunctions.

[0006]

In the conventional transmission system clock synchronizer as described above, the transmission line clock frequency f ₁
A transmission sampling clock frequency f _s and controls the f _r as relative relationship information ΔS and ΔR between the reception sampling clock frequency f _r are the same, for any f ₁ f _s and f _r
Therefore, a clock frequency pull-in operation is started from a state in which a reception sampling clock outside the frequency deviation specification (for example, within ± 10 ppm) of a transmission sampling clock is output in a transient state (such as when power is turned on). However, there is a problem that the reception sampling clock cannot be reproduced only by the transmission relative frequency information ΔS determined by the frequency stability of the transmission sampling clock.

The problem to be solved by the present invention is to limit the oscillation control voltage on the receiving side by a transmission system clock synchronizer,
It is an object of the present invention to provide a method (control voltage limited transmission / reception sampling clock frequency synchronization method) in which the reception sampling clock starts the clock frequency pull-in operation within the frequency deviation standard of the transmission sampling clock even in a transient state.

[0008]

SUMMARY OF THE INVENTION A transmission system clock synchronizer according to the present invention matches transmission and reception relative frequency information between a transmission and reception sampling clock frequency detected at a transmission and reception side and an independent transmission line clock frequency. The reception sampling clock frequency is controlled so as to synchronize the transmission and the reception sampling clock frequency, and the following means are provided on the reception side to solve the above-mentioned problem, and the control voltage limiting transmission / reception sampling clock frequency is provided. It is characterized by adopting a synchronous system.

The reception sampling clock generator controls the oscillation frequency in accordance with the limited voltage signal from the control voltage limiting means and generates a desired reception sampling clock.

The reception relative clock counting means generates relative frequency information between the reception sampling clock from the reception sampling clock generator and the transmission line clock from the frame termination means for reproducing from a separately provided reception transmission frame signal.

The subtracter subtracts the received relative frequency information from the received relative clock counting means and the transmitted relative frequency information from the demultiplexer that demultiplexes the received transmission frame signal provided separately.

The integrator performs an integration operation on the difference signal from the subtractor.

The D / A converter performs D / A conversion on the integration signal from the integrator and outputs the result as a control voltage signal.

The control voltage limiting means limits the voltage division of the control voltage signal from the D / A converter, and feeds back the signal as a limited voltage signal.

[0015]

[0016]

The frequency monitoring means determines whether the voltage control signal from the D / A converter is high or low with respect to a preset positive / negative reference voltage or according to a reception sampling clock from a reception sampling clock generator. The significance of the received relative frequency information generated by counting the transmission clocks from the means is determined by the magnitude of a preset maximum / minimum reference value and is output to the self-propelled setting means as a control signal.

[0018]

The transmission system clock synchronizer of the present invention, on the receiving side, first reproduces a transmission clock from a transmission frame signal to be received, and transmits transmission relative frequency information (relative frequency information between a transmission sampling clock and an independent transmission clock). Demultiplex. Next, reception relative frequency information (relative frequency information between a reception sampling clock and an independent transmission clock) that counts and generates the transmission clock in accordance with a reception sampling clock generated by voltage-controlling the oscillation frequency and the transmission relative frequency information Is performed on the difference signal of. Further, the voltage control signal generated by performing the D / A conversion is subjected to a voltage division limit, or is set to zero only for an arbitrary time in a transient state or for a value outside a specified range, or is set in advance even when the value is an arbitrary value. And feed back to the reception sampling clock generation.

[0019]

1 is a block diagram of a transmission system clock synchronizer according to an embodiment of the present invention, except for the control voltage limiting means 20 on the transmission side and the reception side in FIGS. 1 (a) and 1 (b). This corresponds to FIG. 9 of the conventional example. The control voltage limiting means 20 is provided with a voltage divider composed of resistors R1 and R2, limits the control voltage signal 111 from the second D / A converter 19, and applies a control voltage to the reception sampling clock generator 15. The signal 112 is output.

The transmission system clock synchronizer of the above embodiment is
A method in which the oscillation control voltage on the receiving side is limited, and the reception sampling clock 107 starts the clock frequency pull-in operation within the frequency deviation standard of the transmission sampling clock 103 even in a transient state (control voltage limited transmission / reception sampling clock frequency synchronization method). ).

As shown in FIG. 1B, the control voltage limiting means 20 shows the input / output characteristics of the second D / A converter 19 when the frequency stability of the transmission sampling clock 103 is ± 10 ppm, for example. At 10 (a), the output control voltage is Vmax when the input pattern is "10 0000", and "01 0000".
At time Vmin = −Vmax, the output frequency deviation (δ) of the reception sampling clock 107 in FIG. 10B showing the frequency modulation sensitivity characteristic of the reception sampling clock generator 15 is δ = 0 ppm at the input control voltage V _0. , At ± V ₁ δ = ± 10 pp
When to be a m, R2 / (R1 + R2 ) = V 1 / V
The resistors R1 and R2 are set so as to satisfy max. In a transient state such as when the power is turned on, the limited voltage signal 112Vcont from the control voltage limiting unit 20 always outputs the second D signal.
Vcont ≦ | Vout | with respect to the control voltage signal 111Vout from the A / A converter 19, and the frequency sampling operation of the reception sampling clock 107 is started within the frequency deviation standard (± 10 ppm) of the transmission sampling clock 103. Thus, the transmission and reception sampling clock frequency can be reliably synchronized.

In the above embodiment, the integrated signal 110 from the integrator 18 is replaced with the control voltage limiting means 20 as shown in FIG.
On the other hand, according to the control signal 113 from the power-on reset pulse generator 22 which determines the logic level "L" to be significant for an arbitrary time from power-on, for example, a fixed pattern is used when significant, and the self-running is performed as it is when unintended. Self-propelled setting means 21 which outputs a signal 114 to the second D / A converter 19
May be provided. As shown in FIG. 3, the self-running setting means 21 applies a power-on reset pulse generator 22 to the integrated signal 110 from the integrator 18 using a plurality of AND circuits having the same number of bits as the transmission relative frequency information ΔS. Logic level “L” and “H” according to the significance / significance signal 113 from
The second D / A converter 19 is used as the self-running signal 114 with the fixed pattern “00 0000” as it is when the
Output to During the significant period, the second D / A in FIG.
The control voltage signal 111 from the converter 19 becomes V ₀ , and the reception sampling clock 107 from the reception sampling clock generator 15 becomes δ = 0 ppm in FIG. Since the frequency deviation δ of the reception sampling clock 107 is always set to 0 ppm in the transient state such as when the power is turned on and the clock frequency pull-in operation is started, the same effect as in the above embodiment is obtained.

Further, as shown in FIG. 4 in place of the power-on reset pulse generator 22 in the above-described embodiment, a predetermined positive / negative reference is given to the voltage control signal 111 from the second D / A converter 19. Depending on the level of the voltage, for example, logic level "L"
May be provided to the self-propelled setting unit 21 for outputting a control signal 115 for determining that the value is significant. As shown in FIG. 5, the frequency monitoring means 23 first supplies the second D / A converter 1
To voltage control signal 111 from the 9, compared with the reference voltage V ₁ and -V ₁ to preset the first and second analog comparator, and the high / low at the logical level "H" / "L" Significance of
An insignificant signal and an insignificant / significant signal of logic level "L" / "H" are output. Next, for the significant / insignificant signal and / or the significant / insignificant signal, a control signal 115 for determining the logical level “L” to be significant by a NOR operation (NOR gate) is output to the self-propelled setting means 21. I do. When the control voltage signal 111 from the second D / A converter 19 becomes an unspecified value in a transient state such as when the power is turned on, the frequency monitoring means 2
3 by the self-propelled setting means 21 according to the control signal 115 from “3”.
Since the self-propelled signal 114 of “0000” is output, FIG.
At 0 (a), the control voltage signal 111 from the second D / A converter 19 becomes V ₀ , and in FIG. 10 (b), the reception sampling clock 107 from the reception sampling clock generator 15 has δ = 0.
ppm. Therefore, the above embodiment has the same effect.

In the above embodiment, instead of the frequency monitoring means 23, as shown in FIG. 6, the reception clock for counting and generating the transmission clock 104 from the frame termination means 11 in accordance with the reception sampling clock 107 from the reception sampling clock generator. A frequency monitoring unit 23a may be provided which outputs a control signal 115 for determining, for example, a logical level “L” to be significant according to the relative value of the relative frequency information to a preset maximum / minimum reference value to the self-propelled setting unit 21. Good. As shown in FIG. 7, the frequency monitoring unit 23a first generates a received sampling clock 107 from the receiving sampling clock generator 15 by using a 1 / N divider.
/ N frequency-divided pulse, and the period N /
The reception relative frequency information [Delta] R = Nf ₁ / f _r of the line clock 104 counted by the counter to generate, including the f _r to capture output register. Next, a reference value ΔRmax set in advance by the first and second digital comparators with respect to the ΔR.
And ΔRmin, and the logical level “H”
/ Significant / insignificant signal of "L" and logic levels "L" and "H"
Is output. Further, for the significant / insignificant signal and / or the significant / insignificant signal, a control signal 115 for determining the logic level “L” as significant by the NOR gate is output to the self-propelled setting means 21. Even when the control voltage signal 111 from the second D / A converter 19 has an arbitrary value in a transient state such as when the power is turned on, the second D / A
The control voltage signal 111Vout from the A converter 19 is Vm
in ≦ Vout ≦ Vmax, and the frequency deviation δ of the reception sampling clock 107 is also −80 ppm ≦ δ ≦ 80p
Therefore, a 10-bit number is required to represent the reception relative frequency information ΔR within δ = ± 80 ppm in FIG. 8 showing the input / output characteristics of the reception relative frequency information generation part. Therefore, if a 10-bit counter, register, and first and second digital comparators are configured in FIG.
Can be detected from. The first and second digital comparators calculate the reference value as ΔRmax = “10 0100 1010”, Δ
Rmin is set to “100011 0110”, and δ is set to the standard value (± 10 pp) from the reception sampling clock generator 15.
When receiving sampling clock 107 exceeding m) is input,
The significant control signal 115 from the frequency monitoring unit 23a and the self-running signal 11 of “00 0000” from the self-running setting unit 21
4. The control voltage signal 1 of V ₀ from the second D / A converter 19
11, δ = 0 ppm from the reception sampling clock generator 15
, Respectively. When the received sampling clock 107 whose δ is within the standard value is input, the control signal 115 becomes an insignificant control signal 115 and the clock frequency pull-in operation is started again. Therefore, the same effect as in the above embodiment is obtained.

[0025]

According to the transmission system clock synchronizer of the present invention as described above, the oscillation control voltage on the receiving side is limited, and even in a transient state, the reception sampling clock is controlled within the frequency deviation standard of the transmission sampling clock. Since the method of starting the pull-in operation is adopted, the power supply is compared with the conventional method of simply controlling the reception sampling clock frequency so that the relative relationship information between the transmission line clock frequency and the transmission and reception sampling clock frequencies matches. The transmission sampling clock can be reliably reproduced on the receiving side even at the time of turning on, and there is an effect that a stable clock frequency pull-in operation without malfunction can be realized.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a transmission system clock synchronizer according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of another embodiment showing the present invention.

FIG. 3 is a functional block diagram of a self-propelled setting unit shown in FIG. 2;

FIG. 4 is a functional block diagram of another embodiment showing the present invention.

FIG. 5 is a functional block diagram of a frequency monitoring unit shown in FIG. 4;

FIG. 6 is a functional block diagram of another embodiment showing the present invention.

FIG. 7 is a functional block diagram of another frequency monitoring unit shown in FIG. 6;

FIG. 8 is a view for explaining input / output characteristics of a reception relative frequency information generation part shown in FIG. 7;

FIG. 9 is a functional block diagram of a conventional transmission system clock synchronizer and its transmission and reception relative clock counting means.

10 is a view for explaining input / output characteristics of the second D / A converter shown in FIG. 9, frequency modulation sensitivity characteristics of the reception sampling clock generator, and input / output characteristics of the reception relative clock counting means.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 A / D converter, 2 transmission buffer memory, 3 multiplex demultiplexer, 4 frame generation means, 5 transmission sampling clock generator, 6 transmission relative clock counting means, 11 frame termination means, 12 demultiplexer, 13 reception buffer Memory, 14 first D / A converter, 15 reception sampling clock generator, 16 reception relative clock counting means, 17
Subtractor, 18 integrator, 19 second D / A converter,
20 control voltage limiting means, 21 self-running setting means, 22 power-on reset pulse generator, 23, 23a frequency monitoring means, 101 transmission analog signal, 102 transmission frame signal, 103 transmission sampling clock, 104 transmission line clock, 105 transmission Relative frequency information, 106 received analog signal, 107 received sampling clock, 108
Reception relative frequency information, 109 transmission / reception relative frequency information difference signal, 110 integration signal, 111 control voltage signal,
112 limit voltage signal, 113 control signal, 114 free running signal, 115 control signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

(57) [Claims] 1. A receiving and sampling clock frequency controlled by a transmitting and receiving sampling clock frequency detected by a transmitting and receiving side and a transmission and receiving relative frequency information of an independent transmission line clock frequency so as to coincide with each other. And a transmission clock synchronizer for synchronizing the reception sampling clock frequency with the reception sampling clock for controlling the oscillation frequency in accordance with the limited voltage signal from the control voltage limiting means on the reception side and generating the desired reception sampling clock. A reception relative clock for generating the reception relative frequency information of a generator and the reception sampling clock from the reception sampling clock generator and the transmission line clock from the frame termination means for reproducing from a separately provided reception transmission frame signal; Counting means; and the reception provided separately from reception relative frequency information from the reception relative clock counting means. A subtracter that subtracts the transmission relative frequency information from a demultiplexer that demultiplexes the transmission frame signal; an integrator that performs an integration operation on the difference signal from the subtractor; D / A that performs D / A conversion on the integration signal and outputs the result as a control voltage signal
A transmission system clock synchronizer, comprising: a converter; and the control voltage limiting unit that limits a voltage division of a control voltage signal from the D / A converter and feeds back the voltage as the limited voltage signal. 2. A D / A converter in place of the control voltage limiting means .
Preset positive / negative reference for voltage control signal from
A frequency that outputs a control signal that determines the significance of the voltage
Number monitoring means, and self-running setting means for outputting a fixed pattern to the integrated signal from the integrator in accordance with the control signal when significant, and outputting the same as a self-running signal to the D / A converter when insignificant. transmission system according to claim 1, wherein black
Click synchronization device. 3. A maximum / minimum reference value set in advance with respect to reception relative frequency information generated and counted by a frequency monitoring means in accordance with a reception sampling clock from a reception sampling clock generator and a transmission clock from a frame termination means. 3. The transmission system clock synchronizer according to claim 2 , wherein a significance is determined according to the magnitude of the signal, and is output as a control signal to the free-running setting means.