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JP2997366B2 - Solar cell element - Google Patents
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JP2997366B2 - Solar cell element - Google Patents

Solar cell element

Info

Publication number
JP2997366B2
JP2997366B2 JP4138427A JP13842792A JP2997366B2 JP 2997366 B2 JP2997366 B2 JP 2997366B2 JP 4138427 A JP4138427 A JP 4138427A JP 13842792 A JP13842792 A JP 13842792A JP 2997366 B2 JP2997366 B2 JP 2997366B2
Authority
JP
Japan
Prior art keywords
region
silicon substrate
surface side
hole
solar cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4138427A
Other languages
Japanese (ja)
Other versions
JPH05335606A (en
Inventor
勝彦 白沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4138427A priority Critical patent/JP2997366B2/en
Publication of JPH05335606A publication Critical patent/JPH05335606A/en
Application granted granted Critical
Publication of JP2997366B2 publication Critical patent/JP2997366B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00Individual photovoltaic cells, e.g. solar cells
    • H10F10/10Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00Constructional details of devices covered by this subclass
    • H10F77/20Electrodes
    • H10F77/206Electrodes for devices having potential barriers
    • H10F77/211Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219Arrangements for electrodes of back-contact photovoltaic cells
    • H10F77/227Arrangements for electrodes of back-contact photovoltaic cells for emitter wrap-through [EWT] photovoltaic cells, e.g. interdigitated emitter-base back-contacts
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells

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  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は太陽電池素子に関し、特
にシリコン基板の裏面側のみに電極を形成した太陽電池
素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell device, and more particularly to a solar cell device having an electrode formed only on the back side of a silicon substrate.

【0002】[0002]

【従来の技術およびその問題点】太陽電池素子は、図3
に示すように、p型シリコン基板31内の一主面側にn
+ 領域32を形成してp−n接合部を形成し、このシリ
コン基板31の一主面側のn+ 領域32上と他の主面側
にそれぞれ電極33、34を形成したものが一般的であ
る。なお、図3中、35は反射防止膜である。ところ
が、このような太陽電池素子では、受光面側に電極33
があるために、この受光面側電極33によって入射光が
遮られて影によるロスが発生するとともに、この受光面
側電極33部や受光面側高濃度層32部分でキャリヤの
再結合損失が発生するという問題がある。
2. Description of the Related Art A solar cell device is shown in FIG.
As shown in FIG.
+ Region 32 is formed to form a pn junction, and electrodes 33 and 34 are formed on n + region 32 on one main surface side of silicon substrate 31 and on the other main surface side, respectively. It is. In FIG. 3, reference numeral 35 denotes an antireflection film. However, in such a solar cell element, the electrode 33 is provided on the light receiving surface side.
As a result, the incident light is blocked by the light receiving surface side electrode 33 and a loss due to shadow occurs, and a recombination loss of the carrier occurs in the light receiving surface side electrode 33 and the light receiving surface side high concentration layer 32 portion. There is a problem of doing.

【0003】そこで、受光面側の光影面積を減少させる
とともに受光面側電極部でのキャリヤの再結合を抑制す
るために、図4に示すように、全ての電極をシリコン基
板41の裏面側に配置した太陽電池素子も提案されてい
る。すなわち、p型シリコン基板41の一主面側には凹
凸部42と反射防止膜43だけを形成して、シリコン基
板41内の他の主面側にn+ 領域44とp+ 領域45を
形成し、このn+ 領域44部分とp+ 領域45部分と点
状に接触する電極46、47をそれぞれ形成したもので
ある。このように構成すると、シリコン基板41の受光
面側には電極がないことから光影面積はゼロになり、ま
た電極との接触面積を減少させることでキャリヤの再結
合も抑制できるようになる。
Therefore, in order to reduce the light shadow area on the light receiving surface side and to suppress the recombination of carriers at the light receiving surface side electrode portion, as shown in FIG. Arranged solar cell elements have also been proposed. That is, only the concave and convex portions 42 and the antireflection film 43 are formed on one main surface side of the p-type silicon substrate 41, and the n + region 44 and the p + region 45 are formed on the other main surface side in the silicon substrate 41. Then, the electrodes 46 and 47 are formed so as to be in point contact with the n + region 44 and the p + region 45, respectively. With this configuration, since there is no electrode on the light receiving surface side of the silicon substrate 41, the light shadow area becomes zero, and the recombination of carriers can be suppressed by reducing the contact area with the electrode.

【0004】ところが、この太陽電池素子では、シリコ
ン基板41の比抵抗が大きいと太陽電池素子を形成した
場合に直列抵抗が増大するとともに、表面再結合の影響
を大きく受け、効率が大きく低下するという問題があ
る。
However, in this solar cell element, if the silicon substrate 41 has a large specific resistance, the series resistance increases when the solar cell element is formed, and the efficiency is greatly reduced due to the influence of surface recombination. There's a problem.

【0005】そこで、図5に示すように、p型シリコン
基板51内に多数の貫通孔52を形成するとともに、こ
のシリコン基板51の受光面側と貫通孔52内にn+
域53を連続して形成し、裏面側のp+ 領域54と貫通
孔部分の裏面側のn+ 領域55部分にそれぞれ電極5
6、57を形成することによってシリコン基板51の受
光面側の光影面積を減少させるようにした太陽電池素子
も提案されている(例えば特開平1−51282号公報
参照)。このような貫通孔52は、例えばYAGレーザ
などによって形成されるが、シリコン基板51にYAG
レーザをスポット的に照射して貫通孔52を形成するの
は、煩雑で時間を要し、太陽電池素子が非常に高コスト
になるとともに、これらの貫通孔52の近傍にn+ 領域
を正確に形成するのが困難であり、製造歩留りも低下す
るという問題があった。なお、図5中、58はp型シリ
コン基板の受光面側に形成された反射防止膜である。
Therefore, as shown in FIG. 5, a large number of through holes 52 are formed in a p-type silicon substrate 51, and an n + region 53 is formed continuously with the light receiving surface side of the silicon substrate 51 and in the through hole 52. The electrode 5 is formed on each of the p + region 54 on the back side and the n + region 55 on the back side of the through hole.
A solar cell element in which the light-shading area on the light-receiving surface side of the silicon substrate 51 is reduced by forming the layers 6 and 57 has also been proposed (for example, see JP-A-1-51282). Such a through hole 52 is formed by, for example, a YAG laser or the like.
Forming the through-holes 52 by irradiating a laser in a spot-like manner is complicated and time-consuming, the cost of the solar cell element becomes extremely high, and the n + region is precisely formed in the vicinity of these through-holes 52. There is a problem that it is difficult to form and the production yield is reduced. In FIG. 5, reference numeral 58 denotes an antireflection film formed on the light receiving surface side of the p-type silicon substrate.

【0006】本発明は、このような従来技術の問題点に
鑑みて成されたものであり、光影面積による効率低下を
防止するとともに、キャリヤの再結合損失を防止した低
コストで高効率な太陽電池素子を提供することを目的と
するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and it is possible to prevent a reduction in efficiency due to a light-shading area and to prevent a recombination loss of a carrier, thereby realizing a low-cost and high-efficiency solar cell. It is an object to provide a battery element.

【0007】[0007]

【発明の構成】本発明によれば、受光面側に凹凸部を有
するp型シリコン基板内にライン状の貫通孔を設けると
ともに、このシリコン基板裏面側の前記貫通孔近傍にn
+ 領域を設け、このシリコン基板の受光面側から貫通孔
部分を経由して前記n+ 領域に繋がる電子の伝導領域を
前記シリコン基板内に設け、このシリコン基板の受光面
側と前記貫通孔内にパシベーション膜および反射防止膜
を設け、このシリコン基板裏面側の前記n+ 領域が形成
された部分以外の部分にp+ 領域を設け、前記n+ 領域
とp+ 領域上に電極を形成して成る太陽電池素子が提供
され、そのことにより上記目的が達成される。
According to the present invention, a linear through-hole is provided in a p-type silicon substrate having an uneven portion on the light-receiving surface side, and an n-type through hole is provided near the through-hole on the back surface of the silicon substrate.
+ Region is provided, and an electron conduction region connected to the n + region from the light receiving surface side of the silicon substrate via the through hole portion is provided in the silicon substrate, and the light receiving surface side of the silicon substrate and the through hole are provided. A passivation film and an antireflection film, a p + region is provided in a portion other than the portion where the n + region is formed on the back side of the silicon substrate, and electrodes are formed on the n + region and the p + region. Thus, the above object is achieved.

【0008】[0008]

【作用】上記のようにシリコン基板の受光面側には電極
が存在しないことから、光影損失とキャリヤの再結合損
失が減少する。さらに、シリコン基板の受光面側に凹凸
部を形成するとともに、シリコン基板内にライン状の貫
通孔を形成することによって、シリコン基板の表面積を
増大し、また貫通孔を形成するための時間が著しく低減
されてこの貫通孔とこの貫通孔の周辺のn+ 領域の形成
が容易になる。したがって、高効率の太陽電池素子を低
コストで製造歩留りを低下させることなく製造できるよ
うになる。
As described above, since there is no electrode on the light receiving surface side of the silicon substrate, light loss and carrier recombination loss are reduced. Furthermore, by forming an uneven portion on the light receiving surface side of the silicon substrate and forming a linear through hole in the silicon substrate, the surface area of the silicon substrate is increased, and the time required for forming the through hole is significantly increased. This facilitates formation of the through hole and the n + region around the through hole. Therefore, a highly efficient solar cell element can be manufactured at low cost without lowering the manufacturing yield.

【0009】[0009]

【実施例】以下、本発明を添付図面に基づき詳細に説明
する。図1は、本発明に係る太陽電池素子の一実施例を
示す斜視図であり、1は全体としてp型シリコン基板を
示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a perspective view showing one embodiment of a solar cell element according to the present invention, and 1 shows a p-type silicon substrate as a whole.

【0010】前記シリコン基板1は、例えばボロンなど
のp型不純物を含有させた0.4〜10Ω・cm程度の
比抵抗を有する厚み50〜200μm程度のシリコン基
板で構成される。このシリコン基板1は、引き上げ法な
どによって形成した単結晶シリコン基板でもよく、また
鋳造法などによって形成した多結晶シリコン基板でもよ
い。
The silicon substrate 1 is formed of a silicon substrate having a specific resistance of about 0.4 to 10 Ω · cm and a thickness of about 50 to 200 μm containing a p-type impurity such as boron. This silicon substrate 1 may be a single crystal silicon substrate formed by a pulling method or the like, or may be a polycrystalline silicon substrate formed by a casting method or the like.

【0011】前記シリコン基板1内には、ライン状の貫
通孔1aが形成されている。この貫通孔1aは、シリコ
ン基板1の表面積(受光面積)を増大させるとともに、
後述する少数キャリア(電子)をシリコン基板1の裏面
側に導くために形成される。このライン状の貫通孔1a
は、幅が30〜100μm程度で、長さがシリコン基板
1の両端部を残した長さに形成される。なお、この貫通
孔1aは、シリコン基板1の端部近傍から他の端部近傍
へ連続して形成する場合に限らず、断続的に形成しても
よい。また、この貫通孔1aは、シリコン基板1の表面
に対して垂直に形成する場合に限らず、シリコン基板1
の表面に対して一定の角度を持たせて形成することによ
り、入射光をシリコン基板1内に効率良く取り入れるよ
うにしてもよい。
In the silicon substrate 1, a linear through hole 1a is formed. This through hole 1a increases the surface area (light receiving area) of the silicon substrate 1 and
It is formed to guide a minority carrier (electron) described later to the back surface side of the silicon substrate 1. This line-shaped through hole 1a
Is formed to have a width of about 30 to 100 μm and a length excluding both ends of the silicon substrate 1. The through hole 1a is not limited to being formed continuously from the vicinity of one end of the silicon substrate 1 to the vicinity of another end, but may be formed intermittently. Further, this through hole 1a is not limited to the case where the through hole 1a is formed perpendicular to the surface of the silicon
The incident light may be efficiently taken into the silicon substrate 1 by forming it at a certain angle with respect to the surface.

【0012】前記シリコン基板1の受光面側には、テキ
スチャー処理によるピラミッド状凹凸部1bが形成され
ている。このピラミッド状凹凸部1bは、シリコン基板
1の表面での照射光の反射ロスを低減させるために形成
される。なお、ピラミッド状凹凸部に限らず、V字溝な
どを多数形成するようにしてもよい。シリコン基板1の
表面にV字溝を形成する場合は、フォトリソグラフィー
技術により水酸化ナトリウム溶液などで形成される。な
お、図1において、3はn+ 領域の電極、4はp+ 領域
の電極である。
On the light receiving surface side of the silicon substrate 1, a pyramid-shaped uneven portion 1b is formed by texture processing. The pyramid-shaped uneven portion 1b is formed to reduce the reflection loss of irradiation light on the surface of the silicon substrate 1. In addition, not only the pyramid-shaped uneven portion but also a large number of V-shaped grooves may be formed. When a V-shaped groove is formed on the surface of the silicon substrate 1, it is formed by a photolithography technique using a sodium hydroxide solution or the like. In FIG. 1, reference numeral 3 denotes an electrode in an n + region, and reference numeral 4 denotes an electrode in a p + region.

【0013】図2は、本発明に係る太陽電池素子の部分
断面図である。前記シリコン基板1内には、ライン状の
貫通孔1aが傾斜して形成されている。このシリコン基
板1の裏面側の貫通孔1aの近傍には、選択的にn+
域5が形成されている。このn+ 領域5は、リン(P)
や砒素(As)などの半導体用不純物を高濃度に含有し
ている。また、シリコン基板1の裏面側のn+ 領域5が
形成された部分以外の部分には、n+ 領域5部分から適
当な距離を隔ててBSF(裏面電界)層となるp+ 領域
6が形成されている。このp+ 領域6は、アルミニウム
元素などを高濃度に含有させて形成される。
FIG. 2 is a partial sectional view of a solar cell element according to the present invention. In the silicon substrate 1, a linear through hole 1a is formed to be inclined. An n + region 5 is selectively formed near the through hole 1a on the back surface side of the silicon substrate 1. This n + region 5 is made of phosphorus (P)
It contains semiconductor impurities such as arsenic and arsenic (As) at a high concentration. In a portion other than the portion where the n + region 5 is formed on the back surface side of the silicon substrate 1, ap + region 6 serving as a BSF (back surface electric field) layer is formed at an appropriate distance from the n + region 5 portion. Have been. This p + region 6 is formed by containing an aluminum element or the like at a high concentration.

【0014】前記シリコン基板1の受光面側および貫通
孔1a部分のシリコン基板1内には、電子の伝導領域7
などが形成される。この電子の伝導領域7は、n層、ヘ
テロ接合層、あるいは反転層などで構成され、裏面側に
形成されたn+ 領域5に接続されるように形成される。
すなわち、表面近傍で発生した電子・正孔を効率良く分
離し、シリコン基板1の表面へ導かれた電子をシリコン
基板1の裏面側に形成されたn+ 領域5へ導くためであ
る。電子の伝導領域7をn層で構成する場合は、シリコ
ン基板1の表面部分に、リン(P)や砒素(As)など
のn型半導体不純物を拡散すればよい。また、電子の伝
導領域7をヘテロ接合層で構成する場合は、例えばアモ
ルファスシリコンカーバイド層などをシリコン基板1の
表面に形成すればよい。さらに、電子の伝導領域7を反
転層で構成する場合は、シリコン基板1の表面に例えば
電荷密度が3×1011〜2×1013cm-2程度の窒化シ
リコン膜などで電子引付層8を形成すればよい。なお、
電子の伝導領域7をn層やヘテロ接合層で形成する場合
は、この電子引付層8は必ずしも必要ではない。
In the silicon substrate 1 at the light-receiving surface side of the silicon substrate 1 and the through hole 1a, an electron conduction region 7 is provided.
Are formed. The electron conduction region 7 includes an n layer, a heterojunction layer, an inversion layer, or the like, and is formed so as to be connected to the n + region 5 formed on the back surface side.
That is, it is for efficiently separating electrons and holes generated near the surface and guiding electrons guided to the front surface of the silicon substrate 1 to the n + region 5 formed on the back surface side of the silicon substrate 1. When the electron conduction region 7 is formed of an n-layer, an n-type semiconductor impurity such as phosphorus (P) or arsenic (As) may be diffused into the surface of the silicon substrate 1. When the electron conduction region 7 is formed of a heterojunction layer, for example, an amorphous silicon carbide layer or the like may be formed on the surface of the silicon substrate 1. Further, when the electron conduction region 7 is formed of an inversion layer, the electron attracting layer 8 is formed of, for example, a silicon nitride film having a charge density of about 3 × 10 11 to 2 × 10 13 cm −2 on the surface of the silicon substrate 1. May be formed. In addition,
When the electron conduction region 7 is formed of an n-layer or a heterojunction layer, the electron attracting layer 8 is not always necessary.

【0015】なお、前記シリコン基板1の貫通孔1a内
を含む表面側には酸化シリコン(SiOX )膜などから
成るパシベーション膜2が厚み50Å程度に形成されて
いる。また、図2中、9はフッ化マグネシウム層などか
ら成る反射防止膜である。さらに、シリコン基板1の裏
面側に形成されたn+ 領域5上には、n+ 領域5と点状
に接触するAlなどから成る電極3、およびp+ 領域6
と点状に接触するAlなどから成る電極4がそれぞれ形
成されている。なお、n+ 領域5の電極3とp+ 領域6
の電極4とは、シリコン基板1の裏面側の対向部でそれ
ぞれ合流するように櫛歯状に形成すればよい。また、こ
のn+ 領域5の電極3とp+ 領域6の電極4とは、BS
R(裏面側反射防止層)を兼ねるものである。
[0015] On the surface side including the through-hole 1a of the silicon substrate 1 is a passivation film 2 made of silicon oxide (SiO X) film is formed on a thickness of about 50 Å. In FIG. 2, reference numeral 9 denotes an antireflection film made of a magnesium fluoride layer or the like. Further, on n + region 5 formed on the back surface side of silicon substrate 1, electrode 3 made of Al or the like, which is in point contact with n + region 5, and p + region 6
And electrodes 4 made of Al or the like, which are in point contact with each other. The electrode 3 of the n + region 5 and the p + region 6
The electrode 4 may be formed in a comb-tooth shape so as to merge with each other at the opposing portions on the back surface side of the silicon substrate 1. The electrode 3 in the n + region 5 and the electrode 4 in the p + region 6 are
It also serves as R (backside antireflection layer).

【0016】上述のような太陽電池素子において、電子
の伝導領域7を反転層で構成する場合は、次のような工
程で形成される。まず、p型シリコン基板1をHClな
どで清浄化する。次に、10μm程度に絞られたYAG
レーザなどを用いてライン状の貫通孔1aを傾斜して形
成する。次に、ダメージ層を除去するために、弗酸・硝
酸の混合液などを用いてシリコン基板1の表面を軽くエ
ッチングする。次に、シリコン基板1の受光面側に、ピ
ラミッド状の凹凸部1bを形成する。このピラミッド状
凹凸部1bは、水酸化ナトリウム溶液などを用いたテキ
スチャー処理により形成される。次に、受光面と貫通孔
のn領域、裏面のn+ 領域、およびp+領域をイオン注
入法または熱拡散法により形成する。次に、酸化シリコ
ン膜などから成るパシベーション膜2をプラズマCVD
法あるいは熱酸化法により形成して、裏面側の所定部分
(n+ 領域とp+ 領域の電極を形成する部分)をエッチ
ング除去する。次に、n+ 領域5およびp+ 領域6上に
Alなどから成る電極3、4をスクリーン印刷法または
蒸着法により形成する。最後に、窒化シリコン膜などか
ら成る電子引付層8とフッ化マグネシウム膜などから成
る反射防止膜9をプラズマCVD法などで形成すること
により完成する。
In the above-described solar cell element, when the electron conduction region 7 is constituted by an inversion layer, it is formed by the following steps. First, the p-type silicon substrate 1 is cleaned with HCl or the like. Next, YAG narrowed down to about 10 μm
Using a laser or the like, the linear through hole 1a is formed to be inclined. Next, in order to remove the damaged layer, the surface of the silicon substrate 1 is lightly etched using a mixed solution of hydrofluoric acid and nitric acid. Next, a pyramid-shaped uneven portion 1b is formed on the light receiving surface side of the silicon substrate 1. The pyramid-shaped uneven portion 1b is formed by a texturing process using a sodium hydroxide solution or the like. Next, the light receiving surface and the n region of the through hole, the n + region on the back surface, and the p + region are formed by ion implantation or thermal diffusion. Next, a passivation film 2 made of a silicon oxide film or the like is formed by plasma CVD.
A predetermined portion on the rear surface side (portion for forming the n + region and p + region electrodes) is removed by etching or thermal oxidation. Next, electrodes 3 and 4 made of Al or the like are formed on n + region 5 and p + region 6 by screen printing or vapor deposition. Finally, an electron attracting layer 8 made of a silicon nitride film or the like and an antireflection film 9 made of a magnesium fluoride film or the like are formed by plasma CVD or the like.

【0017】[0017]

【発明の効果】以上のように、本発明に係る太陽電池素
子では、受光面側に凹凸部を有するp型シリコン基板内
にライン状の貫通孔を設けるとともに、このシリコン基
板裏面側の前記貫通孔近傍にn+ 領域を設け、このシリ
コン基板の受光面側から貫通孔部分を経由して前記n+
領域に繋がる電子の伝導領域を前記シリコン基板内に設
け、このシリコン基板の受光面側と前記貫通孔内にパシ
ベーション膜および反射防止膜を設け、このシリコン基
板裏面側の前記n+ 領域が形成された部分以外の部分に
+ 領域を設け、前記n+ 領域とp+ 領域上に電極を形
成して成ることから、シリコン基板の受光面側には電極
がなく、電極近傍でのキャリアの再結合損失が無くなる
とともに、シリコン基板の受光面側には、電子の伝導領
域が存在するので、効果的に集電ができ、従来の構成に
比較して安価に電圧・電流特性を向上させることができ
る。また、貫通孔をライン状にしたことから、この貫通
孔を形成するための時間が著しく低減され、この貫通孔
とこの貫通孔の周辺のn+ 領域の形成が容易になる。し
たがって、高効率の太陽電池素子を低コストで製造歩留
りを低下させることなく製造できるようになる。
As described above, in the solar cell element according to the present invention, a linear through-hole is provided in a p-type silicon substrate having an uneven portion on the light-receiving surface side, and the through-hole is formed on the back side of the silicon substrate. An n.sup. + Region is provided near the hole, and the n.sup. +
An electron conduction region connected to the region is provided in the silicon substrate, a passivation film and an antireflection film are provided on the light receiving surface side of the silicon substrate and the through hole, and the n + region on the back surface side of the silicon substrate is formed. Since the p + region is provided in a portion other than the portion described above, and electrodes are formed on the n + region and the p + region, there is no electrode on the light receiving surface side of the silicon substrate, and carrier reclamation near the electrode is not performed. In addition to eliminating coupling loss, there is an electron conduction region on the light-receiving surface side of the silicon substrate, so current can be collected effectively, and voltage and current characteristics can be improved at lower cost compared to conventional configurations. it can. Further, since the through hole is formed in a line shape, the time required for forming the through hole is significantly reduced, and the formation of the through hole and the n + region around the through hole is facilitated. Therefore, a highly efficient solar cell element can be manufactured at low cost without lowering the manufacturing yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る太陽電池素子の一実施例を示す斜
視図である。
FIG. 1 is a perspective view showing one embodiment of a solar cell element according to the present invention.

【図2】本発明に係る太陽電池素子の断面図である。FIG. 2 is a sectional view of a solar cell element according to the present invention.

【図3】従来の太陽電池素子を示す図である。FIG. 3 is a view showing a conventional solar cell element.

【図4】従来の他の太陽電池素子を示す図である。FIG. 4 is a view showing another conventional solar cell element.

【図5】従来のその他の太陽電池素子を示す図である。FIG. 5 is a view showing another conventional solar cell element.

【符号の説明】[Explanation of symbols]

1・・・p型シリコン基板、1a・・・貫通孔、1b・
・・凹凸部、2・・・パシベーション膜、3・・・n+
領域の電極、4・・・p+ 領域の電極、5・・・n+
域、6・・・p+ 領域、7・・・電子の伝導領域、9・
・・反射防止膜。
1 ... p-type silicon substrate, 1a ... through-hole, 1b.
..Uneven portions, 2 ... passivation film, 3 ... n +
, P + region, 5... N + region, 6... P + region, 7... Electron conduction region, 9.
..Anti-reflection film.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 受光面側に凹凸部を有するp型シリコン
基板内にライン状の貫通孔を設けるとともに、このシリ
コン基板裏面側の前記貫通孔近傍にn+ 領域を設け、こ
のシリコン基板の受光面側から貫通孔部分を経由して前
記n+ 領域に繋がる電子の伝導領域を前記シリコン基板
内に設け、このシリコン基板の受光面側と前記貫通孔内
にパシベーション膜および反射防止膜を設け、このシリ
コン基板裏面側の前記n+ 領域が形成された部分以外の
部分にp+ 領域を設け、前記n+領域とp+ 領域上に電
極を形成して成る太陽電池素子。
A linear through hole is provided in a p-type silicon substrate having an uneven portion on a light receiving surface side, and an n + region is provided near the through hole on the back surface side of the silicon substrate. The conduction region of electrons connected to the n + region from the surface side through the through hole portion is connected to the silicon substrate.
Provided within the passivation film and the antireflection film is provided between the light-receiving surface side of the silicon substrate in the through holes, the p + region provided in a portion other than the n + region is formed portion of the silicon substrate backside A solar cell element comprising electrodes formed on the n + region and the p + region.
JP4138427A 1992-05-29 1992-05-29 Solar cell element Expired - Fee Related JP2997366B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4138427A JP2997366B2 (en) 1992-05-29 1992-05-29 Solar cell element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4138427A JP2997366B2 (en) 1992-05-29 1992-05-29 Solar cell element

Publications (2)

Publication Number Publication Date
JPH05335606A JPH05335606A (en) 1993-12-17
JP2997366B2 true JP2997366B2 (en) 2000-01-11

Family

ID=15221717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4138427A Expired - Fee Related JP2997366B2 (en) 1992-05-29 1992-05-29 Solar cell element

Country Status (1)

Country Link
JP (1) JP2997366B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013014860A1 (en) * 2011-07-26 2015-02-23 パナソニック株式会社 Plasma processing apparatus and plasma processing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4440405B2 (en) * 2000-01-19 2010-03-24 三菱電機株式会社 Solar cell and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013014860A1 (en) * 2011-07-26 2015-02-23 パナソニック株式会社 Plasma processing apparatus and plasma processing method

Also Published As

Publication number Publication date
JPH05335606A (en) 1993-12-17

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