JP2998279B2 - Logic simulation equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation apparatus for handling detailed delays in consideration of individual signal propagation delays occurring in logic gates and wirings of logic circuits such as electronic computers, and more particularly to detecting event passing and glitches. Logic simulation device capable of

2. Description of the Related Art Logic simulators are widely used to verify logic circuits of electronic computers and various electronic devices. In recent years, with the increase in scale, complexity, and speed of these logic circuits, we have dealt with the detailed time delay of logic circuits.
There is a demand for a hardware logic simulator that has a function of detecting an event passing or glitch, canceling or changing an event, and capable of executing a logic simulation at high speed.

[0003]

2. Description of the Related Art FIG. 8 is a memory layout diagram for explaining a conventional example. FIG. 8A shows a memory arrangement relating to an event of a conventional example.

Conventionally, the time management memory and the event list memory are memory areas provided in a scheduler (see the embodiment of the present invention). The time management memory stores a value (τ) obtained by quantizing the delay time of a circuit element. ) Is stored as a unit at each relative time. The storage location (n, n + 1, n + 2,...) Of one event to be processed in the event list memory is stored. The event list memory includes a time link unit that links events and events to be processed at the same time. Conventionally, in order to detect an event passing or a glitch from a registered event and cancel or change the corresponding event, a method of searching for an event registered in the past for a target gate in an event list memory is used. Was. Therefore, in this configuration, it is necessary to trace all the events registered in the event list memory, and it takes a long time to search for the corresponding event, which is not suitable for a simulation of a device having a large number of circuits. In order to improve this, the memory arrangement shown in FIG. 8 (b), in which a gate management memory and a gate link unit are added, is used.

FIG. 8B shows a memory arrangement relating to another conventional event. The gate management memory indicates a storage position on the event list memory of an event of one preceding gate input to the gate indicated by the gate number, and a gate link at that position links an event of another preceding gate.

[0006] A method has been used in which an event is traced on a memory configured as described above in accordance with a gate link unit, an event is overtaken or a glitch is detected, and an event to be canceled or changed is found.

[0007]

As described above, according to the conventional method, all events registered in an event list memory are traced in order to find an event registered in the past for a target gate. Alternatively, since a gate management memory and a gate link unit are provided and events are traced according to the gate link unit, a large amount of memory and related hardware are required in the latter case, and in either case, only a long time is required for tracing. However, if processing such as canceling an event is required, more time is required to update the link. Therefore, there is a problem that the processing speed is reduced and the logic simulation including the event passing and the detection and processing of the glitch cannot be executed at a high speed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a hardware logic simulator having a function of detecting an event passing or glitch, canceling or changing an event, and capable of executing a logic simulation at high speed. And

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, in a logic simulation apparatus for evaluating an operation considering a delay time of a logic element constituting a logic circuit, reference numeral 2 denotes an input value of an input signal of a logic element to be evaluated based on given logic element information. Evaluating means for detecting an input signal that changes the output with respect to a change in the output, and using the change in the output value as an event, and specifying a time at which the event is enabled by a relative time corresponding to the delay time;
Reference numeral 5 denotes a schedule unit for registering an event from the evaluation unit 2 and sequentially outputting the registered event when a designated time has arrived. 61 denotes an event input from the schedule unit 5, and An overtaking detecting means for detecting an overtaking event in which an event for an input changed after the event for a changed input is output first and canceling an event relating to the target logical element and outputting the event; To detect an event that causes a glitch among events, and to selectively disable an event relating to the target logic element, or to output an event by replacing the output value of the event with a predetermined value. The detecting means 8 is an overtaking detecting means 61 and a glitch detecting means 62. Seeking logic element of the output destination of the logic elements of the target from the logic circuit based on the input event is an evaluation object determining means for determining the logic elements of the next evaluation.

[0010]

The evaluation means detects an input signal which changes the output due to the change in the input value of the logic element, designates the change in the output value as an event, and designates the time at which the event is activated based on the delay time. The schedule means 5 registers the events from the evaluation means 2 and sequentially outputs the events at designated times.
The overtaking detecting means 61 examines the event from the schedule means 5 and cancels the event in which the overtaking is detected, and the glitch detecting means 62 examines the event from the scheduling means 5 to invalidate the event that generates the glitch, or The output value of the event is replaced with a predetermined value, and the evaluation object determining means 8 obtains the output destination of the logic element based on the events from the overtaking detection means 61 and the glitch detection means 62, and outputs the logic element to be evaluated next. Decide.

[0011]

FIG. 4 is an explanatory diagram of event passing and glitch detection and processing. Fig. 4 (a) shows the logical product (AND)
Represents the model of the gate. A delay value indicating a delay time from when a signal is input to a circuit element to when the signal is output is represented by a quantized integer (called a unit). Generally, the delay when the signal changes from 0 to 1 (U delay) and the delay when the signal changes from 1 to 0 (D delay) are different. In this embodiment, U delay = 5 units, D delay = 2 units And

FIG. 4B is a timing chart showing an example in which an event is canceled because an event has passed. When input A changes from 0 to 1 at time 3,
After 5 unit hours, that is, at time 8, an event in which the output C changes from 0 to 1 is registered. Next, when the input B changes from 1 to 0 at time 4, an event in which the output C changes from 1 to 0 after 2 unit time, that is, at time 6, is registered. Actually, the output does not change because the input B changes from 1 to 0 before the influence of the change of the input A is transmitted. Therefore, in this case, the two registered events must be canceled.

FIG. 4C shows a case where a glitch, that is, a pulse having a time width shorter than the delay value of the element (for example, two units of the D delay of the AND gate) is logically generated. Such pulses usually do not often occur at the output, but may occur as noise or spikes. In such a case, an indefinite logical value X indicating neither a logical 0 nor a logical 1 is output to warn the possibility that noise may occur or a case where the pulse is erased in the simulation due to the type or property of the circuit at the subsequent stage. In this case, two modes are required.

FIG. 2 is a system configuration diagram showing an embodiment of the present invention. In the figure, event buffers 1a, 1b, 1c
Is a buffer for holding information of a gate to be evaluated at a certain time, and separates a 0-delay (when a delay such as a dot-OR directly connected to a gate output is considered to be zero) and a gate of one or more delays separately. And the processing is switched to the next time after the zero-delay gate disappears, and the simulation of the logic circuit in which the zero-delay and the unit-delay are mixed is efficiently performed without disturbing the flow of the pipeline. (For the event buffer, refer to the evaluation event buffer of Japanese Patent Application No. 02-104552 filed on April 20, 1990).

The evaluation pipeline 2a has information relating to the input signal of each gate (fan-in information) and a truth table for calculating the output value of the gate.
The gate is evaluated for the gate to be evaluated read from a, 1b, and 1c, and an event is output only when the output value can be changed. Events are the relative time (TIME) at which the value at which the gate output changes should be updated, the number of the processor sending the event (PENO), and the number of the evaluated gate (GNO).
), The changed new value of the evaluated gate output (NEWS)
And its old value (OLDS). If the delay time is 0 or 1 unit delay, it is sent to the subsequent stage, bypassing the scheduler 5a and the event check circuit 60.

The scheduler 5a stores an event of a plurality of units delayed as a result of evaluation by the evaluation pipeline 2a, delays the evaluated event by a designated time, and outputs the delayed event to the event check circuit 60 (scheduler 5a). For details, refer to the event schedule device of Japanese Patent Application No. 02-069437 filed on March 15, 1990).

The event check circuit 60 counts the events, compares the output values of the events, and the like by using a built-in processor, and controls the components constituting the event check circuit 60 to perform the functions of the present invention. That is, the event is canceled when the event after the delay has overtaken the event, and when a pulse (glitch) having a width smaller than the delay value of the gate is output, the event is set in accordance with a mode designated in advance. Either disappear or output an indefinite value X.

A first net status memory (hereinafter referred to as N
7a is the current output value of the gate (referred to as NSM) based on the output value of the event from the scheduler 5a.
Hold.

A first new event memory (hereinafter, NE)
4a, the output value of the gate is set to NSM7a at the next time.
Hold events temporarily to update to. Second net status memory (hereinafter referred to as NSMT) 7b
Temporarily stores the output value of the gate when evaluated by the evaluation pipeline 2a for control in the event check circuit 60 and for reference from the evaluation pipeline 2a (the storage content is referred to as NSMT). .

A second new event memory (hereinafter, NE)
4b temporarily stores an event to be updated to NSMT7b. Event transfer interface
ET) is an interface for exchanging events between processors when an event resulting from the change is to be processed by another simulator (processor).

A buffer (hereinafter referred to as BUF) 9a temporarily holds an event to be sent to the fan-out pipeline 8a. Fan-out pipeline 8a is BUF9a
From the events stored in the event buffer, the gate to which the gate is to be output (fan-out), that is, the gate to be processed next, is obtained and supplied to the event buffers 1a, 1b, 1c.

FIG. 3 is a block diagram showing an embodiment of the present invention, and is a block diagram showing details of the event check circuit 60 shown in FIG. The event input register 6i inputs and sets events (PENO, GNO, NEWS, OLDS) from the scheduler 5a when registering and checking events.

The event canceling unit 6c checks an event input from the scheduler, detects a glitch in accordance with the flowcharts shown in FIGS. 5, 6, and 7, and cancels an unnecessary event.

The event output register 6x outputs the event updated by the event check section 6c to the fan-out pipeline 8a via the BUF 9a. The event check memory (ECM) 6m is an event check unit 6c
Control data (MO
DE, EVCNT, MU, XO) is read out via the readout register 6r, and the control data to be updated is written via the write register 6w.

In MODE, when a glitch occurs in the output of the gate, the output is not changed (MODE = 0), an indefinite value X is output only during the period in which the glitch occurs (MODE = 1), or the output of the gate is changed to the next. Fixed at X until the change of
(MODE = 2) is a flag that specifies in advance for each gate. In this embodiment, for example, when the output value is expressed by 2 bits, the logic 0 is represented by 00, the logic 1 is represented by 11, and the indefinite value X is represented by 01 or 10.

The EVCNT counts the number of events for the gate. The value is incremented by 1 when an event is registered in the scheduler 5a, and decremented by 1 when the event is read out for checking.

When reading an event from the scheduler 5a, the MU sets "1" when an event is registered in multiple for the gate. XO is set to 1 when an event is output as X.

When the event output signal (EVOUT) is 1, it indicates that a valid event has been output, and when it is 0, there is no event, that is, the event is cancelled.
FIGS. 5, 6 and 7 are flowcharts of the embodiment of the present invention. FIG. 5 shows an operation for registering an event in the scheduler, and FIGS. 5 and 6 show an operation for reading and checking the event from the scheduler 5a.

An example of the event overtaking and glitch detection shown in FIGS. 4B and 4C is an event check circuit.
The operation of 60 will be described along the steps (Rn, Sn, Tn) of the flowcharts of FIGS.

(A) When canceling the event shown in FIG. 4 (b) Time 3 (see FIG. 5) R1: The input signal A changes from 0 to 1 (0/0).
The event is registered at time 8 (3 + 5), and NSMT is set to 1. The event check circuit 60 captures the event into the event input register 6i, reads out the R2: gate number (GNO) as an address to the ECM 6m,
EVCNT is counted up to 1 and R4: ECM6m EV
Write the incremented value of 1 to CNT. Time 4 (see FIG. 5) R1-R4: As in the case of time 3, an event that changes from 1 to 0 (denoted as 1/0) due to a change in the input of B is registered at time 6 (4 + 2). , NSMT are set to zero. EC
The M6m EVCNT is counted up to 2. Time 6 (See Fig. 6) S1: 1/0 event registered at time 4 is the scheduler 5a
And the event check circuit 60 sets the event in the event input register 6i. S2: The ECM 6m is read using the gate number (GNO) as an address. S3: MU = 0, and S4: (refer to FIG. 7) EVCNT = 2
Therefore, S5: MU is set to 1. S6: NSM ≠ OLDS ((NSM = 0, OLDS = 1), so S
8: Set EVOUT to 0 (no event output). T1: Count down EVCNT to 1. T2: The data updated in the above step is stored in the ECM. T3: Since EVOUT = 0, no event is output. Time 8 (see Fig. 6) S1: Event 0/1 registered at time 6 is the scheduler 5a
And the event check circuit 60 sets the event in the event input register 6i. S2: The ECM 6m is read using the gate number (GNO) as an address. Since S3: MU = 1 and S9: EVCNT = 1, S10: M
Let U be 0. Since S11: XO = 0 and S12: NSM = NSMT (= 0), S13: EVOUT is set to 0 (no event output). T1-T3: (See Fig. 7) As in the case of time 6, EVCN
T is counted down to 0, and the updated data is EC
Store it in M6m.

In this way, the registered event is 2
Both are canceled. (A) When MODE = 0 in FIG. 4 (c) Time 2 R1−R4: As in the case of time 3 in (A) above, the event of 0/1 is registered at time 7 due to the input change of signal A. And
NSMT is set to 1. EVCNT = 1. Time 6 R1-R4: Similarly, due to the input change of signal B, a 1/0 event is registered at time 8, NSMT is set to 0, and EVCN
Let T = 2. Time 7 (refer to FIG. 6) S1-S2: When the event of 0/1 is read from the scheduler 5a, the event check circuit 60 sets the event in the event input register 6i, and sets ENO to GNO as an address.
Read CM6m. S3: MU = 0 and S4: (refer to FIG. 7) EVCNT = 2
Therefore, S5: MU is set to 1. Since S6: NSM = OLDS (= 0) and S7: MODE = 0, S8: EVOUT is set to 0 (no event output). T1-T3: Count down EVCNT to 1 and store the updated data in ECM6m. Time 8 (see FIG. 6) S1-S2: When an event of 1/0 is read from the scheduler 5a, the event check circuit 60 sets the event in the event input register 6i, and sets E to the GNO as an address.
Read CM6m. Since S3: MU = 1 and S9: EVCNT = 1, S10: M
Let U be 0. Since S11: XO = 0 and S12: NSM = NSMT (= 0), S13: EVOUT is set to 0 (no event output). T1-T3: (See Fig. 7) EVCNT is counted down to 0, and the updated data is stored in ECM6m.

Therefore, if a glitch occurs when MODE = 0, the event is canceled as indicated by C1 in FIG. 4 (c). (C) Time of MODE = 1 in FIG. 4 (c) Time 2 Same as when MODE = 0. Time 6 Same as when MODE = 0. Time 7 (refer to FIG. 6) S1-S2: When the event of 0/1 is read from the scheduler 5a, the event check circuit 60 sets the event in the event input register 6i, and sets ENO to GNO as an address.
Read CM6m. S3: MU = 0, and S4: (refer to FIG. 7) EVCNT = 2
Therefore, S5: MU is set to 1. S6: NSM = OLDS (= 0) and S7: MODE = 1, so S14: input OLDS (that is, input the OLDS value of the event input register to the event output register) and NEWS X (event change from 0 to X occurs), S15: XO is set to 1, and S16: EVOUT is set to 1. T1-T3: Count down EVCNT to 1. T2: Store the updated data in ECM6m. T3: Event (PENO, GNO,
OLDS, NEWS) is output to the fan-out pipeline 8a via the BUF 9a together with EVOUT (= 1). Time 8 (refer to FIG. 6) S1-S2: When an event of 1/0 is read from the scheduler 5a, the event check circuit 60 sets the event in the event input register 6i, and sets ENO using GNO as an address.
Read CM6m. Since S3: MU = 1 and S9: EVCNT = 1, S10: M
Let U be 0. Since S11: XO = 1 and S17: MODE = 1, S18:
OLDS is set to X, NEWS and NSMT are set to 0 (event change from X to 0), S19: XO is set to 0, and S20: EVOUT is set to 1. T1-T3: (See Fig. 7) EVCNT is counted down to 0, the updated data is stored in the ECM, and the event (PENO, GNO, OLDS, NEWS) is output from the event output register to EVOUT.
(= 1) and output. Output an event.

Therefore, as shown by C2 in FIG. 4 (c), an indefinite value X is output only during the period when the glitch occurs. (D) When MODE = 2 in FIG. 4 (c) Time 2 Same as when MODE = 0. Time 6 Same as when MODE = 0. Time 7 Same as when MODE = 1. Time 8 (see FIG. 6) S1-S2: When an event of 1/0 is read from the scheduler 5a, the event check circuit 60 sets the event in the event input register 6i, and sets E to the GNO as an address.
Read CM6m. Since S3: MU = 1 and S9: EVCNT = 1, S10: M
Let U be 0. S11: Since XO = 1 and S17: MODE = 2, S21:
XO is set to 0, and S13: EVOUT is set to 0 (no event output). T1-T3: (See Fig. 7) EVCNT is counted down to 0, the updated data is stored in the ECM 6m, and the event (PENO, GNO, OLDS, NEWS) is output from the event output register 6x to the EV.
Output with OUT (= 1). Output an event.

Accordingly, as shown by C3 in FIG. 4C, the output is fixed at X until the next change occurs. As described above, in the present embodiment, the event link in the scheduler is traced every time the event is processed, and it is not necessary to change the event, so that the flow of the pipeline is not disturbed or blocked. The system is configured to efficiently detect event passing and glitches and perform processing.
In this embodiment, the time required for processing one event is determined by reading the event check memory (ECM6m),
It is a time to determine whether there is an event passing or a glitch and write the ECM6m based on the determination result.
Using a device with an appropriate speed for CM6m, read, judge,
By executing writing in one memory cycle, an event can be executed in one delay unit (1τ).

[0035]

As described above, the present invention is configured, so that every time an event is sequentially output from the schedule means based on the delay time specified according to the designated time, it is checked whether the event has passed or a glitch has occurred. Can be. Therefore, a logic simulation device can be realized with a small amount of hardware without requiring a large-capacity memory as shown in the conventional example, and an event check can be performed in the flow of event processing. Time is reduced. Therefore, detailed delay simulation including event overtaking and glitch detection / processing is performed.
There is an effect that it can be executed at high speed and economically.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a system configuration diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram showing an embodiment of the present invention.

FIG. 4 is an explanatory diagram of detection and processing of event passing and glitches

FIG. 5 is a flowchart (part 1) of the embodiment of the present invention.

FIG. 6 is a flowchart (part 2) of the embodiment of the present invention.

FIG. 7 is a flowchart (part 3) of the embodiment of the present invention.

FIG. 8 is a memory layout diagram illustrating a conventional example.

[Explanation of symbols]

 1a, 1b, 1c Event buffer 2 Evaluation means 2a Evaluation pipeline 4a First new event memory (NEM) 4b Second new event memory (NEMT) 5 Scheduling means 5a Scheduler 6c Event check section 6i Event input register 6m Event check Memory (ECM) 6r Read register 6w Write register 6x Event output register 7a First net status memory (NSM) 7b Second net status memory (NSMT) 8 Evaluation target determining means 8a Fan-out pipeline 9a Buffer (BUF) 60 Event check circuit 61 Overtaking detection means 62 Glitch detection means

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 G06F 11/25 G01R 31/28

Claims (2)

(57) [Claims] 1. A logic simulation device for evaluating an operation of a logic element constituting a logic circuit in consideration of a delay time, comprising: input signals of a logic element to be evaluated based on given logic element information Evaluation means for detecting an input signal that changes the output in response to a change in the value, and using the change in the output value as an event, and designating a time at which the event is enabled by a relative time corresponding to a delay time; A schedule means for registering an event from the system and sequentially outputting the registered event when a designated time arrives, an event input from the schedule means, and a possibility of occurrence of a glitch or An event for an input changed after an event for an input changed earlier is overtaken by an event that is output from the scheduling means first. A detection means for determining the presence or absence of teeth, the event is registered in the schedule means from said evaluating means
The count is incremented each time the
Count every time a detected event is processed by the detection means
Counting means for reducing the time, and an output value of an event from the scheduling means.
Storage means for storing the current output value of the circuit element, and when an event is output from the schedule means,
The value before the change of the output value of the event is stored in the storage means.
Comparing means for comparing the output value of the
If the difference between the increment and decrement of the counting by the counting means is 2 or more,
Condition that the comparison results by the comparing means are not equal
To detect an event overtaking, the difference is 2 or more and
Possibility of glitch occurrence on condition that the comparison results are equal
Detecting means for detecting the logic element to be output from the logic circuit based on the event input from the detecting means, and evaluating means determining means for determining the next logical element to be evaluated. A logic simulation device provided. 2. The delay time of a logic element constituting a logic circuit.
Is a logic circuit evaluation method that evaluates operation taking into account
Te, event a change in the output value with respect to the change of the input values to the logic element
Registered as an event with the time when the event is activated.
Count the events to be recorded and registered , store the current output value of the logic element, and change the registered event to the time when the event is activated.
And the event read from the registered event count value.
The number of events, and the change in the stored output value and the output event
Compares with the previous value and reads the number of registered events.
The difference in the number of events is 2 or more, and the comparison results are equal.
Under the condition that a glitch has occurred,
The condition that the minutes are 2 or more and the comparison results are not equal
Change after the event for the input that changed earlier.
Event for which the event for the converted input is output first
Of Logic Circuits that Detect Overtaking of Vehicles
Method.