JP2877005B2 - Logic simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method, and more particularly to a delay simulation method for designing a memory LSI (large-scale integrated circuit).

[0002]

2. Description of the Related Art Conventionally, in a logic simulation method, as shown in FIG. 8, when a change in an input signal of a logic element at a certain time of an input pattern 1 is observed (step S11 in FIG. 8), a predetermined truth value is obtained. The logic level of the output signal corresponding to the logic level of the new input signal is determined based on Table 11 (step S12 in FIG. 8).

Thereafter, the gate propagation delay time of the logic element is calculated according to the following equation: t _pd = t + R × CL (1) (step S1 in FIG. 8).
3, 14). In the equation (1), t _pd is a gate propagation delay time, t is a constant, R is an output resistance, and CL is an output load.

In a logic element that handles two or more input signals, the gate propagation delay changes depending on the combination of the logic levels of those input signals.
In addition, the accuracy of the gate propagation delay time t _pd is improved by appropriately calculating or selecting the output resistance R according to the combination of the logic levels of the input signals or selecting the output resistance R from Table 12 prepared in advance.

The output change based on the gate propagation delay time t _pd calculated by executing the processing in each of the above steps is reserved, and the logic simulation of the logic element is continued (step S15 in FIG. 8).

[0006]

In the above-described conventional logic simulation method, when a change in the input signal of the logic element is observed, the logic level of the output signal corresponding to the logic level of the new input signal is determined, and then the logic element is determined. Is calculated according to the equation (1), an output change based on the gate propagation delay time is reserved, and the logic simulation of the logic element is continued.

In recent years, the operating frequency of semiconductor products such as memory LSIs has tended to increase. However, as the operating frequency of semiconductor products has increased, the operating margin of internal circuits has been decreasing. As a result, in a situation where the operating frequency is high, the voltage amplitude of the wiring of the logic circuit is narrower than when the operating frequency is low, and it can be seen that the gate propagation delay time depends on the operating frequency.

However, the logic simulator according to the method described above requires that a single input signal change, that is, a gate propagation delay time of a logic element with respect to a certain input signal does not depend on a past change of the input signal. Since it is assumed that the gate propagation delay time depends on the operating frequency, the accuracy of the gate propagation delay time decreases.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a logic simulation method capable of improving the accuracy of the gate propagation delay time even under conditions where the gate propagation delay time depends on the operating frequency. Is to do.

[0010]

According to the logic simulation method of the present invention, a change in an input signal to a logic element occurs.
That the logic element has been
The time defined by the propagation delay time and the transition time of the output signal
Reserve a time interval, and within this time
Observe whether or not any changes occur, and make predictions when no new changes occur.
The reduced time is defined as the output change time of the logic element.
You.

Another logic simulation method according to the present invention is a logic simulation method for a logic element to which a plurality of input signals are inputted.
Input method whose level has changed first
Signal, and from the time of its change,
Fixed gate propagation delay time and output signal transition time
Are stored as temporary output transition information, and
If the level of another input signal changes within the
In this case, the provisional output transition information is corrected.

Another logic simulation method according to the present invention, in the above-described configuration , comprises a set of logic levels of an input signal.
Calculate the correction amount of the threshold value of the input signal from the
Of the gate propagation delay time based on the correction amount of the threshold value of
A positive amount is calculated.

[0013] Still another logic simulation method according to the present invention, in the above-described configuration , includes a method for analyzing at least a signal.
Including logic level and transition time and passing between the logic elements
The gate propagation delay time based on the information
I'm trying.

[0014]

According to the present invention, provisional output values are obtained by the drive capability corresponding to the input signal to the logic element, and when these provisional output values exceed a preset threshold value, the output change of the logic element is reserved.

At this time, when a logic level of at least one of the plurality of input signals is changed before a corresponding output is obtained after a plurality of input signals are input to the logic element, the plurality of input signals are changed. The gate propagation delay time corresponding to the input signal whose logical level has been changed among the plurality of input signals is corrected using the provisional output value for the first combination of the logical levels of each of the input signals.

Further, the variation of the threshold value is calculated by a parameter which affects the electrical characteristics of the basic element constituting the logic element, and the gate propagation delay time is corrected by the variation of the threshold value.

Further, the gate propagation delay time is corrected based on information including at least the logic level and transition time of the signal and transmitted and received between the logic elements.

As a result, the accuracy of the gate propagation delay time τ is improved even under conditions where the gate propagation delay time τ depends on the operating frequency.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a partial processing operation of the logic simulation method according to one embodiment of the present invention. A logic simulation method according to one embodiment of the present invention will be described with reference to FIG.

When a change is observed in the input signal of the logic element at a certain time of the input pattern 1 (step S in FIG. 1).
1) The logic level of the output signal corresponding to the logic level of the new input signal is determined based on the truth table 2 or the logic formula given in advance (step S2 in FIG. 1 ).

Next, parameters necessary for calculating the gate propagation delay time and the transition time of the output signal are obtained from the combination of the logic levels of the input signals by using parameter table 3 (FIG. 1 ).
Step S3).

This parameter table 3 is based on the fact that it is empirically known that the gate propagation delay time of CMOS logic elements and the like and the transition time of the output signal are proportional to the transition time of the input signal and the output load. Have been created.

That is, the gate propagation delay time is τ, the transition time of the output signal is t _{T (Y)} , and the transition time of the input signal is t
_{T (A, B),} when the output load and _{CL, ταt T (A, B} ) ταCL t T (Y) αt T (A, B) t T (Y) αCL ...... (2 It is empirically known that this relationship exists.

Using this, equation (2) is equalized, and τ = a1 + b1 × CL + c1 × tT _{(A, B)} tT _(Y) = a2 + b2 × CL + c2 × tT _{(A, B )} (2) Here, a1 and a2 are t _{T (A, B)}
, CL and proportional constants, b1 and b2 indicate coefficients relating to CL, and c1 and c2 indicate coefficients relating to tT _{(A, B)} . Parameter table 3 is a table of proportional constants a1, a2 and coefficients b1, b2, c1, c2 prepared in advance prior to the logic simulation based on the actually measured data.

The transition time of the input signal at this time is a value obtained by multiplying the time required for the transition width of the actually measured waveform to change from 10% to 90% of the total amplitude by 1.25. The gate propagation delay time τ is such that the transition width between the input signal and the output signal is 50% of the total amplitude.
% Time difference.

Here, the coefficients b 1,
Since b2 is inversely proportional to the drive capacity, these coefficients b
1 and b2 are values standardized by the drive capacity at the time of actual measurement. That is, assuming that the drive capacity at the time of actual measurement is β0 and the standardized coefficients are b1 'and b2', the normalized coefficients b1 'and b2' are b1 '= b1.times..beta.0 b2' = b2.times..beta.0 ... ... (4)

As a result, the logic simulator obtains τ = a1 +(B1 '/ β0)× CL + c1 × t_{T (A, B)}  t_{T (Y)}= A2 +(B2 '/ β0)× CL + c2 × t_{T (A, B)}  The signal including the transition time is reproduced by the equation (5). this
As a method of calculating the drive capability β0 at the time,
There are methods such as conversion from the register size and output resistance.

Next, the correction amount of the threshold value of the input signal is determined from the combination of the logic levels of the input signal with reference to the parameter table 4 (step S4 in FIG. 1). This correction amount is "0" when the threshold value of the input signal is equal to the bisecting point of the full amplitude, and "-1" and "+1" respectively when the threshold value is equal to both ends of the full amplitude. Value equivalent to the value.

The correction amount of the gate propagation delay time τ is as follows: Δτ = m × ΔV _TH × τ (6) Here, Δτ is a correction amount of the gate propagation delay time τ, ΔV _TH is a correction amount of the threshold value of the input signal, and m is “+1” or “−1” depending on the transition direction of the input signal.
Take the value of

A temporary output value (analog value) is calculated based on the values calculated in the above steps (step S in FIG. 1).
5). In this case, first, provisional output transition information due to a change in the past input signal is required, and therefore, the provisional output value calculated in the past and stored in the storage area 5 is used.

Assuming that the initial value of the temporary output value is Y0,
This initial value Y0 has a value of -1.0 to +1.0, similarly to the correction amount ΔV _TH of the threshold value of the input signal. Here, the time when the output signal starts to transition, the temporary output value at that time (Y1 = Y0) and the transition time tT _(Y1) are stored in the storage area 5 as a set in association with each other.

Using the stored set of values (temporary output transition information), the time when the temporary output value exceeds the threshold value of the output signal, that is, the time when the temporary output value becomes 0, is calculated. At this point, a change in the output signal is reserved (step S6 in FIG. 1), and the logic simulation is continued (step S7 in FIG. 1). In this state, if there is no new input signal change, the logical level of the output signal changes at the time when the output change is reserved.

FIG. 2 is a diagram for explaining a method of calculating a gate propagation delay according to one embodiment of the present invention. Time t ₄₀₂ and the output signal calculated output signal Y starts a transition when to change is observed from "0" to logic level "1" of the single input signal A in FIG Y starve A time point t ₄₀₃ exceeding the threshold is shown.

The time t at which the output signal Y starts transitioning
₄₀₂ is calculated by the following equation: t ₄₀₂ = t ₄₀₁ + [τ′−t _{T (Y1)} ] (7) Here, t ₄₀₁ is when the input signal A exceeds the threshold, that is, when the input signal A becomes 0.

The time point t ₄₀₃ at which the output signal Y exceeds the threshold value is calculated by the following equation: t ₄₀₃ = t ₄₀₂ + t _{T (Y1)} × (−m) × Y1 (8)

FIG. 3 is a diagram for explaining a method of calculating a gate propagation delay for a plurality of inputs according to one embodiment of the present invention. The case where a change in the logic level of a new input signal is observed before the change in the logic level of the output signal will be described with reference to FIG.

In this case, as in the above-described processing, temporary output transition information, that is, the time when the output signal starts transition and the transition time are stored by focusing only on the change of the new input signal. As a result, two sets of temporary output transition information are stored together with the first input signal change.

First, from the stored temporary output transition information, the one at which the output signal starts transitioning at the earliest time point is extracted, and from the time point t603, the second earliest transition start time is _calculated using the value of the transition time. provisional output value at time t ₆₀₄ Y2
And calculated from the expression Y2 = Y1 + m × (t 604 -t 603) / t T (Y1) ...... (9). After that, the calculated value is set as a new initial value, and the second earliest transition start time t ₆₀₄ and the transition time are stored as a set.

Based on the stored information, the time point t _{605 at} which the provisional output value exceeds the threshold value is calculated from the following formula: t ₆₀₅ = t ₆₀₄ + t _{T (Y2)} × (−m) × Y2 (10) .

As described above, the provisional output transition information is stored, and at the same time, the old information that is no longer necessary for the calculation of the provisional output value, that is, the time when Y + 2 × t _{T (Y)} is older than the present time, is stored. Discard the information shown.

As a result, the gate propagation delay time from the input signal B (τ _b = t ₆₀₆ −t ₆₀₂ ) is corrected by the influence of the input signal A (τ _c = t
₆₀₅ becomes the -t _602).

FIG. 4 is a diagram showing an example of the truth table 2 of FIG. In the figure, the truth table 2 stores the logic level of the output signal Y corresponding to the combination of the logic levels of the input signals A and B.

That is, the logic level of the input signal A is "0", and the logic level of the input signal B is "d" indicating any of "0", "1", and "x" indicating indefinite. In this case, the logic level of the output signal Y is "1", the logic level of the input signal A is "d", and the logic level of the input signal B is "0", the logic level of the output signal Y is "1".
Becomes

The logic level of the input signal A is "1".
When the logic level of the input signal B is "d", the logic level of the output signal Y is "d", the logic level of the input signal A is "d", and the logic level of the input signal B is "1". , The logic level of the output signal Y becomes “d”.

Further, the logic level of the input signal A is "1".
When the logic level of the input signal B is "1", the logic level of the output signal Y is "0", the logic level of the input signal A is "x", and the logic level of the input signal B is "x". , The logic level of the output signal Y also becomes “x”.

FIG. 5 is a diagram showing an example of the parameter table 3 of FIG. 1, FIG. 6 is a diagram showing an example of the parameter table 4 of FIG. 1, and FIG. 7 is a diagram for a plurality of inputs according to an embodiment of the present invention. FIG. 9 is a diagram illustrating a specific example of a method of calculating a gate propagation delay.
A method of calculating a gate propagation delay for a plurality of inputs will be specifically described with reference to FIGS.

Here, it is assumed that the input transition time is 0.5 ns, the time difference between the input signals A and B is 0.1 ns, the drive capability β 0 is 1, and the output load CL is 3. In this case, the transition time t _{T (A, B)} of the input signal is 0.5 / 2 = 0.25.

First, when the logic level of the input signal A changes from "1" to "0", the logic level of the input signal B remains "1". The parameter corresponding to the combination of the signal B with the logic level “1” is obtained from the parameter table 3.

In this case, a1 = 0.0694, b1 '=
0.0339, c1 = 0.1520, a2 = 0.027
8, b2 '= 0.0500, c3 = 0.3459 are taken out, and the gate propagation delay time .tau.1 and the transition time tT _{(Y1) of} the output signal are calculated from equation (5).

That is, the gate propagation delay time τ1 and the transition
Transfer time t_{T (Y1)}Τ1 = a1 +(B1 '/ β0)× CL + c1 × t_{T (A, B)}  = 0.0694 + (0.0339 / 1) × 3 + 0.1520 × 0.25 = 0.2091 t_{T (Y1)}= A2 +(B2 '/ β0)× CL + c2 × t_{T (A, B)}  = 0.0278 + (0.0500 / 1) × 3 + 0.3459 × 0.25 = 0.2642.

When the logic level of the input signal B also changes to "0" after the logic level of the input signal A changes to "0", the logic levels of the input signal A and the logic level of the input signal B change to "0". The parameter corresponding to the combination with “0” is obtained from the parameter table 3.

In this case, a1 = 0.0235, b1 '=
0.0190, c1 = 0.1883, a2 = 0.039
3, b2 '= 0.0216, c3 = 0.2973, and the gate propagation delay time .tau.2 and the output signal transition time tT _(Y2) are calculated from equation (5).

That is, the gate propagation delay time τ2 and the transition
Transfer time t_{T (Y2)}Τ2 = a1 +(B1 '/ β0) × CL + c1 × t_{T (A, B)}  = 0.0235 + (0.0190 / 1) × 3 + 0.1883 × 0.25 = 0.1275 t_{T (Y2)}= A2 +(B2 '/ β0)× CL + C2 × t_{T (A, B)}  = 0.0393 + (0.0216 / 1) × 3 + 0.2973 × 0.25 = 0.1784.

On the other hand, when the logic level of the input signal A changes from “1” to “0” and the logic level of the input signal B remains “1”, the correction amount ΔV _TH of the threshold value of the input signal is from the parameter table 4, [Delta] V so _TH = -0.003 is obtained, the gate propagation delay time after correction .tau.1 'is based on the equation (6), τ1' = τ1 + Δτ1 = τ1 + m × ΔV TH × τ1 = τ1 (1 + m × ΔV _TH ) (11)

Therefore, the corrected gate propagation delay time τ1
'Is obtained as follows: τ1' = τ1 (1 + m × ΔV _TH ) = 0.2091 × (1 + 1 × −0.003) = 0.2091 × 0.997 = 0.2084

When the logic level of the input signal B changes from "1" to "0" after the logic level of the input signal A changes from "1" to "0", the input signals A, B
Is considered to have changed from "1" to "0" at the same time, the correction amount ΔV _TH of the threshold value of the input signal is obtained from the parameter table 4 as ΔV _TH = 0.021. Therefore, the corrected gate propagation delay time τ 2 ′ is given by the following equation (11): τ 2 ′ = τ 2 (1 + m × ΔV _TH ) = 0.1275 × (1 + 1 × 0.021) = 0.275 × 1.021 = 0 .1301 are obtained.

Next, at the time point t1 at which the output signal Y starts transitioning due to the change of the input signal A, from the equation (7), t1 = tT _{(A, B)} + [τ1'-tT _(Y1) ] = 0.25+ [0.2084-0.2642] = 0.942 is obtained.

The time point t2 at which the output signal Y starts transitioning due to a change in the input signal B is given by the following equation (7): t2 = tT _{(A, B)} + [τ2'-tT _(Y2) ] = 0 .35+ [0.1301-0.1784] = 0.317. In this case, the time difference between the input signals A and B is 0.
1 ns, the transition time t due to the change of the input signal B
_{T (A, B)} is 0.35.

[0060] Further, the output value Y2 of the provisional in earlier transition start time point t2 at the second position from the equation (9), Y2 = Y1 + m × ( t 604 -t 603) / t T (Y1) = -1 + 1 × (0 .3017-0.1942) /0.2642=-0.5931. In this case, t ₆₀₃ = t 1 and t ₆₀₄ = t 1
t2.

Based on the values obtained from the above calculations, first, a time point ta (first output reservation) at which the temporary output value Y1 exceeds the threshold value is determined. Here, since ta = t ₄₀₃ ,
From the equation (8), the first output reservation ta is given by: ta = t ₄₀₂ + t _{T (Y1)} × (−m) × Y1 = 0.942 + 0.2642 × (−1) × (−1) = 0.4584 can get. In this case, t ₄₀₂ = t 1.

Further, a time point tb (second output reservation) at which the temporary output value Y2 exceeds the threshold value is obtained. Where tb
So = t _605, the output reservation tb second time from equation _{(10), tb = t 604 + t T} (Y2) × (-m) × Y2 = 0.3017 + 0.1784 × (-1) × (-0. 5931) = 0.4075. In this case, t ₆₀₄ = t 2.

Therefore, in FIG. 7, the input transition time =
When a logic simulation is performed under the conditions of 0.5 ns, the time difference between the input signals A and B = 0.1 ns, the driving capability β0 = 1, and the output load CL = 3, the output based on the transition start time of the input signal A As for the time of change, 0.4075 ns was obtained by the above calculation, whereas 0.40 ns was obtained for the actually measured data.

On the other hand, the conventional logic simulation method does not have means for calculating a provisional output value (analog value). It is common to adopt the slower one of them.

That is, in the input change as described above, the output change with respect to the input signal A is: output change time = transition time t _{T (A, B)} + gate propagation delay time τ = 0.25 + 0.2091 = 0.4591. The output change with respect to the input signal B is obtained as follows: output change time = transition time t _{T (A, B)} + gate propagation delay time τ = 0.35 + 0.2091 = 0.5991. In this case, the gate propagation delay times τ1 and τ2 calculated from the equation (5) are used as the gate propagation delay time τ.
Of these, the slower gate propagation delay time τ1 is used.

Therefore, in the conventional logic simulation method, the output change time is 0.5591 ns, which is 1.39 times the actually measured data (0.40 ns). On the other hand, in the embodiment of the present invention, the output change is 0.4075 ns, which is 1.02 times, and the output change reservation closer to the actually measured data can be made.

As described above, the input signals A and B to the logic element
Tentative output value Y1,
By determining Y2 and reserving the output change of the logic element when these provisional output values Y1 and Y2 exceed a preset threshold value, the condition that the gate propagation delay time τ depends on the operating frequency is obtained. Even below, the accuracy of the gate propagation delay time τ can be improved.

The present invention can further take the following aspects with respect to the description in the claims.

(1) When a change in an input signal to the logic element is observed in an input pattern to the logic element, a level of an output signal of the logic element is determined, and a gate propagation delay time of the logic element is calculated. A logic simulation apparatus for verifying the gate propagation delay time by executing a logic simulation after the execution of the logic simulation, wherein a means for obtaining a temporary output value based on an output drive capability corresponding to an input signal to the logic element; Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value.

(2) When a change in the input signal to the logic element is observed in the input pattern to the logic element, the level of the output signal of the logic element is determined, and the gate propagation delay time of the logic element is calculated. A logic simulation device that verifies the gate propagation delay time by executing a logic simulation after the execution of the logic simulation. Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value, and before a plurality of input signals are input to the logic element and the corresponding outputs are obtained. A first combination of logic levels of each of the plurality of input signals when a logic level of at least one of the plurality of input signals is changed; Logic simulation apparatus characterized by having a means for correcting the gate propagation delay time corresponding to an input signal the logic level is changed among the plurality of input signals using the output values of the provisional respect.

(3) When a change in an input signal to the logic element is observed in an input pattern to the logic element, a level of an output signal of the logic element is determined, and a gate propagation delay time of the logic element is calculated. A logic simulation apparatus for verifying the gate propagation delay time by executing a logic simulation after the execution of the logic simulation, wherein a means for obtaining a temporary output value based on an output drive capability corresponding to an input signal to the logic element; Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value, and the variation of the threshold value by a parameter which affects the electrical characteristics of the basic element constituting the logic element. And a means for correcting the gate propagation delay time by a change in the threshold value. Shon apparatus.

(4) When a change in an input signal to the logic element is observed in an input pattern to the logic element, a level of an output signal of the logic element is determined, and a gate propagation delay time of the logic element is calculated. A logic simulation apparatus for verifying the gate propagation delay time by executing a logic simulation after the execution of the logic simulation, wherein a means for obtaining a temporary output value based on an output drive capability corresponding to an input signal to the logic element; Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value, and before a plurality of input signals are input to the logic element and the corresponding outputs are obtained. A first combination of logic levels of each of the plurality of input signals when a logic level of at least one of the plurality of input signals is changed; Means for correcting a gate propagation delay time corresponding to the input signal whose logic level has been changed among the plurality of input signals using a provisional output value with respect to an electrical characteristic of a basic element constituting the logic element. A logic simulation apparatus comprising: means for calculating a change in the threshold value based on an influencing parameter; and means for correcting the gate propagation delay time based on the change in the threshold value.

(5) When a change in an input signal to the logic element is observed in an input pattern to the logic element, a level of an output signal of the logic element is determined, and a gate propagation delay time of the logic element is calculated. A logic simulation apparatus for verifying the gate propagation delay time by executing a logic simulation after the execution of the logic simulation, wherein a means for obtaining a temporary output value based on an output drive capability corresponding to an input signal to the logic element; Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value, based on information including at least a logic level and a transition time of a signal and transmitted and received between the logic elements. Means for correcting the gate propagation delay time.

(6) When a change in the input signal to the logic element is observed in the input pattern to the logic element, the level of the output signal of the logic element is determined, and the gate propagation delay time of the logic element is calculated. A logic simulation apparatus for verifying the gate propagation delay time by executing a logic simulation after the execution of the logic simulation, wherein a means for obtaining a temporary output value based on an output drive capability corresponding to an input signal to the logic element; Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value, and before the corresponding output is obtained after a plurality of input signals are input to the logic element. A first combination of logic levels of each of the plurality of input signals when a logic level of at least one of the plurality of input signals is changed; Means for correcting a gate propagation delay time corresponding to the input signal whose logical level has been changed among the plurality of input signals using a temporary output value for the input signal, and at least a logical level and a transition time of the signal, and Means for correcting the gate propagation delay time based on information exchanged between the elements.

(7) When a change in the input signal to the logic element is observed in the input pattern to the logic element, the level of the output signal of the logic element is determined, and the gate propagation delay time of the logic element is calculated. A logic simulation apparatus for verifying the gate propagation delay time by executing a logic simulation after the execution of the logic simulation, wherein a means for obtaining a temporary output value based on an output drive capability corresponding to an input signal to the logic element; Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value, and the variation of the threshold value by a parameter which affects the electrical characteristics of the basic element constituting the logic element. And a means for correcting the gate propagation delay time by changing the threshold value, and at least a logic level and a transition of the signal. Logic simulation apparatus characterized by having a means for correcting the gate propagation delay time based on information exchanged between include time and said logic element.

(8) When a change in an input signal to the logic element is observed in an input pattern to the logic element, a level of an output signal of the logic element is determined, and a gate propagation delay time of the logic element is calculated. A logic simulation apparatus for verifying the gate propagation delay time by executing a logic simulation after the execution of the logic simulation, wherein a means for obtaining a temporary output value based on an output drive capability corresponding to an input signal to the logic element; Means for changing the output of the logic element when the output value of the logic element exceeds a preset threshold value, and before the corresponding output is obtained after a plurality of input signals are input to the logic element. A first combination of logic levels of each of the plurality of input signals when a logic level of at least one of the plurality of input signals is changed; Means for correcting a gate propagation delay time corresponding to the input signal whose logic level has been changed among the plurality of input signals using a provisional output value with respect to electrical characteristics of a basic element constituting the logic element. Means for calculating the variation of the threshold value by an influencing parameter; means for correcting the gate propagation delay time by the variation of the threshold value; and at least a logic level and a transition time of a signal, and Means for correcting the gate propagation delay time based on information transmitted and received.

[0077]

As described above, according to the present invention, when a change in the input signal to the logic element is observed in the input pattern to the logic element, the level of the output signal of the logic element is determined and the logic element is determined. Calculating a gate propagation delay time and then performing a logic simulation to verify the gate propagation delay time, wherein a step of obtaining a temporary output value by an output drive capability corresponding to an input signal to the logic element; Changing the output of the logic element when the tentative output value exceeds a preset threshold value. There is an effect that the accuracy of the delay time can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a partial processing operation of a logic simulation method according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a method of calculating a gate propagation delay according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating a method of calculating a gate propagation delay for a plurality of inputs according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of a truth table of FIG. 1;

FIG. 5 is a diagram showing an example of a parameter table of FIG. 1;

FIG. 6 is a diagram showing an example of a parameter table of FIG. 1;

FIG. 7 is a diagram showing a specific example of a method of calculating a gate propagation delay for a plurality of inputs according to an embodiment of the present invention.

FIG. 8 is a flowchart showing a partial processing operation of the logic simulation method according to one embodiment of the present invention.

[Explanation of symbols]

1 Input pattern 2 Truth table 3, 4 Parameter table 5 Temporary output transition information storage area t ₄₀₁ Time when input signal A passes threshold value t ₄₀₂ Temporary output value Y transitions due to change in input signal A Time to start t ₄₀₃ Time when provisional output value Y passes the threshold value t ₆₀₁ Time when input signal A passes the threshold value t ₆₀₂ Time when input signal B passes the threshold value t ₆₀₃ Provisional output value Time t _{604 at} which Y starts a transition due to a change in input signal A t ₆₀₄ Time at which a tentative output value Y starts a transition due to a change in input signal B when there is no influence of input signal A t ₆₀₅ provisional output value Y starve the output value Y of the provisional is calculated at the time t ₆₀₇ input signal a that passes the threshold is changed if there is no influence of time t ₆₀₆ input signal a passing through the threshold Time at which the threshold is passed

Claims (3)

(57) [Claims] 1. A logic simulation method for a logic element to which a plurality of input signals are input, wherein the logic element detects a change in a first input signal and responds to an output drive capability of the logic element.
A time when the output signal exceeds an output threshold is obtained from a gate propagation delay time corresponding to the first input signal and a transition time of the output signal, which are set in advance, and stored as temporary output transition information. Setting, the level change of the second input signal occurs between the time of the change of the first input signal and the time when the output signal exceeds the output threshold, and the rate of change of the output signal waveform is reduced. When the time of the output signal exceeding the output threshold changes due to the change, a temporary output transition information is obtained from a gate propagation delay time according to the second input signal and a transition time of the output signal ,
Temporary output transition information corresponding to the first input signal and the
2 from the temporary output transition information corresponding to the input signal of
A logic simulation method comprising: generating a force signal; and changing a logic output of the logic element when the new output signal exceeds the output threshold. 2. The logic simulation method according to claim 1, wherein the first input signal and the second input signal are signals that change the output of the logic element in the same signal level direction. 3. A correction amount of a threshold value of the input signal is calculated from a combination of logic levels of the input signal, and a gate propagation delay time is corrected according to the input signal based on the correction amount of the threshold value. 2. The logic simulation method according to claim 1, wherein the quantity is calculated.