JP3034699B2 - Manufacturing method of MISFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and
SFET (Metal Insulator Semiconductor)
conductor Field Effect Tra
nsister) manufacturing method.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there are the following.

FIG. 11 shows such a conventional general N-type MOS.
FIG. 3 is a cross-sectional view of a transistor.

In FIG. 1, a P-type silicon substrate 51 is shown.
An N-type source and drain 52, a gate oxide film 53 and a field oxide film 55 are formed thereon, and a gate electrode 54 made of polycrystalline Si is formed on the gate oxide film 53. The insulating film for use 56 is formed.
Therefore, a contact hole is formed in the wiring isolation insulating film 56 by selective etching, and the wiring metal film 57 is wired.

One problem of the MOS transistor having such a structure is that the reliability of the gate oxide film 53 is deteriorated due to the dielectric breakdown.

FIG. 12 shows one method for examining the electric breakdown voltage characteristics of the gate oxide film 53. In FIG. A gate oxide film 62 is formed on the P-type substrate 61. As the gate oxide film 62, an oxide film having a thickness of 10 to 50 nm is generally used at present. Further, a polycrystalline Si gate electrode 63 is formed on the gate oxide film 62. In this investigation, in order to improve the sensitivity of the breakdown voltage, the area is much larger than that of a normal transistor, for example, 10 to 30 mm.
² is used.

In the structure thus manufactured, the terminal 64 is brought into contact with the gate electrode 63 and the breakdown voltage of the gate oxide film 62 is measured. As a measuring method at this time, the voltage at which the specified current flows is measured by the ammeter 66 by sequentially increasing the variable voltage source 65 from a low voltage.
Is determined to be the withstand voltage.

FIG. 13 shows the breakdown voltage distribution of the gate oxide film 62 at this time.
The area of the gate electrode 63 is 20 mm ² and the determination current is 4 μA / cm ² . The withstand voltage of the gate oxide film 62 is a low voltage group called A mode and a medium voltage B
A general breakdown voltage distribution is shown which is distributed separately into a mode group and a C mode group showing an intrinsic breakdown voltage of an oxide film.

[0009]

As described above, in a generally formed gate oxide film, a low breakdown voltage portion called an A mode or a B mode exists, so that the reliability is reduced. There is.

In order to prevent this defect, a voltage stress test is performed to remove the initial defect.
It could not be a complete preventive measure, and had cost problems.

The present invention eliminates the A-mode and B-mode defects of the gate oxide film withstand voltage described above and provides a highly reliable MIS.
An object of the present invention is to provide a method for manufacturing an FET.

[0012]

SUMMARY OF THE INVENTION The present invention, in order to achieve the above object, in the manufacturing method of [1] MISFET, MISFET
Growing the gate insulating film, charging the surface of the gate insulating film to a predetermined potential, and ionizing the solution.
And a step of growing a metal film for a gate electrode.

[2] Production of the MISFET according to the above [1]
In the fabrication method, the charge on the surface of the gate insulating film was rotated.
Insulating liquid while contacting the insulator with the gate insulating film
Rinsing with frictional force with insulator
It is.

[0014]

According to the present invention, as described above, MISFE
In the method of manufacturing T, in the step after the gate oxide film is grown, the surface of the gate oxide film is charged to a predetermined potential, and then washed with an ionized wet cleaning solution, and then a gate electrode is formed.

Therefore, particles that have been mechanically adhered or particles that have been adhered due to electrostatic force are completely removed, and polycrystalline Si as a gate electrode that grows on the gate oxide film becomes uniform. The breakdown voltage is improved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a MISFET showing an embodiment of the present invention.
5 is a manufacturing process flowchart of FIG.

First, a process prior to a gate film forming step such as an active step is performed, and a gate oxide film (SiO ₂ film) for improving a withstand voltage is grown, for example, to a thickness of 20 nm (step). Next, a charging treatment is performed with a brush scrub using pure water (step), and then a dip cleaning is performed with an ionized cleaning liquid, for example, a mixed liquid of sulfuric acid, hydrogen peroxide and pure water (step), A polycrystalline silicon gate electrode is formed (step), and POCl ₃
(Step), and thereafter, a wafer process is performed by a general process.

FIG. 2 is a diagram showing an example of a charging process for a gate oxide film according to an embodiment of the present invention. Here, an outline of an apparatus called a scrubber, which scrubs a conventionally used semiconductor wafer with a brush together with pure water and removes foreign matters adhering to the wafer surface, is shown.

First, the semiconductor wafer 1 that has completed the gate oxidation step is vacuum-sucked by a conductive spin chuck 2 and is rotated by a rotating shaft 3.
The surface of the semiconductor wafer 1 is brushed by a brush 5 attached to a rotary motor 4. At this time, it is assumed that the spin chuck 2 is connected to the GND potential. The brush 5 is swung from the center to the periphery of the semiconductor wafer 1 by the swing axis. Further, during and after the brush processing by the pure water nozzle 6, pure water is discharged to rinse the surface of the semiconductor wafer 1. At this time, static electricity is generated and charged on the surface of the gate oxide film by friction with pure water.

FIG. 3 is a diagram showing the relationship between the scrubbing time (second) of the gate oxide film and the charging voltage (V) at this time.

The scrub conditions are as follows: a 6-inch semiconductor wafer at a low pressure of about ^{2 to 4} kgf / cm ² ;
It was rinsed at pm. At this time, the oxide film of the semiconductor wafer 1 is negatively charged due to friction with pure water, that is, charged with electrons, gradually increases with the processing time, and shows a saturation characteristic at a certain value.

FIG. 4 shows the correlation between the saturation charging voltage and the gate oxide film thickness. The value proportional to the film thickness, that is, 12 MV,
/ Cm.

Further, FIG. 5 shows that when the gate oxide film thickness is 20 nm, the wafer rotation speed is increased from 1000 rpm to 3000 rpm.
It shows the charge amount with respect to the rinsing time when the rpm was changed to 6000 rpm. Wafer rotation speed 100
At 0 rpm, it takes about 400 seconds to show the saturation band voltage, while at 3000 rpm, it takes about 100 seconds,
At 6000 rpm, saturation can be as fast as 30 seconds.

As shown in FIG. 6, the combination of the pure water rinse and the brush scrub (marked with ○) shows the same value as the pure water rinse alone (marked with ▲). It can be seen that it was determined only by the friction of After a while
Cleaning solutions that are ionizing, such as sulfuric acid and hydrogen peroxide,
Dip-wash the mixed solution of pure water, rinse with pure water and spin dry. Thereafter, an electrode material, for example, polycrystalline S
growing an i film by thermal decomposition of SiH ₄ at about 600 ° C.
Further, polycrystalline Si is diffused by thermal diffusion of POCl ₃ or the like, and a gate electrode pattern is formed by photolithography and an etching technique. Thus, a MOSFET is manufactured.

FIGS. 7 to 9 show the M thus produced.
FIG. 9 is a diagram illustrating the withstand voltage of an OSFET 20 nm gate oxide film measured by changing the charging voltage during brush scrub.

FIG. 7 shows that the conditions for removing particles by a general brush scrub are as follows.
The total time of brush and pure water rinsing is about 30 seconds, and the charge amount on the oxide film at this time is -6V. Although the breakdown voltage distribution of the gate oxide film is slightly improved under these conditions, when the brush scrub is not performed, the characteristics are almost the same as those in FIG. 13 and the A mode and B mode failures are observed.

However, as shown in FIG. 8, the brush scrub and the pure water rinsing time are set to 4 times for the gate oxide film of 20 nm.
As a result, the A-mode and B-mode failures were greatly reduced, and the C-mode value, which is the intrinsic withstand voltage of the oxide film, was reduced in most areas. Is shown. Under this condition, as shown in FIG. 5, at a wafer rotation speed of 1000 rpm, a pure water rinse for about 400 seconds is required to show a saturated charged voltage, and the processing time is greatly increased. In addition, as shown in FIG. 5, at 3000 rpm, 100 seconds, 6000 rpm
At pm, a high-speed rotation of 30 seconds can reach a saturated charge amount in a short time.

FIG. 9 shows a MOSFET 20 nm according to the present invention.
This is a breakdown voltage distribution when the gate oxide film is rinsed with pure water at a wafer rotation speed of 6000 rpm for 30 seconds. As in FIG. 8, the A-mode and B-mode defects are eliminated and the intrinsic withstand voltage value of the C-mode is shown, and the withstand voltage is greatly improved.

On the other hand, after saturation charging in the same manner,
FIG. 10 shows a breakdown voltage distribution of a semiconductor wafer on which a polycrystalline Si film is directly grown in a charged state without washing with an ionized solution.

In the case of the wafer without cleaning with the ionized solution, although a slight A-mode and B-mode failure is observed, a significant improvement is observed as compared with the breakdown voltage distribution of FIG. 10 without the brush scrub.

It is conceivable from these results that particles adhering to the oxide film surface are completely removed by the brush scrub, and the factor of incomplete growth during subsequent polycrystalline Si growth is prevented. 8 and 9
As shown in the figure, the maximum charged voltage of the oxide film is 12 MV / cm.
This is consistent with the intrinsic voltage of the oxide film, which is generally said to be. In other words, electrons that are negative charges are charged on the surface of the gate oxide film, and when the friction between the gate oxide film and the pure water is further increased, the breakdown voltage of the oxide film becomes higher than the withstand voltage. It is considered that electric charges flow to Si of the substrate through the substrate. As described above, the entire surface has charges equal to the oxide film breakdown voltage, that is, electrons, and some of the oxide film surfaces have leaked charges and have no excess electrons, that is, the oxidation state. The electron distribution on the film surface is greatly different.

Generally, CVD film deposition by thermal decomposition
It is considered that the surface electrons are greatly involved, and the uneven distribution of the electron state on the surface immediately after the brush scrub is caused by polycrystalline S
It is considered that this appears as abnormal growth of i. In the gate oxide film and the polycrystalline Si having the structure thus grown,
The withstand voltage of the oxide film is degraded due to unevenness of the interface, thermal stress, and the like, resulting in A-mode failure.

On the other hand, if the charged state is dipped in the ionized cleaning liquid after the brush scrub, the charged electrons are released into the liquid and the charge is reduced. Also, particles that have mechanically adhered to the oxide film surface are removed by brush scrub, and particles that adhere to the surface due to electrostatic attraction force. It will be released from the oxide film surface.

As described above, the surface of the oxide film after the treatment with the brush scrub and the ionized cleaning liquid is in a very clean state without being charged with electrons.

When polycrystalline Si is grown in such a state, uniform polycrystalline Si growth is started on the surface of the oxide film, a stable polycrystalline Si oxide film interface is obtained, and good oxide film breakdown voltage is exhibited. Become like

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0038]

Effect of the Invention] As described above in detail, according to the present invention, after the charging of the gate insulating film of M ISFET, by washing with ionized solution, by particles or the electrostatic force which is mechanically attached Since the attached particles are completely removed and the polycrystalline Si as the gate electrode grown on the gate oxide film becomes uniform, the electric breakdown voltage of the gate oxide film is improved, and the initial yield and reliability of the MISFET are improved. Can be planned.

[Brief description of the drawings]

FIG. 1 is a manufacturing process flowchart of a MISFET showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a charging process of a gate oxide film according to the embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a scrub time of each gate oxide film and a charging voltage according to the embodiment of the present invention.

FIG. 4 is a diagram showing a correlation between a saturation charging voltage of a gate oxide film and a gate oxide film thickness showing an example of the present invention.

FIG. 5 is a graph showing the relationship between the number of rotations of the semiconductor wafer and the charging speed according to the embodiment of the present invention.

FIG. 6 is a graph showing a charging voltage characteristic obtained by a brush scrub and a pure water rinsing process according to an embodiment of the present invention.

FIG. 7 is a graph showing a MOSFET 20 nm gate oxide film breakdown voltage distribution characteristic (semiconductor wafer rotation speed 100) showing an embodiment of the present invention.
0 rpm, brush scrub for 30 seconds).

FIG. 8 shows a MOSFET 20 nm gate oxide film breakdown voltage distribution characteristic diagram (semiconductor wafer rotation speed 100) showing an embodiment of the present invention.
0 rpm, brush scrub 400 seconds).

FIG. 9 is a diagram showing a MOSFET 20 nm gate oxide film breakdown voltage distribution characteristic (semiconductor wafer rotation speed 600) showing an embodiment of the present invention.
0 rpm, brush scrub for 30 seconds).

FIG. 10 is an oxide film breakdown voltage distribution characteristic diagram showing an example of the present invention.

FIG. 11 is a cross-sectional view of a conventional general N-type MOS transistor.

FIG. 12 is a diagram showing a method for examining the electrical breakdown voltage characteristics of a gate oxide film.

FIG. 13 is a diagram showing a breakdown voltage distribution of a conventional gate oxide film.

[Explanation of symbols]

 Reference Signs List 1 semiconductor wafer 2 spin chuck 3 rotating shaft 4 rotating motor 5 brush 6 pure water nozzle

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57) [Claims] (A) growing a gate insulating film of a MISFET; (b) charging the surface of the gate insulating film to a predetermined potential; (c) washing in an ionized solution; d) a step of growing a metal film for a gate electrode. Wherein charging of the surface of the gate insulating film is rinsed with insulating liquid while contacting the rotated insulator on the gate insulating film, the production of MISFET of claim 1 Symbol placement performed by the frictional force between the insulator Method.