JP3064341B2 - Semiconductor element - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, particularly to a junction field effect transistor, and more particularly to a technique effective when applied to a low input capacitance junction field effect transistor.

[Conventional technology]

As one of semiconductor devices, a junction field effect transistor (JFET) is known. Regarding JFET, for example, "Transistor Classroom" published by Japan Broadcasting Publishing Association, Showa
It is described on pages 106 to 114 issued on December 1, 1944.

Japanese Patent Application No. 55-182008 discloses a junction field effect transistor having a bar gate structure. As shown in FIG. 10, the JFET having the bar gate structure is formed of an epitaxial layer provided on the main surface of a p ^{+ type} substrate 1 made of, for example, silicon and surrounded by ap ^{+ type} isolation region 2. The n-type island 3 is formed. The n-type island 3 is short as shown in FIG. Then, two rod-shaped gate (G) regions 4 are provided on the surface layer of the n-type island 3 so as to divide the n-type island 3 into three. This gate region 4
As shown in FIG. 10, the surface layer of the n-type island 3 is constituted by a p ^{+ -type} layer formed by implanting impurities into the surface, and both ends thereof are formed as shown in FIG.
Deviating from the n-type island 3 and reaching the p ^{+ -type} isolation region 2. As a result, the gate region 4 is electrically connected to the p ^{+ type} substrate 1. A drain (D) region 5 is provided between (inside) the two gate regions 4.
Are provided, and a source (S) region 6 is provided outside each gate region 4. As shown in FIG. 10, the drain region 5 and the source region 6 are formed by an n ^{+ -type} layer formed by implanting impurities into the surface of the n-type island 3.

On the other hand, a drain electrode 7 is provided on the drain region 5.
A source electrode 8 is provided on the source region 6, and a gate electrode (not shown) is provided on the surface of the p ^{+ type} substrate 1. In the figure, 10 and 11 are insulating films (oxide films)
It is.

The technology relating to the junction type field effect transistor is also disclosed in JP-A-55-74183, JP-A-58-215075, JP-A-60-25273, and JP-A-61-101082. ing.

[Problems to be solved by the invention]

JFET is used for the preamplifier of the video camera. JFETs for video camera preamplifiers are required to have low input capacitance and high transconductance characteristics in order to reduce noise in video camera preamplifier sets. JFET
Figure of merit [mutual conductance (g _m ) / input capacitance (C
_iss )]], the most effective means is to shorten the gate length (L _g ).

On the other hand, as described above, the JFET has an upper gate region 4 of p ⁺
It is electrically connected to the p ^{+ type} substrate 1 via the type isolation region 2. The gate region 4 is formed by selectively removing the insulating film by photoetching and diffusing impurities into the semiconductor surface exposed by removing the insulating film. However, in the conventional structure, when the gate length L _g is reduced, for example, the gate length L _g varies from about 2 μm to the formation of the end portion of the gate, and the end of the gate region 4 becomes p ⁺
The present inventor has clarified that a defect that does not reach the isolation region 2 occurs. That is, in the conventional JFET, after a thick insulating film is partially formed on the surface of the epitaxial layer provided on the main surface of the p ^{+ type} substrate 1,
Using this thick insulating film as a mask, ap ^{+ -type} isolation region 2 is formed to form an n-type island 3. And
In forming the gate region 4, after forming an insulating film again on the main surface side of the p ^{+ type} substrate 1, a photoresist is applied,
The photoresist layer is exposed to a desired pattern and developed to form an etching mask, and the insulating film is selectively removed using the etching mask as a mask. By the way, since the insulating film remains at the time of isolation formation, a step 13 is generated at a portion substantially along the periphery of the island. Photoresist layer on the insulating film which has such a step 13 is becomes thicker at the step portion, the gate length L _g is 2.0μm or less, will cause poor resolution, in the portion corresponding to the edge of the gate Etching may not be possible. In addition, if the exposure time is lengthened, the gate length becomes thicker than the designed value due to excessive exposure.

An object of the present invention is to provide a semiconductor device having a junction field-effect transistor that can achieve miniaturization of a gate length even in a JFET having a structure in which a step exists on the main surface side of a semiconductor substrate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, in the JFET of the present invention, in the gate region formed by impurity diffusion in the surface layer portion of the semiconductor substrate,
The gate length of the gate end portion corresponding to the step portion of the insulating film provided on the main surface side of the semiconductor substrate is longer than other gate portions.

This gate is formed, for example, on an island made of an epitaxial layer provided on the surface layer of the semiconductor substrate, and extends both ends of the island into the isolation region of the same conductivity type as the semiconductor substrate surrounding the island. In this case, the gate may be formed so as to be electrically connected to the semiconductor substrate and to have a longer gate length at a portion including a region corresponding to the periphery of the island than at other portions. In addition, the step around the insulating film provided on the surface of the island may be formed so as to overlap without deviating from a region where the gate length of the gate is longer than other portions.

[Action]

As described above, since the gate length of the JFET of the present invention is as short as 1 μm or less, the figure of merit is improved. Although the gate length of this JFET is short, the end of the gate corresponding to the step portion of the insulating film has a long gate length. Even if the photoresist layer at the portion corresponding to the step portion of the film becomes thicker, since the exposure and phenomenon are performed reliably, the etching pattern for forming the gate region is reliably formed, so the gate Such that the end portions are not electrically connected to the isolation region having the same conductivity type does not occur, and the yield is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a main part of a semiconductor device constituting a JFET according to one embodiment of the present invention, FIG. 2 is a sectional view taken along the line II-II of FIG. 1, and FIG. FIGS. 4 to 9 are cross-sectional views taken along the line III-III. FIGS. 4 to 9 are views showing steps of manufacturing the JFET according to the present invention. FIG. 4 is a cross-sectional view showing a part of the semiconductor substrate. FIG. 6 is a cross-sectional view of a semiconductor substrate on which a shaped island and an etching for forming a gate are formed, FIG. 6 is a partial plan view showing an etching pattern for forming a gate, and FIG. FIG. 8 is a sectional view of a semiconductor substrate on which a source region and a drain region are formed, and FIG. 9 is a sectional view of a semiconductor substrate on which a source electrode and a drain electrode are formed.

A semiconductor device according to the present invention, that is, a semiconductor device having a junction field effect transistor (JFET), has a substantially rectangular shape as shown in FIG. 1 and FIG. JF
As shown in FIG. 2, the ET includes a p ⁺ type substrate 1 made of p ⁺ type (first conductivity type) silicon and an n type (second type) provided on the main surface of the p ^{+ type} substrate 1. Conductive type) epitaxial layer 12
It is formed by utilizing. In this example, the p ^{+ -type} substrate 1 itself or the semiconductor substrate including the epitaxial layer 12 is referred to as a semiconductor substrate. The periphery of this semiconductor element is a p ^{+ -type} isolation region 2, the bottom of which reaches the p ^{+ -type} substrate 1. Therefore, a region in which the surrounded by the p ⁺ -type isolation region 2 constitutes the n-type island 3 to be opposite conductivity type to the p ⁺ -type isolation region 2 and the p ⁺ -type substrate 1.
The n-type island 3 is a region surrounded by a frame indicated by a two-dot chain line extending along the inside of a rectangular frame indicated by a chain line in FIG. In FIG. 1, the passivation film on the surface is omitted.

On the other hand, as shown in FIG. 1, two rod-shaped gate (G) regions 4 composed of p ^{+ -type} regions are provided in the surface layer portion of the n-type island 3, and both gate regions 4 are formed. Outside the source (S) region 6 parallel to the gate region 4.
Are provided, and one drain (D) region 5 is provided between the two gate regions 4. The drain region 5 and the source region 6 are composed of n ⁺ -type regions, and are provided in the n-type island 3 without reaching the p ^{+ -type} isolation region 2 around the n-type island 3. As shown in FIG. 3, both ends of the two gate regions 4 are separated from the n-type island 3 and reach the p ^{+ -type} isolation region 2.

This is one of the features of the present invention. FIG. 1 shows an end portion of the gate region (gate) 4, that is, the boundary between the n-type islands 3 and the boundary between the n-type islands 3. In a certain length region intersecting the step 13 shown by a dashed line, the gate length _Lg is longer. In this example, the gate length L _g of the gate region 4 extending between the drain region 5 and the source region 6, in order to improve the performance index, for example, a 1μm or less, a region where a gate length is longer, that is, the length The gate length of the gate portion 14 is selected such that the patterning for forming the gate region is ensured even with respect to the variation in the thickness of the photoresist layer in the photolithography, and is, for example, 3 to 4 μm.

On the other hand, the principal surface side of the p ^{+ type} substrate 1, to be exact,
On the surface of the epitaxial layer 12, an insulating film 15 is provided. The insulating film 15 is thicker at the portion corresponding to the n-type island 3 and thinner at the portion corresponding to the p ^{+ -type} isolation region 2, and has a boundary of about 4000 °.
It is 13. Also, a thin insulating film extends on the surface of the gate region 4. The reason that the thickness of the insulating film 15 differs in each part is that several degrees of the insulating film are formed in the manufacturing process. The insulating film 15 is partially removed, and a drain electrode 7 and a source electrode 8 made of aluminum are provided on the drain region 5 and the source region 6 exposed by the removal.
These drain electrodes 7 and the source electrode 8, as shown in Figure 1, extend to over the p ⁺ -type isolation region 2, and a circular bonding pad 20 and 21 on the p ⁺ -type isolation region 2 Is composed. The surface of the semiconductor element other than the bonding pads 20 and 21 is covered with a passivation film 22 made of an insulating film. On the back surface of the semiconductor element, that is, on the surface of the p ^{+ type} substrate 1, a gate electrode 23 made of an Au-based electrode is provided.

Next, a method of manufacturing a semiconductor device having a JFET will be described with reference to FIGS. Note that only a single semiconductor element portion is shown for explanation.

First, as shown in FIG. 4, ap ⁺ type substrate 1 made of p ⁺ type (first conductivity type) silicon having a thickness of about 360 μm is prepared. This p ^{+ type} substrate 1 has a specific resistance of 0.01 Ω-cm
At the same time, an epitaxial layer 12 having a thickness of about 1 to 4 μm is formed on the main surface (upper surface). The epitaxial layer 12 is an n-type layer having an impurity concentration of about 2 × 10 ¹⁶ cm ⁻³ . Therefore, the insulating film 15a is partially formed on the main surface side of the semiconductor substrate, strictly speaking, on the surface side of the epitaxial layer 12 by surface oxidation and photolithography. This insulating film 15a is made of a SiO ₂ film and has a thickness of 6000 mm.
It is about the thickness.

Next, as shown in FIG. 5, implantation of boron (B) a high concentration as an impurity, reaching the p ⁺ -type substrate 1 p ⁺
A shaped isolation region 2 is formed. As a result, a rectangular n-type island 3 is formed as shown in FIG. The p ^{+ -type} isolation region 2 has an impurity concentration of 10 ¹⁸ cm ⁻³ . Thereafter, as shown in FIG. 5, p ⁺
An oxide film is formed on the main surface side of the substrate 1, and the surface of the p ^{+ -type} isolation region 2 is also covered with an insulating film 15b of about 2000 °. Further, the insulating films 15a and 15b are selectively removed by a conventional photoetching technique, and holes 25 for implanting impurities are formed as shown in FIG. That is, as shown in FIG. 5, a photoresist is applied to the main surface of the p ^{+ -type} substrate 1 to form a photoresist 26, and the photoresist 26 is exposed (exposed) to a desired pattern and developed. The insulating film 15 is selectively etched using the photoresist 26 after development as an etching mask to form the holes 25. Two such holes 25, in other words, gate hole patterns 25 are provided in parallel so as to cross the n-type island 3.

In FIG. 6, a region indicated by a two-dot chain line between the two gate hole patterns 25 is a drain region 5 formed in a later step, and is drawn outside the gate hole pattern 25, respectively. The region indicated by the two-dot chain line is the source region 6 formed in a later step as described above. Therefore, the width direction of the gate hole pattern 25 is corresponds to approximately the gate length, the width L _a gate hole pattern 25 in this example has a 1μm weak about. Also, JFET
Has its ends it is necessary to connect the gate p ⁺ -type substrate 1 and electrically, the gate to the p ⁺ -type isolation region 2 having the same conductivity type as p ⁺ -type substrate 1 surrounding the n-type island 3 Are formed to overlap. However, when the gate hole pattern 25 is separated from the n-type island 3 and reaches the p ^{+ -type} isolation region 2 with the same width, the boundary between the 15a and 15b in the insulating film 15 is formed. Since the level difference 13 is as large as about 4000 °, the photoresist layer 26 at the level difference 13 becomes thicker, which causes insufficient exposure (photosensitivity), and the edge portion of the gate hole pattern 25 is often not accurately formed even when developed. Become. In other words, the pattern is too thin, and the insulation film
The bottom portion of 15 is not removed by etching, and the gate hole pattern 25 for exposing the surface of the p ^{+ -type} isolation region 2 is not formed.

Accordingly, in the present invention, as shown in FIG. This wide part
Region across said stepped 13 27, i.e., provided so as to extend over the length region the photoresist layer 26 becomes thicker, the width L becomes longer than the width L _a, for example, 3
It is 4 μm. Thereby, even if the photoresist layer 26 becomes thick near the step 13, both ends of the gate hole pattern 25 formed by exposure and development surely reach the p ^{+ -type} isolation region 2, and the p ⁺ The surface of the isolation region 2 is also accurately exposed.

Next, a thickness of 1000 mm is formed at the bottom of the gate hole pattern 25.
To form an insulating film (thermal oxide film) 15C with a thickness of
Boron is implanted as an impurity through the insulating film 15C (implantation energy 40 KeV) and an annealing treatment (1000
C) to form ap ^{+ -type} layer having a depth of about 0.3 μm and a width of 1 μm. This p ^{+ -type} layer becomes the gate region 4 and the gate length L _g is about 1 μm.

Next, on the main surface side of the p ^{+ type} substrate 1,
A PSG (phosphosilicate glass) film 28 is selectively formed, and the 15a is selectively removed by etching using the PSG film 28 as a mask. Then, phosphorus is implanted as an impurity into the exposed surface of the n-type island 3 and annealed. Processing n ⁺
Form layer is formed. This n ^{+ -type} layer becomes the drain region 5 and the source region 6 as shown in FIG.

Next, after removing the PSG film 28, a drain electrode 7 and a source electrode 8 made of aluminum having a thickness of about 1 μm are selectively formed on the drain region 5 and the source region 6 by ordinary photolithography. I do.
Pattern of the drain electrode 7 and the source electrode 8 has a shape as shown in FIG. 1, a portion each protrude from the top n-type island 3 p ⁺ form isolation regions 2
Extending above and extending to the bonding pads 20,2
It is set to 1.

Next, a passivation film 22 made of an insulating film having a thickness of several thousand Å is formed on the main surface side of the p ^{+ type} substrate 1 excluding the bonding pads 20 and 21. Thereafter, the thickness of the entire polishing the lower surface of the p ⁺ -type substrate 1 was about approximately 160 .mu.m, p ⁺
Gate electrode made of Au-based metal on the surface (lower surface) of the shaped substrate 1
Form 23. Thereby, as shown in FIG.
A semiconductor device having a junction field effect transistor is manufactured.

According to such an embodiment, the following effects can be obtained.

(1) Since the gate length of the JFET of the present invention can be reduced to 1 μm or less, the effect that the figure of merit can be improved can be obtained.

(2) Although the gate length of the JFET of the present invention is reduced to 1 μm or less, the gate length is increased at the gate end overlapping the isolation region. Such a defect that the contact with the semiconductor device does not occur no longer occurs, and the effect of improving the reliability of the product is obtained.

(3) Although the gate length of the JFET of the present invention is reduced to 1 μm or less, the gate length is increased at the gate end overlapping the isolation region. Such a defect that the contact with the substrate is not caused no longer occurs, and the effect that the production yield is improved and the production cost is reduced is obtained.

(4) According to (1) to (3), according to the present invention, a synergistic effect that a low-noise JFET can be manufactured at low cost is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

In the above description, the case where the invention made by the present inventor is applied to the manufacturing technique of the junction field effect transistor, which is the application field as the background, has been described, but the invention is not limited thereto.

The present invention can be applied to an IC incorporating at least a junction field effect transistor.

〔The invention's effect〕

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

In the JFET of the present invention, the connection between the isolation region and the gate is ensured by making the end portion of the gate corresponding to the step portion of the insulating film a wide structure, and the gate length is reduced to 1 μm or less. So high figure of merit
JFET can be manufactured with good reproducibility.

[Brief description of the drawings]

FIG. 1 is a plan view showing a main part of a semiconductor device constituting a JFET according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, and FIG. FIG. 4 is a cross-sectional view taken along a line III-III, FIG. 4 is a cross-sectional view showing a part of a semiconductor substrate used for manufacturing a JFET according to the present invention, and FIG. 5 is a semiconductor in which an n-type island and an etching for forming a gate are formed. FIG. 6 is a plan view of a part of the semiconductor substrate also showing an etching pattern for gate formation, FIG. 7 is a cross-sectional view of a semiconductor substrate also provided with a gate region, and FIG. FIG. 9 is a sectional view of a semiconductor substrate on which a source electrode and a drain electrode are formed, and FIG. 10 is a sectional view of a semiconductor element on which a conventional JFET is formed. FIG. 11 is a cross-sectional view Is a plan view showing the door pattern. 1 ... p ^{+ type} substrate, 2 ... p ^{+ type} isolation region, 3
... n-type island, 4 ... gate region, 5 ... drain region, 6 ... source region, 7 ... drain electrode, 8 ...
... Source electrode, 10,11 ... Insulating film, 12 ... Epitaxial layer, 13 ... Step, 14 ... Long gate part, 15,15a, 15b, 15c
... insulating film, 20, 21 ... bonding pad, 22 ... passivation film, 23 ... gate electrode, 25 ... hole (pattern for gate), 26 ... photoresist layer, 27 ... wide part, 28 ... PSG membrane.

Claims (2)

(57) [Claims] A first region including a source region and a drain region;
A field effect transistor including a first region of a conductivity type and a gate region of a second conductivity type formed in the first region, and having a step of an insulating film in a portion along a periphery of the first region; A semiconductor device, wherein the gate region is formed such that a gate length of a portion corresponding to a portion having a step of the insulating film is longer than a gate length of another portion. A first region including a source region and a drain region;
A field effect transistor having a first conductivity type semiconductor region and a second conductivity type gate region formed between the source region and the drain region is formed on a surface layer of the second conductivity type second semiconductor region. A step of an insulating film is formed at a boundary between the first semiconductor region and the second semiconductor region; the gate region extends from the first semiconductor region to the second semiconductor region; A semiconductor element, characterized in that a width of an end portion corresponding to a step portion of the insulating film in the first semiconductor region is wider than a width of another portion.