JPS6028144B2 - Manufacturing method of MIS type semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing an MIS type semiconductor device.

For more information, please see the new ROM (Read Only Memory)
The present invention relates to a method for manufacturing a highly integrated E/D skin SLSI having a circuit. E/DMISLSIs equipped with ROM circuits applied in the information processing field are required to have a high degree of integration in order to improve reliability, reduce costs, and operate at high speed. Conventionally, E/DMISLS [(hereinafter referred to as ROME/DMI
(abbreviated as SLSI) is a MIS type transistor Q arranged in a matrix as shown in Fig. 1 and Fig. 2 a to c.
、． ~ A part of Q3 is depletion type (Q, .o, Q, 3o, Q2o, Q33D), and the rest is enhancement type (Q, group, Q2, E,
Q2 details, Q3, B, Q328).

In addition, in FIG. ~X3 is output signal wiring,
Y, to Y3 are address wirings. And this ROM
E/DMISBI is shown in Fig. 2a as a plan view, Fig. 2b as a longitudinal cross-sectional view taken along arrow AA' in Fig. 2a, and Fig. 2c as a longitudinal sectional view taken as seen on arrow BB in Fig. 2a. Silicon substrate 1
It has a gate electrode made of a conductive polycrystalline silicon film 3 formed with a gate silicon oxide film 2 interposed thereon, and an N-type layer 4 formed by a self-alignment method using this gate electrode pattern is used as a source or It has a drain structure. In the figure, an N-type layer 5 under the gate electrode
6 is a diffusion layer in a depletion type MIS transistor, and 6 is a field silicon oxide film. Due to its structure, this type of ROME/DMOSBI has
Although the element size is kept as small as possible and the degree of integration is high, each MIS type transistor Q, . ~Since the N+ type layer 4 that becomes the source or drain in Q33 is formed on the surface of the silicon substrate 1, the lateral element dimension becomes considerably large, and the chip size becomes large to obtain 1 for multi-bit ROME/DMIS. It is something.

Therefore, an object of the present invention is to provide a method for manufacturing an S-type semiconductor device such as a ROM old/D-type SLSI having a novel structure and an extremely small element size.

In the present invention, a plurality of IMIS type transistors having gate electrodes are provided on a part of the surface of a semiconductor substrate with a first insulating film interposed therebetween in a matrix form, and gate electrodes in the IMIS type transistors are provided at regular intervals. a second insulating film provided on the entire surface of the electrode and the entire surface of the semiconductor substrate whose surface is exposed; and a gate electrode with a second insulating film interposed on the semiconductor substrate between each of the first skin S-type transistors. one second MIS type transistor provided between each of the first or second IMIS type transistors;
A method for manufacturing an MIS type semiconductor device in which a part of MIS type transistors is made to be a depletion type and the remaining part is made to be an enhancement type. Impurities for depletion are selectively introduced into a portion where a transistor is to be formed, and then the gate electrode is formed.

Hereinafter, ROME/DMOSLS, which is an embodiment of the present invention, will be described.
The method for producing I will be specifically explained.

The main feature of the ROME/DMOS according to the present invention is that it utilizes the multilayer wiring technology of MOSLSI and arranges MOS transistors in rows and columns with extremely high integration. Hansment Taifu.
Impurity ions of a conductivity type opposite to that of the substrate are ion-implanted into the channel region of a MOS transistor, thereby converting the transistor into a depletion type transistor. The gate electrode spacing in each MOS type transistor is made as small as possible, and the conventional ROMMOS of this type has a structure that achieves a high degree of integration that is about twice as high as that of the conventional ROMMOS.

Note that FIG. 3 is a schematic diagram showing a part of the ROM circuit according to the present invention, in which X, ~X3 are output signal wirings, Y, ~Y
6 is address wiring, Q, . Q36 indicates a silicon gate MOS transistor, the index D added thereto indicates a depletion type, and the index E indicates an enhancement type.

Now, the ROME/DMOS LSI according to the present invention and its manufacturing method will be explained in detail in the order of steps with reference to the drawings. A silicon wafer 11 having anti-P type or N type conductivity is prepared as a starting material, and its entire surface is thermally oxidized to form a field silicon oxide film 12 of about 1 Am. Next, the field silicon oxide film 12 is selectively removed by photo-etching or the like to expose the surface of the silicon wafer 11 which will become the device active region (FIG. 4).
. A gate silicon oxide film 13 of approximately 1000 A is formed on the silicon wafer 11 whose surface is exposed (FIG. 5), and then, in order to form a depletion type MIS transistor, a conductivity type opposite to that of the silicon wafer 11 is formed at that location. Impurities are ion-implanted into these channel regions to form a mist-type region 1 opposite to that of the silicon wafer 11.
Form 1a. For example, the silicon wafer 11 is
In the case of P-type conductivity, ions of N-type conductivity such as phosphorus are selectively implanted into the channel region of the depletion type MOB transistor using a photoresist as a mask, and the ions are removed by subsequent heat treatment. The implanted impurities are diffused into the silicon wafer 11 and N
A mold layer 11a is formed. N as silicon wafer 11
When using a type conductivity type, a P type conductivity type impurity such as poron may be used as the impurity to be ion-implanted to form the P type layer 11a. This depletion type MOS transistor Q, 20, Q, 4D
, Q2, Q32D, and Q35D are the eyes of the ROM. Furthermore, a conductive polycrystalline silicon film 14 of 3500 to 5000 Δ is formed on the entire surface by CVD or the like (FIG. 6). The broken line shown in FIG. 6A indicates the boundary between the field silicon oxide film 12 and the gate silicon oxide film 13. {i' The polycrystalline silicon film 14 is selectively removed to form a gate electrode pattern, and using this as a mask, an unnecessary portion of the gate silicon oxide film 13 is removed to expose the surface of the silicon wafer 11 at that location (step Figure 7).

The polycrystalline silicon film 14 of this gate electrode pattern, the gate silicon oxide film 13 underneath, and the silicon wafer 11
A large number of first silicon gate type MOS type transistors can be constructed by this, and these transistors are arranged in a matrix at constant intervals. 'ヮ' Next, a second MOS type transistor is connected between the first MOS type transistor and
In order to provide a silicon gate type MOS transistor, a silicon oxide film 15 of about 1000A is formed over the entire surface (FIG. 8).

This silicon oxide film 15 is a second silicon gate type M
It serves as the gate silicon oxide film of the OS type transistor and also electrically insulates the first and second transistors.

In addition, in order to make the characteristics of the first and second transistors the same, the gate silicon oxide film 13 is formed to have the same film properties and thickness as the gate silicon oxide film 13 in the first transistor, and the first and second transistors are sufficiently electrically connected. Select the film thickness necessary for target separation. Note that the two-dot chain line in the figure indicates the boundary line of the polycrystalline silicon film 13. P'
A conductive polycrystalline silicon film 16 having a thickness of 3500 to 5000 Å is formed on the entire surface by CVD or the like, and a gate electrode pattern for the second silicon gate MOS transistor is formed by photoetching or the like (FIG. 9).

Note that FIG. 10 shows indices in the ROM circuit configuration shown in FIG. 3. Note that the channel region of the depletion type MOS transistor, which is the eye of this ROM, is formed by selectively ion-implanting impurities into the silicon wafer 11 in the aforementioned process (FIGS. 4 to 6). It is something that

Next, although not shown, the entire surface is coated with an IJ insilicate glass film as a passivation film.

As mentioned above, ROME/DMOSL according to the present invention
SI uses a silicon wafer 11 as a starting material and a conductive polycrystalline silicon film thereon to form first and second silicon gate type MOS transistors Q, . ~Q$ are formed in a matrix, so it has an extremely high degree of integration with a simple manufacturing process.

For example, if the line width that can be formed by current photo-etching is 8 mm, the first and second MOS transistors can be formed with a device active region of 8 Am width, and the ROME with secondary source and drain diffusion layers can be formed. /DMO
In SLSI, each element active region is 16m
The IC chip area can be reduced by more than twice compared to the case where the width is about the same or more. In the present invention, silicon gate type MOS transistors having extremely small element dimensions are arranged in a matrix with the distance between them kept as small as possible, and any of these transistors can be of an enhancement type or Since it can be configured as a depletion type, it can be used as a ROM or as an E/DMOS LSI with various specifications, and can be used as a high performance and highly integrated MIS type semiconductor device in various forms.

Note that the ROME/DMOSLS according to the present invention described above
During the manufacturing process of I, an insulating film (silicon oxide film, etc.) is used as a mask for selective etching when forming the polycrystalline silicon film 14 into a gate electrode pattern, and it is left as is in subsequent steps. The thickness of the insulating film on the polycrystalline silicon film 14 as the gate electrode pattern (
The overlapping structure of the insulating film as a mask and the newly formed silicon oxide film 15 becomes large, and the parasitic capacitance between the first and second transistors can be reduced.

As described above, the MIS type semiconductor device according to the present invention is not limited to the above-described embodiments, but can be applied to various embodiments.

[Brief explanation of drawings]

Figures 1 to 2 a to c are subordinate ROME/DMOS
A circuit diagram of an LSI, a plan view and a vertical cross-sectional view showing its structure, and FIG.
The circuit diagrams of a part of the MOSLSI, FIGS.
FIG. 2 is a plan view and a vertical cross-sectional view showing a DMOS LSI and its manufacturing method in the order of steps. 1, 11... Silicon wafer, 2, 13, 15...
...Gate silicon oxide film, 3, 14, 16...
...Polycrystalline silicon film for gate electrode, 4...N+ type layer, 5...N type layer, 6, 12...Field silicon oxide film, 11a...What is silicon wafer 11? Regions of opposite conductivity type. Figure 1 Figure 3 Figure 2 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] 1. A first conductor layer formed to extend across the element active region set on the surface of the semiconductor substrate with an insulating film interposed therebetween; A second conductor layer formed on the element active region so as to overlap at least a portion of the first conductor layer.
an MIS type transistor connected in series by using each of the first and second conductor layers on the element active region as a gate electrode of an MIS type transistor;
The MIS forming an S-type transistor and connected in series
M type transistors are made with some of them being depletion type and the rest being enhancement type.
A method for manufacturing an IS type semiconductor device, which comprises introducing impurities into a selected portion of the surface of a device active region to make it a depletion type, and then forming the first and second conductive layers. A method for manufacturing an MIS type semiconductor device characterized by: