JPS6028145B2 - Manufacturing method of MIS type semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing an MIS type semiconductor device.

For more information, please see the new ROM (Read Only Memory)
The present invention relates to a method for manufacturing a highly integrated E/DMISLSI having a circuit.

EnoD equipped with a ROM circuit applied to the information processing field
MISLSI is required to have a high degree of integration in order to improve reliability, reduce cost, and operate at high speed.

Conventionally, B/Ds equipped with this type of highly integrated ROM circuit
MISLS1 (hereinafter abbreviated as ROME/DMISLSI) consists of MIS type transistors Q, . ~ A part of Q3 is a depletion type (Q, .o, Q
, 3o, Q2D, Q33o), and the rest are enhancement types (Q cape, Q2, E, Q2 spot, Q3, 8
, Q326).

In addition, in FIG. ~X3 is output signal wiring,
Y, to Y3 are address wirings. And this ROM
E/DMIS 1 shows a plan view in FIG. As shown, silicon substrate 1
It has a gate electrode made of a conductive polycrystalline silicon film 3 formed with a gate silicon oxide film 2 interposed thereon, and an N0 type layer 24 manufactured by a self-alignment method using this gate electrode pattern is used as a source or It has a drain structure. In the figure, an N-type layer 5 under the gate electrode is a diffusion layer outside the depletion type MIS transistor, and 6 is a field silicon oxide film. This type of ROME/DMOS 1 has a highly integrated structure with the element size as small as possible, but each of the MIS type transistors Q, . ~Since the N+ type layer 4 which becomes the source or drain in Q33 is formed on the surface of the silicon substrate 1, the lateral element dimension becomes considerably large, and the chip size becomes large to obtain 1 for multi-bit ROME/DMIS. It is something.

Therefore, an object of the present invention is to provide a method for manufacturing a MIS type semiconductor device such as a ROM old/D skin SLSI having a novel structure and extremely small element size.

In the present invention, a plurality of IMIS type transistors having a first gate electrode are provided on a part of the surface of a semiconductor substrate with a first insulating film interposed therebetween in a matrix shape, and a plurality of IMIS type transistors are provided in a matrix at regular intervals. a second insulating film provided on the entire surface of the gate electrode on the outside and the entire surface of the semiconductor substrate whose surface is exposed; and each of the first skins S
One second MIS type transistor is provided between each of the first skin S type transistors, each of which has a second gate electrode provided on a semiconductor substrate with a second insulating film interposed between the first type S type transistors. A method for manufacturing an MIS type semiconductor device in which a part of the first or second S-type transistor is of a depletion type and the remaining part is of an enhancement type, wherein the first or second S-type transistor is of the enhancement type. After forming a first gate electrode on the insulating film, removing the first insulating film not covered by the first gate electrode,
Next, a second insulating film is formed on the surface of the semiconductor substrate, and then a second gate electrode is formed.

Hereinafter, ROME/DMOSLS, which is an embodiment of the present invention, will be described.
I and its manufacturing method will be specifically explained.

The main feature of the ROM old/DMOSBI according to the present invention is that it utilizes the multilayer interconnection technology in MOSLSI to arrange MS transistors in rows and columns at an extremely high degree of integration, thereby enhancing the parts that serve as the eyes of the ROM. Mento type MO
An S-type transistor is formed into a depletion-type transistor by ion-implanting impurities of a conductivity type opposite to that of the substrate into the channel region of the S-type transistor. Then, the distance between the gate electrodes of each MOS type transistor is made as small as possible, and this type of RO
It has a structure that achieves about twice the density of MMOS LSI as compared to MMOS LSI.

Note that FIG. 3 is a schematic diagram showing a part of the ROM circuit according to the present invention, in which X, ~X3 are output signal wirings, Y, ~Y
6 is address wiring, Q, . Q36 represents a silicon gate MOS transistor, the index D added thereto represents a depletion type, and the index E represents an enhancement type.

Now, the ROME/DMOS LSI according to the present invention and its manufacturing method will be explained in detail in the order of steps with reference to the drawings. A silicon wafer 11 having anti-P type or N type conductivity is prepared as a starting material, and its entire surface is thermally oxidized to form a field silicon oxide film 12 of about 1 Am. Next, the field silicon oxide film 12 is selectively removed by photoetching or the like to expose the surface of the silicon wafer 11 which will become the device active region (FIG. 4).
. A gate silicon oxide film 13 of approximately 1000 A is formed on the silicon wafer 11 whose surface is exposed (FIG. 5), and then, in order to form a depletion type MOS transistor, a conductivity type opposite to that of the silicon wafer 11 is formed at that location. Impurities are ion-implanted to form regions 11a of a conductivity type opposite to that of the silicon wafer 11 in these channel regions. For example, if the silicon wafer 11 is of P-type conductivity, impurities of N-type conductivity such as phosphorus are selectively implanted into the channel region of a depletion type MOS transistor using a photoresist or the like as a mask. Through subsequent heat treatment, the ion-implanted impurities are diffused into the silicon wafer 11 to form an N-type layer 11a. When using an N-type conductivity type silicon wafer 11, a P-type conductivity type impurity such as boron may be used as the impurity to be ion-implanted to form the P-type layer 11a. These depletion type MOS transistors Q, 2o, Q, Q23o, Q32o, and Qxo serve as the eyes of the ROM. Furthermore, a conductive polycrystalline silicon film 14 having a thickness of 3500 to 5000 Å is formed on the entire surface by CVD or the like (FIG. 6). The broken line shown in FIG. 6a indicates the boundary between the field silicon oxide film 12 and the gate silicon oxide film 13. [A] A gate electrode pattern is formed by selectively removing the polycrystalline silicon film 14, and using this as a mask, an unnecessary portion of the gate silicon oxide film 13 is removed to expose the surface of the silicon wafer 11 at that location (FIG. 7). .

The polycrystalline silicon film 14 of this gate electrode pattern, the gate silicon oxide 13 under it, and the silicon wafer 11 can constitute a number of first silicon gate type MOS transistors, and these transistors are constant. They shall be arranged in a matrix with intervals. {u'
Next, in order to provide a second silicon gate type MOS type transistor between the first MOS type transistors,
A silicon oxide film 15 of about 1000 Å is formed over the entire surface (FIG. 8).

This silicon oxide film 15 is a second silicon gate type M
It serves as the gate silicon oxide film of the OS type transistor and also electrically insulates the first and second transistors.

In addition, in order to make the characteristics of the first and second transistors the same, the gate silicon oxide film 13 is formed to have the same film properties and thickness as the gate silicon oxide film 13 in the first transistor, and the first and second transistors are sufficiently electrically connected. Select the film thickness necessary for target separation. Note that the two-dot chain line in the figure indicates the boundary line of the polycrystalline silicon film 13. P}
A conductive polycrystalline silicon film 16 having a thickness of 3,500 to 5,000 Å is formed on the entire surface by CVD or the like, and a gate electrode pattern for the second silicon gate MOS transistor is formed by photoetching or the like (FIG. 9).

Note that FIG. 10 shows indices in the ROM circuit configuration shown in FIG. 3. Note that the channel region of the MOS transistor of depletion type 〇, which is the eye of this ROM, is formed by selectively ion-implanting impurities into the silicon wafer 11 during the force effect process (Figs. 4 to 6). It is being formed.

Carp Next, although not shown, the entire surface is coated with an IJ insilicate glass film as a passivation film.

As mentioned above, ROME/DMOSL according to the present invention
SI uses a silicon wafer 11 as a starting material and a conductive polycrystalline silicon film thereon to form first and second silicon gate type MOS transistors Q, . ~Q$ are formed in a matrix, so it has an extremely high degree of integration with a simple manufacturing process.

For example, if the line width that can be formed by current photoetching is 8 mm, the first and second MOS transistors can be formed with a device active region of 8 Am width, and the conventional ROME/MOS transistor with source and drain diffusion layers can be formed. DMO
In SLSI, each element active region is 16rm
The IC chip area can be reduced by more than twice compared to the case where the width is about the same or more. In the present invention, silicon gate type MOS transistors having extremely small element dimensions are arranged in a matrix with the distance between them kept as small as possible, and any of these transistors can be of an enhancement type or Depletion Taifu.

Since it can be configured as a ROM or as an Eno-DMOS LSI with various specifications, it can be used as a high performance and highly integrated MIS type semiconductor device in various forms. Note that the RO according to the present invention described above
During the manufacturing process of ME/DMOS LSI, an insulating film (silicon oxide film, etc.) is used as a selective etching mask when forming the polycrystalline silicon film 14 into a gate electrode pattern, and it is left as is in subsequent steps. The polycrystalline silicon film 1 as a gate electrode pattern is
The thickness of the insulating film on the insulating film 14 on 4 (the sum of the insulating film as a mask and the newly formed silicon oxide film 15) increases, and the parasitic capacitance between the first and second transistors increases. can be made small.

As described above, the skin S-shaped semiconductor device according to the present invention is not limited to the above-mentioned embodiments, but can be applied to various embodiments.

[Brief explanation of the drawing]

Figures 1 to 2 a to c are conventional ROME/DMOS
A circuit diagram of an LSI, a plan view and a vertical cross-sectional view showing its structure, and FIG.
The circuit diagrams of a part of the MOSLSI, FIGS.
FIG. 2 is a plan view and a vertical cross-sectional view showing a DMOS LSI and its manufacturing method in the order of steps. 1, 11... Silicon wafer, 2, 13, 15... Gate silicon oxide film, 3, 14, 16... Polycrystalline silicon film for gate electrode, 4... N-type layer, 5...・
. . . N-type layer, 6, 12 . . . Field silicon oxide film, 11a . . . Region of opposite conductivity type to silicon wafer 11. Figure 1 Figure 3 Figure 2 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] 1. The first
a first conductive layer extending across the insulating film, and a first conductive layer extending across the device active region via a second insulating film; a second conductor layer formed to overlap at least a part of the layer, and each of the first and second conductor layers on the element active region is used as a gate electrode of the MIS transistor. to form MIS type transistors connected in series, a part of the MIS type transistors connected in series are of depletion type, and the remaining ones are of enhancement type. After forming a first insulating film on the surface of the device active region, forming the first conductive layer, and removing a portion of the first insulating film that is not covered by the first conductive layer. A method for manufacturing an MIS type semiconductor device, characterized in that a second insulating film is then formed on the surface of the element active region, and then the second conductive layer is formed.