JP3089866B2 - Emulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer development support apparatus, and more particularly to an emulation circuit having an emulation chip that operates using the same clock as a microcomputer in order to obtain execution results of the microcomputer.

[0002]

2. Description of the Related Art An example of a conventional emulation circuit will be described with reference to FIG. FIG. 3A is a block diagram of a conventional emulation circuit. This system is used for debugging the program of the microcomputer 10, and the debugging is mainly performed by executing the program of the microcomputer 10 and dumping the contents of the memory in which the result is stored after the execution.
The microcomputer 10 includes a timing generator 11 and an output circuit 12. The emulation chip 20 is a chip that performs an interface between the microcomputer 10 and the emulator 30, and includes an oscillation circuit 21, a timing generator 22, and a data bus latch circuit 23. The oscillation circuit 21 generates a clock for operating the microcomputer 10,
It is configured as a crystal oscillator having a crystal blank X.

The execution, stop, and other control of the program of the microcomputer 10 are all performed through the emulation chip 20. Therefore, the emulation chip 20 operates in synchronization with the microcomputer 10. The memory 40 is a memory for storing an execution result of the microcomputer 10,
Actually, the contents of the data bus 100 output from the microcomputer 10 are latched and written by the latch circuit 23 of the emulation chip 20. Further, the voltage level conversion circuit 50 converts the voltage level of a signal between the microcomputer 10 and the emulation chip 20.

Next, an example in which the result of execution of the program of the microcomputer 10 is inputted by the emulation chip 20 and written into the memory 40 will be described with reference to a timing waveform diagram of FIG. As described above, since the microcomputer 10 and the emulation chip 20 need to operate synchronously, the clock 2 of the oscillation circuit 21 is used.
00 is output from the terminal T1 and the microcomputer 1
Before the clock 200 is inputted, the voltage level of the clock 200 is converted by the voltage level conversion circuit 50. For this reason, the clock 201 input to the microcomputer 10 passes through the voltage level conversion circuit 50 and the
Due to the wiring capacity up to and the like, a delay t11 occurs as compared with the clock 200. The microcomputer 10 uses the clock 201 to generate a strobe signal 202 as a basic clock in the timing generator 11.

On the other hand, in the emulation chip 20, the clock 200 is once output from the terminal T2, and is delayed by the delay amount
00 'and input from terminal T3. Then, the strobe signal 203 is generated as a basic clock by the timing generator 22 in the emulation chip 20 using the clock 200 '. The emulation chip 20 includes a microcomputer 10
Of the data bus 100 output from the output circuit 12
01 is latched by the strobe signal 203 and written into the external memory 40.

However, the content 101 of the data bus 100 which the emulation chip 20 inputs from the input terminal T4 is used.
Is a data bus 1 including a voltage level conversion circuit 50 and a wiring capacitance.
A delay t13 is generated for the signal 00. For this reason, the strobe signal 20 in the microcomputer 10
If the strobe signal 203 of the emulation chip 20 is not delayed by the delay t13 as compared with 2, the correct data may not be latched. Thus, the amount of delay t which must be provided by the clock delay circuit 60 described above.
12 must be the sum of t11 and t13.
However, since the delay amounts t11 and t13 vary depending on the oscillation frequency, the voltage to be converted, and the like, it is difficult to determine them in advance. Further, since the delay amount t12 cannot be quantitatively measured by this circuit, the delay amount t12 of the delay circuit 60 is appropriately determined.

[0007]

As described above, the conventional emulation circuit adjusts the synchronization deviation between the emulation chip and the microcomputer, which must operate synchronously, due to a delay caused by a clock line and a signal line. Was performed by delaying the clock in the emulation chip, but since the amount of delay could not be quantitatively determined, it was determined appropriately. For this reason, there is a problem that the emulation circuit may not operate normally when the amount of delay is insufficient or too large. SUMMARY OF THE INVENTION An object of the present invention is to provide an emulation circuit capable of appropriately setting a clock delay amount in an emulation chip and ensuring normal operation of the circuit.

[0008]

According to the present invention, a clock is generated.
Oscillator raw, microcomputer, clock delay circuit, the emulation circuit and a emulation chip, the emulation chip, the click
Japanese means for generating a signal at the same timing as this on the basis of the lock has been delayed clock, from the generated signal a microcomputer with respect to the clock
A comparison circuit for comparing the output signal with a signal output in a constant state, wherein a delay amount of the clock delay circuit is set based on a comparison output from the comparison circuit.

[0009]

Next, the present invention will be described with reference to the drawings. FIG. 1A is a block diagram of an emulation circuit according to a first embodiment of the present invention. In this figure, the same parts as those of the conventional configuration shown in FIG. 3 are denoted by the same reference numerals.
In this embodiment, after the clock signal output from the clock output terminal T2 of the emulation chip 20 is delayed by the delay circuit 60, the delayed clock 20
0 'is input from the clock input terminal T3, and the clock 200' is input to the timing generator 22 to output the basic clock 204 together with the strobe signal 203. Further, in order to determine the delay amount of the delay circuit 60, one of the basic clocks of the microcomputer 10 is inputted from a clock input terminal T5, and the inputted basic clock 205 and the basic clock 204 from the timing generator 22 are inputted. Are compared in the comparison circuit 24 and are output to the output terminal T6 as the comparison output 206. Here, EXOR is used as the comparison circuit 24.

Next, an example in which the result of execution of the program of the microcomputer 10 is input by the emulation chip 20 and written into the memory 40 will be described with reference to the timing waveform diagram of FIG. The clock 200 of the oscillation circuit 21 composed of a crystal oscillator is output from the terminal T1 and is input into the microcomputer 10. The clock 200 is converted into a voltage level by the voltage level conversion circuit 50 before being input. I have. For this reason, the clock 201 input to the microcomputer 10 passes through the voltage level conversion circuit 50 and has a delay t1 compared to the clock 200 due to the wiring capacity from the emulation chip 20 to the microcomputer 10 and the like. The microcomputer 10 uses the clock 201 to generate a basic clock 205 and a strobe signal 202 by the timing jellator 11.

On the other hand, in the emulation chip 20, the clock 200 is temporarily output from the terminal T2, and is delayed by the delay amount t2 by the clock delay circuit 60, so that the input terminal T
3 is input. Then, the basic clock 204 and the strobe signal 203 are generated by the timing generator 22 using this clock. Then, in the emulation chip 20, the contents 101 of the data bus 100 output from the microcomputer 10 are latched by the strobe signal 203 in the latch circuit 23 and written into the external memory 40. At this time, the content 101 of the data bus obtained by the emulation chip 20 has a delay t3 due to the voltage level conversion circuit 50, wiring capacitance, and the like. Therefore, the strobe signal 2 in the microcomputer 10
If the strobe signal 203 of the emulation chip 20 is not delayed by the delay t3, correct data cannot be latched unless it is delayed by t3. Will not be.

In order to determine the delay amount t2 of the delay circuit 60, the basic clock 2 of the microcomputer 10 is used.
05 and a basic clock 204 obtained from the basic clock passed through the delay circuit 60 are compared by the comparison circuit 24, and the delay amount t2 of the delay circuit 60 is set based on the output 206 of the comparison circuit 24. That is, here, the comparison circuit 60
Since the XOR is used, it is considered that a period during which the output signal 206 from the comparison circuit 60 is at a high level corresponds to a delay. Therefore, when the delay amount t2 is determined, if the signal 206 is monitored and adjusted so as to eliminate the high-level period, the correct delay amount t2 can be set in the delay circuit 60 . The basic clock 205 is a microcontroller.
Same as data bus 100 output from computer 10
Through the voltage level conversion circuit 50 and the data bus
With the wiring capacitance due to the wiring length almost the same as 100,
There is a delay amount that can be regarded as the same as the delay amount t3.
This allows the setting in the delay circuit 60 described above.
Become. As a result, it is possible to prevent a problem in receiving data of the emulation chip due to a shortage or an excessively large delay amount.

FIG. 2A is a block diagram of an emulation circuit according to a first embodiment of the present invention. The basic circuit configuration of this embodiment is the same as that of the first embodiment, but here, as a signal to be compared in the comparison circuit 24, a part of the data bus contents 101 of the data bus output from the microcomputer 10 is used. The signal 102 and the data bus signal 204 from the timing generator 22 are used. The data bus signal 204 is a specific signal line of the data bus. Therefore, in this embodiment, the measurement of the delay amount is performed when data is output from the microcomputer 10.
That is, it is executed when the microcomputer 10 is executing a specific instruction.

FIG. 2B shows a timing waveform when the microcomputer 10 is executing the specific instruction. The execution of this specific instruction is performed according to an instruction from the emulator 30. At this time, a fixed timing signal is output to the data bus signal 204 with respect to the clock 201. The data bus signal 102 is the same timing signal as the signal output from the data bus 204 when the microcomputer 10 executes a specific instruction. The comparison circuit 24 compares the data bus signal 204 with the data bus signal 204 and outputs the comparison signal 207 to the terminal T6. Output.

Also in this embodiment, since the EXOR is used as the comparison circuit 24, it is considered that the high level of the comparison signal 207 corresponds to the delay. For this reason, when determining the amount of delay, the microcomputer 10 executes a specific instruction to monitor the signal 207,
Since the delay circuit 60 can be adjusted so that the high-level period is eliminated, a correct delay amount can be set in the delay circuit 60.

[0016]

Emulation circuitry as the present invention described above, according to the present invention includes a signal generated based on the clock generated by the oscillator clock delayed by the clock delay circuit, clock from the microcomputer from said oscillator
The comparison circuit compares a signal output in a specific state with respect to the clock, and sets the delay amount of the clock delay circuit based on the comparison result. Since the delay amount can be quantitatively monitored while monitoring the actual operation, there is an effect that a problem of receiving data of the emulation chip due to the shortage or too large of the delay amount does not occur.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of an emulation circuit of the present invention and a timing waveform diagram thereof.

FIG. 2 is a block diagram and a timing waveform diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of an example of a conventional emulation circuit and a timing waveform diagram thereof.

[Description of Signs] 10 microcomputer 11 timing generator 20 emulation chip 21 oscillator circuit 22 timing generator 23 latch circuit 24 comparison circuit 30 emulator 40 memory 50 voltage level conversion circuit 60 delay circuit

Claims (1)

(57) [Claims] An oscillator for generating a clock;
The execution of the program by the clock inputted from the vessel, and outputs a fixed signal in a particular state to the clock, and a microcomputer for outputting the execution result of the program to the data bus, the clock of the oscillator An emulation circuit comprising: a delay circuit; and an emulation chip that receives the delayed clock, obtains a program execution result of the microcomputer from a data bus, and performs a predetermined process based on the delayed clock. Means for generating a signal at the same timing based on the delayed clock; and a means for generating the signal and outputting the signal before output from the microcomputer.
A comparison circuit that compares the signal in the specific state .
An emulation circuit, wherein a delay amount of the clock delay circuit is set based on a comparison output from the comparison circuit.