JP3101433B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a two-stage recess type gate electrode.

[0002]

2. Description of the Related Art (Conventional Example 1) FIGS. 14A to 14C show a conventional method for manufacturing a compound semiconductor field-effect transistor having a two-step recess type gate electrode.
There are known methods based on sectional views of the steps (a) to (c). That is, a semiconductor active layer 32 is formed by ion implantation of impurities or the like on the GaAs compound semiconductor substrate 31, and an insulating film such as a nitride film (SiN) or an oxide film (SiO), After forming the spacer layer 33 by resist, a photoresist 34 for gate patterning is laminated thereon. Next, using the gate pattern of the photoresist 34 as a mask, the spacer layer 33 is
14A, an opening 35 having a width L of, for example, 0.5 .mu.m is formed by the RIE method using F4 + O2 gas. When the spacer layer 33 is formed of a photoresist as described above, a type different from the photoresist 34 laminated thereon is used.

Next, the semiconductor active layer 32 is wet-etched by a desired amount through the opening 35 using the photoresist 34 as a mask to form a lower recess region 36a as shown in FIG. The depth t1 of the lower recess region 36a is about 0.1 μm when the thickness of the semiconductor active layer 32 is 0.5 μm. The recess width W1 of the lower recess region 36a is about 0.5, although it depends on the etching method and the type of the etching solution.
０．７0.7 μm. Next, as shown in FIG. 14 (c), only the spacer layer 33 is substantially 0.2 μm on both sides with a buffered hydrofluoric acid solution.
Perform side etching step by step. Then spacer layer 3
The upper recess region 36b is formed by wet-etching the semiconductor active layer 32 again using the mask 3 as a mask, and a two-step recess region 36 as shown in FIG. 15A is obtained.

[0004] The above-mentioned upper recess region 36b is formed 2
Two-stage recess region 36 obtained by the second etching
Are, for example, such that the depth t2 of the upper recess 36b is 0.
2 .mu.m, the width W2 is 1.1 .mu.m, and the lower recess 36a
Is the same as the depth by the first etching, ie, 0.1.
μm. However, the width W1 'of the lower recess 36a is
Is about 0.9 μm in isotropic wet etching, which is wider than the initially formed width W1.

Thereafter, as shown in FIG. 15B, a gate electrode metal 37a is deposited on the photoresist 34 and through the opening 35 into the two-step recessed region 36 by vacuum evaporation or the like, and then the photoresist 34 is lifted off. , And by removing the gate electrode metal 37a thereon,
A gate electrode 37 having a gate length Lg (substantially equal to the width L of the opening 35) is formed in the two-step recess region 36 as shown in FIG. Although not shown, a field effect transistor (FET) is formed by forming a drain electrode and a source electrode on both sides of the position of the gate electrode 37 in one of the steps before and after the above step.

(Conventional Example 2) FIG. 6 is a cross-sectional view showing a field effect transistor (MESFET) having a two-stage recess type metal Schottky junction gate electrode, which is a kind of compound semiconductor device targeted by the present invention. FIG. 16 shows FIG.
FIG. 11 is a cross-sectional view showing main forming steps of a conventional method for forming a two-step recessed gate electrode of FIG.
Is a wafer (compound semiconductor substrate), and 46 is an active layer formed in the surface region. 42 (42a, 42
b) is an ohmic electrode formed on the active layer 46;
4 is an upper recess, 45 is a lower recess, and 43 is a gate electrode formed in the lower recess 45. Also,
In FIG. 16, reference numeral 52 denotes an insulating film, and 62 denotes a resist. However, except for FIG. 6, the active layer 46 is not shown because it is considered to be a part of the wafer 41.

In the MESFET shown in FIGS. 6 and 16, the voltage applied to the gate electrode 43 and the ohmic electrodes 42a and 42b must be increased in order to increase the output. In order to increase the breakdown voltage in this way, there is a method in which the active layer 46 near the gate electrode 43 is thinned so that the depletion layer easily spreads in the vicinity of the gate electrode 43 when the gate electrode 43 is biased. As one of the methods, there is a method of forming a two-stage recess type gate structure. Next, the conventional forming method will be described.

As shown in FIG. 16A, an insulating film 52 made of SiO 2 is formed on the entire surface of the wafer 41 to a thickness of about 0.1 μm.
A resist 62 having a thickness of about 0.5 μm is formed thereon, and an opening pattern having an opening width of 0.5 μm is formed near the gate electrode formation site. Next, FIG.
As shown in (b), the lower insulating film 5 is formed using the resist 62 as a mask.
2 is wet etching using hydrofluoric acid or CHF
Etching is performed by dry etching using 3 + O2 gas or the like. Next, as shown in FIG. 16C, using the insulating film 52 as a mask, the wafer 41 is etched by wet etching using tartaric acid or the like or by dry etching using a chlorine-based gas to form a recess having a depth of about 0.1 μm. 47 is formed. Next, as shown in FIG. 16D, the insulating film 52 is selectively side-etched with hydrofluoric acid or the like to widen the opening of the insulating film 52. Next, as shown in FIG. 16E, when the wafer 41 is etched by wet etching using tartaric acid or the like using the insulating film 52 as a mask, the lower recess 47 is recessed further downward to a depth of about 0.3 μm. A lower recess 45 having a width of about 0.9 μm, a depth of about 0.1 μm, and a width of about 1.4 to
An upper recess 44 of 2.4 μm is formed. Next, FIG.
As shown in (f), Ti / Au was used as the metal for the gate electrode.
Then, a structure as shown in FIG. 16G having a gate electrode 43 having a gate width of about 0.5 μm and a gate height of about 0.5 μm, that is, the structure of FIG. 6 is formed by performing a lift-off method. You.

(Conventional Example 3) FIG. 17 is a view showing still another example of a conventional two-stage recess forming method of this kind of two-stage recess type field effect transistor. In FIG. 17, reference numeral 71 denotes a semiconductor substrate, and 78 denotes a semiconductor substrate. An active layer, 72 is an ohmic electrode, 73 is an insulating film, 74 is a resist, 75 is a first recess, 76 is a second recess, and 77 is a Schottky metal.

Next, the manufacturing process will be described. In FIG. 9A, after forming a source, a drain and an ohmic electrode 72 on an active layer 78 formed on a semiconductor substrate 71,
An insulating film 73, for example, a SiN film is formed on the entire surface. Then F
A resist pattern 74 having an opening at a position where an ET gate electrode is to be formed is formed.

Next, as shown in FIG. 1B, after the insulating film 73 in the resist opening is etched by SF6 plasma treatment or the like, the exposed GaAs of the active layer 78 is replaced with an appropriate Ga.
As etching solution, for example, H2 SO4: H2 O2: H2
Etching is performed at O = 3: 1: 1 to obtain a first recess 75.

Next, as shown in FIG. 1C, the insulating film 73 is side-etched by immersing it in an appropriate etching solution, for example, 30% HF solution. In this state, when immersed in the above-mentioned GaAs etching solution, a second recess 76 is obtained in addition to the first recess 75 which is etched deeper, and the etching shape is a two-stage structure as shown in FIG. Becomes

Next, a Schottky metal 77 such as Ti
/ Pt / Au = 500 Å / 500 Å / 5000 Å
(e). Next, in the lift-off process, the resist 74 is used.
And unnecessary metal on it is removed to obtain the state shown in FIG.

[0014]

A conventional compound semiconductor field effect transistor device having a two-step recess can be obtained by the above-described method. In forming the two-step recess, a spacer layer 33 or an insulating layer 52, The side etching of 73 controls the amount of etching by the immersion time of the etching solution or etching gas supplied through the openings of the photoresists 34, 62, and 74. However, the supply of the etching solution is uneven in the wafer surface. And the control of the side etching amount becomes unstable because the etching rate is changed by the adhesive force of the semiconductor active layer / spacer layer (insulating layer) / photoresist. There was variation. Since the width of the first and second recesses is determined by the amount of side etching of the insulating film, there is a problem that the recess shape is greatly varied due to the variation of the amount of side etching. Also, if there is a variation or variation in the recess shape due to the variation of the side etch amount between lots or wafers, this is due to the source resistance Rs and the gate / drain breakdown voltage V that determine the characteristics of the FET.
gd0 was dispersed, causing a decrease in yield.

The present invention has been made in order to solve the above-mentioned problems, and a two-step recess structure can be stably formed between lots and wafers stably, and high device characteristics can be obtained. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can achieve uniformity and lower element cost. Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a T-type gate electrode.

[0016]

Means for Solving the Problems Claim 1 of the present invention 2
In a method of manufacturing a semiconductor device having a stepped recess, first, patterning for determining the width W2 of the upper recess and the gate length Lg is performed by applying a photoresist on the semiconductor active layer, and the semiconductor active layer is formed by using the photoresist as a mask. Dry etching is performed to form an upper recess region and a dummy gate, and then an insulator is buried in the upper recess region, and an opening wider than the dummy gate is formed on the semiconductor active layer including the upper surface of the recess by a photoresist. After the insulator in the upper recess region is partially removed by etching using the photoresist as a mask, the semiconductor active layer serving as a dummy gate and the semiconductor substrate thereunder are etched to form a lower gate. By forming a recess region, a two-step recess is obtained.
A T-shaped gate electrode is formed in the step recess region by vacuum deposition and lift-off.

According to a second aspect of the present invention, in a method of manufacturing a semiconductor device having a two-stage recess structure, after forming a dummy gate and a sidewall with an insulating film on a semiconductor active layer, the semiconductor gate is exposed on both sides of the sidewall. A photoresist is applied on the semiconductor active layer so as to locate the dummy gate and the side wall. After that, only the side wall is selectively removed by dry etching, and then wet etching is performed using the photoresist and the dummy gate as a mask. Etching the semiconductor active layer to form an upper recess,
After the photoresist is once removed, the photoresist is applied again on the semiconductor active layer including the upper recess region, the dummy gate is located, and only the dummy gate is selected by wet etching using the photoresist as a mask. Forming a lower recess region by wet etching the semiconductor active layer thereunder to form a lower recess region, and forming a gate electrode by vacuum deposition and lift-off in the lower recess region. It is.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a two-step recess structure, wherein a resist is used instead of an insulating film.
PMGI (Poly methyl glutar)
・ Imide), PMGI side etching layer
Is controlled by exposure, and then the desired width is
Only the development is removed. That is,
Specifically, a PMGI (polymethyl group) is formed on a semiconductor substrate.
Coating and exposure, and the above substrate
At the top, a hole with an opening corresponding to the size of the lower recess
Form a distant pattern and etch the PMGI
PMGI pattern with the same degree of opening
Forming and etching the substrate using the PMGI as a mask
Forming a lower recess, and forming the lower part of the PMGI.
By developing the opening, the size of the opening is
And a step of etching the substrate with the PMGI as a mask to form a two-step recess consisting of an upper recess and a lower recess with a greater depth. Forming a gate electrode on the lower recess of the recess by vapor deposition lift-off using the resist.

A method of manufacturing a semiconductor device having a two-step recess structure according to claim 4 of the present invention, light irradiation assisted etch down
Two-stage recess without using side etching
It is intended to gain structure .

The method of manufacturing a semiconductor device having a two-step recess structure according to claim 5 of the present invention, a semiconductor on a semiconductor substrate
Overhang shape on active layer with opening
Forming a resist pattern, followed by photo-assist
Top opening of the above resist pattern by etching
Etching the semiconductor active layer using the portion as a mask,
Step of obtaining a recess, followed by chemical reaction without using light
Etching only by etching the lower part of the resist opening
The second recess, and deepen it further
Obtaining a first recess .

The method of manufacturing a semiconductor device having a two-step recess structure according to claim 6 of the present invention, the semiconductor substrate a semiconductor active
Has an overhang shape in the opening forming part on the conductive layer
Step of forming a resist pattern, and then do not use light
Etching by only chemical reaction
By using the lower part as a mask, the second recess is formed.
And a light assisted etching to open the resist.
Obtaining a first recess by using the upper portion of the mouth as a mask .

The overhang shape according to claim 7 of the present invention.
7. The method according to claim 5, wherein the step of forming the resist comprises:
In the manufacturing method of the body device, the tapered cross-sectional shape
Forming an insulating film and opening the insulating film pattern portion;
Forming a resist pattern having a portion;
Heat is generated on the side of the insulating film
Pressure bonding process and a process of etching and removing the insulating film.
It is intended to include consisting of a degree.

[0023]

In the method of manufacturing a semiconductor device having a two-step recess according to the first and second aspects of the present invention, the two-step recess region is formed separately from the upper recess and the lower recess, thereby individually controlling the recess dimensions. Therefore, a two-step recess having a specified shape can be reliably formed, and a T-type gate electrode can be easily obtained.

[0024] In the method of manufacturing a semiconductor device according to claim 3 of the present invention, the exposure amount of etching P MGI, about 0.
Since the control can be performed with high precision down to the level of 01 μm / sec, the recess can be developed and removed with an alkali developing solution for a desired time, so that the recess shape can be made highly uniform.

In the method of manufacturing a semiconductor device having a two-step recess structure according to claims 4 , 5 , and 6 of the present invention, the overhang-shaped resist pattern is used as a mask so that the recess width is defined by the upper opening width. The first recess is formed using assist etching, while the second recess is formed by wet etching so that the recess width is defined by the width of the lower opening of the resist pattern. The second recess width does not vary as in the method for obtaining the recess.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. Embodiment 1 FIGS. 1 (a) to 1 (d) and 2 (a) to 2 (d) are sectional views showing an embodiment of the first aspect of the present invention in the order of steps. As shown in FIG. 1A, a semiconductor active layer 2 is formed on a GaAs semiconductor substrate 1, a photoresist 3 is applied on the semiconductor active layer 2, and an opening pattern corresponding to an upper recess width W2 is formed. A pattern corresponding to the gate length Lg is formed in the opening pattern.

Next, using the photoresist 3 patterned as described above as a mask, the semiconductor active layer 2 is etched by dry etching by RIE using SF6 + SiCl4 gas to form an upper portion as shown in FIG. Concave portions corresponding to both sides of the recess region 4 are formed, and a dummy gate 5 is formed between the concave portions, and then the photoresist 3 is removed. Here, since the width W2 of the upper recess region 4 is determined in advance when the photoresist 3 is applied and the pattern is formed as shown in FIG. 1A, the recess shape is not constant due to the variation in the amount of side etching of the spacer layer. The problems of the conventional method are eliminated.

Next, as shown in FIG. 1C, an insulating film such as a nitride film (SiN), an oxide film (SiO) or a nitrided oxide film (SiON) or a photoresist is formed in the upper recess region 4 by an insulator 6. After the surface is planarized by embedding, the dummy gate 5 has an opening pattern wider than the width Lg and smaller than the upper recess width W2 on the semiconductor active layer 2 including the upper recess region 4 in which the insulator 6 is embedded. A resist 7 is formed by coating (FIG. 1 (d)). When the insulator 6 in the upper recess region 4 is formed of a photoresist, it is necessary to prevent the photoresist in the recess from being developed when the photoresist 7 formed thereon is developed. Therefore, it is preferable that both use different resist materials.

Next, as shown in FIG. 2A, a part of the insulator 6 in the upper recess region 4 is removed by dry etching using the photoresist 7 as a mask as shown in FIG. By etching the dummy gate 5 and the semiconductor active layer 2 therebelow with a tartaric acid-based or phosphoric acid-based etchant using the object 6 as a mask to form a lower recess 8, as shown in FIG. Two-stage recess 9
Is obtained. Thereafter, a gate electrode metal 10a is applied to the inside of the two-step recess 9 and the photoresist 7 by a vacuum deposition method, and unnecessary gate electrode metal 10a is removed together with the photoresist 7 by lift-off.
(c) As shown in FIG.
Is obtained. Note that the insulator 6 in the upper recess 4 may be removed by dry etching or wet etching to form the form shown in FIG.

In the first embodiment, since the two-stage recess region is formed completely in two steps of the upper recess region and the lower recess region, the conventional two-stage recess forming method is used. As described above, variations in the side etching of the insulating layer do not cause variations in the recess shapes of the upper and lower recesses, and the width of the lower recess formed first is widened by etching for forming the upper recess. Thus, the two-step recess can be formed stably. Also, since the insulator 6 is used to separate the formation of the upper recess and the lower recess, the lower portion is made thinner by the insulator 6,
A T-shaped gate electrode having a thick upper portion can be easily obtained, and a semiconductor device having a small gate resistance and a stable performance with improved withstand voltage can be manufactured with high yield.

Embodiment 2 FIGS. 3 (a) to 3 (d), FIGS. 4 (a) to 4 (c), and FIGS. 5 (a) to 5 (c) are sectional views showing an embodiment of the second aspect of the present invention in the order of steps. FIG. As shown in FIG. 3A, first, an insulating film 11 such as SiN or SiON is formed on an upper surface of a semiconductor active layer 2 formed on a semiconductor substrate 1, and a photoresist 1 is formed on the insulating film 11.
2 is applied and patterned. Then, using the photoresist 12 as a mask, the other portion of the insulating film 11 is removed by dry etching such as RIE (FIG. 3 (b)), and then the photoresist 12 is removed as shown in FIG. 3 (c). Next, a dummy gate 13 is formed on the semiconductor active layer 2. The length Lg of the gate electrode to be formed later is determined by the width of the dummy gate 13.

Next, an insulating film 14 is formed on the entire surface of the dummy gate 13 and the semiconductor active layer 2 by plasma CVD using a material different from the insulating film forming the dummy gate 13, for example, SiO. It is formed as follows. Then E
By removing the insulating films on both ends of the dummy gate 13 and the semiconductor active layer 2 by dry etching such as CR (Electron Cyclotron Resonance) etching, sidewalls 15 ′ having a desired width are provided on both sides of the dummy gate 13.
15 are formed as shown in FIG.

Next, as shown in FIG. 4B, a photoresist 16 is applied on the semiconductor active layer 2 so that the dummy gate 13 and the sidewalls 15 and 15 are located. Next, after selectively removing only the side walls 15 and 15 by dry etching by RIE, the semiconductor active layer 2 is etched with a tartaric acid-based or phosphoric acid-based etchant using the photoresist 16 and the dummy gate 13 as a mask. And upper recess 1 as shown in FIG.
7 and a dummy gate 18 are formed.

After the photoresist 16 in FIG. 4C is once removed, a new photoresist 19 is applied on the semiconductor active layer 2 so that the dummy gate 18 is caught as shown in FIG. 5A. I do. Next, using the photoresist 19 as a mask, only the dummy gate 13 is selectively removed by etching with a buffered hydrofluoric acid solution. Then, the dummy gate 18 and the semiconductor active layer 2 thereunder are tartaric acid or phosphoric acid. By etching using a system etchant and forming a lower recess 20 in the semiconductor active layer 2 as shown in FIG. 5B, a two-step recess region 21 is obtained by the upper recess 17 and the lower recess 20. Can be

Thereafter, a gate electrode metal 10a is deposited in the two-step recess region 21 and on the photoresist 19, and unnecessary gate electrode metal 10a is lifted off together with the photoresist 19, as shown in FIG. ,
A semiconductor device having the gate electrode 10 formed in the two-step recess region 21 is obtained.

In the second embodiment, as in the first embodiment, the two-stage recess region is formed in two steps of the upper recess region and the lower recess region. The two-step recess can be stably formed without the lower recess width fluctuating unlike the formation. Also, a photoresist 19 for forming a lower recess is formed.
Is formed so as to fill the space where the substrate is etched using the dummy gate 13 as a mask, so that a T-type gate electrode can also be easily formed, and the gate resistance is small and the withstand voltage is improved. Semiconductor devices can be manufactured with high yield.

In the first and second embodiments, the step of wet etching using an etching solution such as tartaric acid or phosphoric acid or buffered hydrofluoric acid is not limited thereto, and may be performed by dry etching. It is possible. As the gate electrode metal, Al, WSi,
Ti / Al, Ti / Mo / Al, Ti / Mo / Ti / A
One or more kinds of metals having a laminated structure such as u can be used.

Embodiment 3 Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 6 is a cross-sectional view of a compound semiconductor field-effect transistor having a two-step recess type gate according to the present embodiment, and FIG. 7 is a cross-sectional view showing main steps of a manufacturing method thereof. In FIG. 6, 41 is a GaAs semiconductor substrate, 46 is an active layer formed on the semiconductor substrate 41, 44 is an upper recess, 45 is a lower recess, and 42a and 42b are ohmic electrodes. In FIG. 7, reference numeral 50 denotes an insulating film, and reference numeral 60 denotes a resist.

Next, the manufacturing method will be described. Figure (a)
As shown in FIG. 3, an insulating film such as SiO is formed on the upper surface of the semiconductor substrate 41, a photoresist is applied thereon, and the photoresist is patterned to a width of about 1 to 2 μm. By etching the insulating film, 1-2 of the size corresponding to the upper recess is obtained.
An insulating film 50 having a width of μm is formed. Next, as shown in FIG. 3B, a resist 60 is applied thereon to a thickness of about 0.5 μm to form a resist 60 opening pattern having a width of about 0.5 μm corresponding to the gate electrode pattern. Next, as shown in FIG. 4C, the insulating film 10 is etched by wet etching using hydrofluoric acid or dry etching using CHF3 + O2 gas or the like using the resist 60 as a mask.
At 0, an opening corresponding to the gate electrode pattern is formed. At this time, the opening width of the insulating film 50 is about 0.6 μm. Further, using the insulating film 50 as a mask, the semiconductor substrate 1 is etched by wet etching using tartaric acid or the like or by dry etching using a chlorine-based gas to a depth of about 0.1.
A recess 47 having a width of about 0.5 to 0.7 μm is formed. Here, when wet etching is performed, the etching is performed in the depth direction, and at the same time, depending on the plane orientation of the substrate material, the etching solution, etc., for example, at a ratio of 0.7 to 1.0, for example, in the horizontal direction. Since the opening width of the recess 47 is wider than the opening pattern of 0.5 μm,
In this case, it is more preferable to use dry etching including the above-described etching of the insulating film from the viewpoint of improving dimensional controllability. Next, as shown in FIG. 4D, the insulating film 50 having a width of about 1 to 2 μm is entirely removed with hydrofluoric acid or the like. Next, as shown in FIG. 3E, the semiconductor substrate 1 is etched by wet etching using an etching solution such as tartaric acid, so that the lower recess 47 is further recessed to a depth of about 0.3 μm and a width of about 0.3 μm. A lower recess 45 of about 0.9 μm, a depth of about 0.1 μm, and a width of about 1.4 to 2.4 μm.
m upper recess 44 is formed. Next, a metal for the gate electrode 43, such as Ti / Au, is deposited and lifted off as shown in FIG. 5F, and a two-step recess gate can be formed as shown in FIG.

In the present embodiment, in the method of manufacturing a compound semiconductor device having a two-step recess, the insulating film 50 is left on the compound semiconductor substrate 41 by etching to a desired size. A lower recess is formed by utilizing the opening formed by the step (a), then, after the insulating film 50 is etched, the substrate 41 is etched to form two-stage recesses 44 and 45, and the upper recess is formed according to the dimensions of the insulating film 50. Since the dimensions of 44 are defined, the recess shape can be formed with good dimensional uniformity, and the element performance can be made uniform. Therefore, the non-defective rate can be improved, and the price of the element can be further reduced.

Embodiment 4 FIG. 8 is a cross-sectional view showing the main steps of one embodiment of a method for manufacturing a compound semiconductor field-effect transistor device having a two-stage recess type gate according to the third aspect of the present invention . The same components are shown, 51 is a PMGI, and 61 is a resist.

Next, the manufacturing method will be described. Figure (a)
As shown in FIG. 7, PMGI 51 is applied to a thickness of about 0.1 μm on a semiconductor substrate 41, and 1 W / W using light (Deep UV light) having a wavelength of 300 nm or less, particularly 280 nm.
The entire surface is exposed with an exposure energy of cm2. PMGI
Is not a scale that has the property of being difficult to mix with the resist for optical exposure used in the subsequent process, but has the property of being exposed to Deep UV light and being developed with an alkaline developer, like a general resist for optical exposure. It is. Next, in FIG. 2B, the optical resist 61 is set to about 0.5
It is applied to a thickness of μm, and then exposed / developed and patterned to have an opening of about 0.5 μm width serving as a gate pattern on the semiconductor substrate 41. At this time, PMGI51
Are developed with an alkali developer to open.

Next, as shown in FIG. 3C, the wafer 41 is etched by wet etching using tartaric acid or the like or by dry etching using a chlorine-based gas using the resist 61 as a mask, and has a depth of about 0.1 μm. A recess 47 is formed. Here, as described above, it is preferable to use dry etching from the viewpoint of improving dimensional controllability. Next, Figure (d)
As described above, the development is performed with an alkaline developing solution containing 2.38% by weight of TMAH (tetramethylammonium hydroxide). At this time, by performing the exposure under the above exposure conditions, it is possible to control the etching rate of the PMGI with respect to the alkali developing solution to a level of about 100 angstroms / sec. 8 μm), for example, 0.2 μm to 0.3
If you want to perform extra etching in the horizontal direction,
By immersing in an etchant for ~ 30 seconds for development, an opening of the PMGI resist 51 having a desired width can be obtained. Next, as shown in FIG. 3E, when the wafer 41 is etched with tartaric acid or the like using the resist 61 as a mask, the depth is reduced to about 0.5 mm.
Lower recess 45 of 3 μm and width of about 0.9 μm, and upper recess 4 of depth of about 0.1 μm and width of about 1.4 to 2.4 μm
4 are formed. The following is Ti, which is a metal for a gate electrode.
By depositing / Au or the like and performing the lift-off method, the structure of FIG. 6 having the recess gate electrode 43 having a gate width of about 0.5 μm and a gate height of about 0.5 μm is formed.

In this embodiment, in the method of manufacturing a compound semiconductor field-effect transistor element having a two-step recess, the upper-step recess size is defined by using a high controllability of the etching rate instead of the insulating film. That is, the etching rate with respect to the alkali developer is 100
Since PMGI that can be controlled to the angstrom / sec level is used, the dimensional uniformity of the recess shape can be greatly improved, and the device performance can be made uniform. As a result, the non-defective product rate can be improved and the device price can be greatly reduced. There is an effect that can be.

[0045] Example 5 Figure 9 shows a method of manufacturing a semiconductor device according to an embodiment of the invention of claim 5, in FIG, a semiconductor substrate of GaAs or the like 71, 78 formed on the semiconductor substrate 71 activity layer,
72 is an ohmic electrode forming source and drain electrodes, 75 is a lower first recess, 76 is an upper second recess, 77 is a Schottky metal formed on the lower recess 75, and 84 is a resist. The dimensions of each part in the figure are as follows: the active layer thickness is 2000 to 6000 angstroms, the opening width of the resist is 0.1 to 1 μm, and the difference between the upper opening width and the lower opening width is 0.1 to 0.3 μm. The depth of the first recess is 500 to 1500 angstroms, the depth of the second recess 6 is 1000 to 2000 angstroms,
The gate electrode width is the same as the upper opening width of the resist.

Next, the manufacturing method will be described. In FIG. 7A, a semiconductor active layer 7 formed on a semiconductor substrate 71 is formed.
After the source, drain, and ohmic electrodes 72 are formed on the gate electrode 8, a resist pattern 84 having an opening in a desired region where a gate Schottky electrode is to be formed is formed. Here, the resist pattern 84 has an overhang-shaped cross-sectional profile, that is, the upper opening A
And the lower opening B is widened.

Here, the overhang profile of the resist 14 can be easily obtained by using an image reversal resist or a negative resist as the resist. This is because, in these resists, the light hits the resist from above because the light hits the resist, the light attenuates in the film thickness direction,
This is because an overhang profile in which the lower opening is wide and the upper opening is narrow is easily obtained because the range of light is narrow in a deep place.

The overhang resist 8
When forming 4, for the purpose of improving the light shielding property,
If an arbitrary metal film is formed on the resist 84, the amount of the light reaching a deep place is reduced, and the overhang shape can be more easily obtained.

Next, by etching the semiconductor active layer 78 using light-assisted etching, a first recess structure 75 having a depth of about 0.05 to 0.15 μm as shown in FIG. At this time, since the resist 84 has an overhanging shape, the etching is performed for the upper opening width A of the resist 84. Here, as shown in FIG. 12, the light assisted etching is a liquid 9 having a property such that the semiconductor etching reaction proceeds only when excited by light.
1. For example, if the substrates 71 and 78 are GaAs, H2 S
O4 + H2 O, HCl aqueous solution, C6 H2 (OH) 2 (S
This is performed by irradiating light to the portion to be etched in a state of being immersed in O3 Na) 2 + H2 O (tartaric acid) or the like. Alternatively, as shown in FIG. 13, if a gas that allows the etching reaction of the semiconductor to proceed only when excited by light, for example, if the substrates 71 and 78 are made of GaAs, room temperature C
Etching can also be performed by placing a wafer in an l2 gas atmosphere 92 and irradiating the portion to be etched with light. In each case, the light used is at a wavelength of 70
Light less than or equal to 00 angstroms can be used.

Next, normal etching without using light is performed.
For example, sulfuric acid based etchant, H2 SO4: H2 O2: H
By performing the process on the substrate 71 using the overhanging resist 84 according to 2 O = 3: 1: 1,
As shown in (c), in addition to the first recess 75 which is further recessed in the depth direction, a second recess 76 having a depth of about 0.1 to 0.2 μm is obtained as a two-step recess. At this time, since the etching of the second recess is performed using the lower opening having a large opening width B of the resist 84 as a mask, the etching of the first recess is performed.
Etching is performed wider than the recess 75 of the first step. As a result, a two-step recess structure including the lower recess 75 and the upper recess 76 is obtained.

Next, as shown in FIG. 5D, a Schottky metal 77 is entirely deposited and lift-off is performed to form a gate electrode 73, thereby obtaining a desired FET as shown in FIG.

In the manufacturing method of this embodiment, after the first recess 75 is formed by using the optically assisted etching, the second recess 76 is formed by using the wet etching.
Is formed, the width of the second recess 76 is determined by the width B of the lower opening of the photoresist pattern 84 and the property of isotropic etching of wet etching, and the second recess 76 is side-etched to form the second recess. There is no variation in the second recess shape as in the obtaining method. Also figure
The width of the first recess 75 widens in the steps of (b) to (c) in the lateral direction of the wet etching. Before the widening, the width of the first recess 75 is defined by the light-assisted etching. Since the extent of the spread is also determined by the type of etching, there is almost no variation in the recess shape due to the spread. Therefore, in this embodiment, a two-stage recess structure can be formed stably between lots and between wafers, thereby achieving high uniformity of element characteristics and reduction of element price.

[0053] Example 6 10 show a manufacturing method of a semiconductor device according to an embodiment of the invention of claim 6, performed before the formation of the first recess 75 by the light-assisted etching in the above Example 5, followed usually In the sixth embodiment, as shown in FIG. 10, the formation of the second recess 76 by wet etching is performed first (see FIG. 10).
(b)), and then the first recess 75 is formed by light-assisted etching (FIG. (c)). In this embodiment, as in the fifth embodiment, the width of the second recess is determined by the width B of the lower opening of the photoresist pattern 84 and the proportion of the lateral etching spread by the wet etching. No variation occurs. Therefore, as in the fifth embodiment, the two-step recess structure can be formed uniformly and stably between lots and wafers, and the device characteristics can be made more uniform and the device price can be reduced. Further, in this embodiment, since the lower first recess is formed after the upper second recess is formed, the width of the lower recess 75 is the same as the upper opening width A of the photoresist pattern 84. And the two-step recess shape can be formed more stably.

[0054] Example 7 FIG. 11 illustrates a method of manufacturing a semiconductor device according to an embodiment of the invention of claim 7, the present embodiment 7, to obtain the overhang resist profile shape in (a) of FIG. 9 and 10 Method. As shown in FIG. 11A, first, an insulating film 90 having a tapered shape is formed.
As shown in (b), a resist pattern 84 having an opening is provided in a portion of the insulating film 90. Next, 150-200
By performing the heat treatment at a temperature of ° C., the resist 84 is thermally sagged, and the gap between the resist 84 and the insulating film 90 is filled, thereby obtaining the state shown in FIG. Next, the insulating film 90 is removed by an appropriate etching method, for example, immersion in a 30% aqueous HF solution to obtain the state shown in FIG.

[0055]

As described above, according to the present invention,
The two-step recess region is divided into an upper recess region and a lower recess region.
Since the two recesses are formed in two steps, the width of the lower recess is not changed as in the conventional formation of the two recesses, so that the two recesses can be formed stably. In addition, a T-type gate electrode can be easily obtained in forming the gate electrode, and a semiconductor device having stable performance can be manufactured with high yield.

In the method for manufacturing a compound semiconductor device having a two-step recess, the insulating film defining the upper recess dimension is etched to a desired size, or the etching rate is changed by exposure instead of the insulating film. PMGI, which can improve the controllability of the device, is adopted, so that the dimensional uniformity of the recess shape can be improved, the device performance can be made uniform, and thereby the yield rate can be improved, and the price of the device can be greatly reduced. This has the effect.

Further, according to the method of manufacturing a semiconductor device according to the present invention, the first recess of the two-stage recess structure is formed by light-assisted etching, so that the second recess is formed by using the side etching of the insulating film. There is an effect that the two-step recess structure can be manufactured with high uniformity without causing variation as in the conventional method of forming.

[Brief description of the drawings]

[1] Figure 1 (a) ~ FIG 1 (d) is a sectional views showing an example (Example 1) of the method of manufacturing the semiconductor device according to claim 1 of the present invention.

FIGS . 2 (a) to 2 (d) show FIGS. 1 (a) to 1 (d) of the first embodiment .
It is a process sectional view following 1 (d).

FIGS . 3 (a) to 3 (d) are process sectional views showing one embodiment (embodiment 2) of the method for manufacturing a semiconductor device according to claim 2 of the present invention.

4 (a) to 4 (c) show FIGS. 3 (a) to 3 (d) of the second embodiment .
It is a process sectional view following 3 (d).

5 (a) to 5 (c) show FIGS. 4 (a) to 4 (d) of the second embodiment .
It is a process sectional view following 4 (c).

[6] The method of Examples 3 and 4 of the present invention, a cross-sectional view of a double recessed gate MOSFET is a compound semiconductor device obtained by the contact and the conventional example 2 method.

7 is a process cross-sectional view showing an embodiment (Embodiment 3) of the manufacturing method of the semi-conductor device of the present invention.

FIG. 8 is a process sectional view showing one embodiment (Embodiment 4) of the method of manufacturing a semiconductor device according to claim 3 of the present invention;

FIG. 9 is a process sectional view showing one embodiment (Embodiment 5) of the method for manufacturing a semiconductor device according to claim 5 of the present invention;

FIG. 10 is a process sectional view showing one embodiment (Embodiment 6) of the method of manufacturing a semiconductor device according to claim 6 of the present invention;

FIG. 11 is a process cross-sectional view showing a manufacturing process for manufacturing the overhang-shaped resist patterns of Examples 5 and 6.

FIG. 12 is a diagram showing an example of optically assisted etching in Examples 5 and 6.

FIG. 13 is a diagram showing an example of light-assisted etching in Examples 5 and 6.

14 (a) to 14 (c) are cross-sectional views showing steps of a method for manufacturing a conventional semiconductor device.

FIGS . 15 (a) to 15 (c) are cross-sectional views showing a method of manufacturing a conventional semiconductor device, following FIGS . 6 (a) to 6 (c).

FIG. 16 is a cross-sectional view of a main manufacturing step in another example of the conventional method of manufacturing a semiconductor device.

FIG. 17 is a sectional view of a main manufacturing step in another example of the conventional method of manufacturing a semiconductor device.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mitsunori Nakatani 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. Optical and Microwave Device Laboratory (72) Inventor Takahide Ishikawa 4 Mizuhara, Itami-shi, Hyogo 1-chome, Mitsubishi Electric Corp. Optical and Microwave Device Laboratory (72) Inventor Yutaka Nagai 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corp. Optical and Microwave Device Laboratory (56) References JP-A-3-227528 (JP, A) JP-A-4-137737 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/812

Claims (7)

(57) [Claims] 1. A method of manufacturing a two-step recessed field-effect transistor having a gate electrode in a lower recess in a two-step recess, wherein a photoresist is applied on a semiconductor active layer formed on a semiconductor substrate and patterned. Forming an opening except for a position where a gate electrode is formed at a position where an upper recess is formed, and etching the semiconductor active layer through the opening using the photoresist as a mask to form a dummy gate having a desired size. Forming recesses corresponding to both sides of the upper recess so as to leave the center in the center thereof; enclosing an insulator in the two recesses of the upper recess; an upper recess and a semiconductor active layer enclosing the insulator. Forming an opening wider than the dummy gate by applying and patterning a photoresist on the surface comprising Dry etching through the opening using photoresist as a mask to partially remove the insulator in the two recesses; and etching the dummy gate and the semiconductor layer therebelow using the remaining insulating film as a mask to form a lower recess. Forming a two-stage recess by forming a gate electrode, and vacuum-depositing a gate electrode metal in a lower-stage recess region of the two-stage recess, and lifting off to form a gate electrode. Manufacturing method. 2. A method of manufacturing a two-stage recess type field effect transistor having a gate electrode in a lower stage recess of a two-stage recess, wherein a dummy gate made of an insulating film is formed on a semiconductor active layer formed on a semiconductor substrate. Forming a sidewall made of an insulating film of a material different from that of the dummy gate on both sides of the dummy gate; applying a photoresist on the semiconductor active layer on both sides of the sidewall, and selecting only the sidewall. Forming a recess by etching the semiconductor active layer through the opening using the photoresist and the dummy gate as a mask to form recesses on both sides of the upper recess; After coating a photoresist on the semiconductor active layer including the photoresist, a dummy gate is selected using the photoresist as a mask. Forming a lower recess by etching the semiconductor active layer to form a lower recess, vacuum depositing a gate electrode metal in the lower recess region, and lifting off the gate electrode by lift-off. Forming a semiconductor device. 3. A method of manufacturing a two-stage recess type field-effect transistor having a gate electrode in a lower stage recess of a two-stage recess , wherein a PMGI (polymethyl glue) is formed on a compound semiconductor substrate.
(Tar / imide) coating and exposure, and an opening corresponding to the size of the lower recess is formed on the substrate.
Forming a resist pattern having the above-mentioned PMGI
PMGI pattern with the same degree of opening
Forming a turn, etching the substrate using the PMGI as a mask,
Forming a hole, and developing the opening of the PMGI to form the opening
Expanding the method to a size corresponding to the upper recess, and etching the substrate using the PMGI as a mask to form the upper recess.
And a lower recess with a greater depth 2
Forming a step recess and using the resist on the lower recess of the two-step recess
Forming a gate electrode by vapor deposition lift-off.
A method for manufacturing a semiconductor device. 4. A method of manufacturing a two-stage recess type field effect transistor having a gate electrode in a lower stage recess of a two-stage recess, wherein the first recess as the lower stage recess is formed by an optically assisted etching.
It is characterized by using a chin to obtain a two-step recess structure.
Semiconductor device manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 4, wherein
Forming a resist pattern having an overhang shape in an opening forming portion thereof on a semiconductor active layer on a semiconductor substrate, and then forming the resist pattern using optically assisted etching.
D the semiconductor active layer an upper opening of the over in as mask
Etching to obtain a first recess, followed by etching using only a chemical reaction without using light.
Using the lower portion of the opening of the resist as a mask,
To obtain the first recess with a greater depth
And a method of manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 4 , wherein the semiconductor device has an opening formed on a semiconductor active layer of a semiconductor substrate.
For forming a resist pattern having a hung shape
And then etching by chemical reaction without light
By using the lower part of the opening of the resist as a mask,
A step of obtaining a second recess and photo-assisted etching are performed on the upper portion of the opening of the resist.
Obtaining a first recess by performing as a mask. 7. The method of manufacturing a semiconductor device according to claim 5 , wherein the step of forming the overhang-shaped resist includes the step of forming an insulating film having a tapered cross-sectional shape , Resist pattern with openings
Forming a resist, and heating the resist to generate heat sag, thereby
A method of manufacturing a semiconductor device, comprising: a step of pressing the insulating film on a side surface thereof; and a step of etching and removing the insulating film .