JPH0119656B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse cycle discrimination circuit that discriminates when the cycle of an input pulse suddenly increases.

When measuring various physical quantities such as temperature, pressure, or rotation speed, these physical quantities are converted into corresponding pulse periods and extracted. The pulse signal extracted in this way is
Changes in physical quantities are detected by detecting periodic changes, but there may be dangers if physical quantities change rapidly over a predetermined range. Therefore, it is necessary to perform rapid detection.

In this case, conventionally commonly used equipment measures the generation period of each pulse,
A change characteristic is calculated by calculating the change in this measured value using a microcomputer or the like, and a case where this change characteristic exceeds a predetermined value is determined as an abnormality.

However, in determining the pulse period using the above-described configuration, the change characteristics of the pulse period are calculated by calculation, and sudden changes in the pulse period are detected from this calculated characteristic. This cannot be done quickly, and the equipment becomes extremely expensive.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a pulse period determination circuit which has a simple configuration and is capable of quickly determining sudden changes in the pulse period.

In order to achieve such an object, the present invention determines a case where the pulse period becomes longer than a predetermined pulse period range as a sudden change exceeding a fixed value. Hereinafter, the pulse period discrimination circuit according to the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pulse period discrimination circuit according to the present invention. In the figure, reference numeral 1 denotes a counter which takes in a clock pulse A through a clock input terminal C, and takes in an input pulse B for discrimination through a reset input terminal R. In this counter 1, input pulse B
The period of is counted by clock pulse A,
The time when the count value of clock pulse A reaches an arbitrary value is set as Q _x . In addition, Q _y is counted from the set value of Q _x , and when the count value exceeds the predetermined pulse period range and the pulse period becomes longer, it is determined that the period has suddenly changed beyond the specified value. It is set to a value one count before the count value corresponding to the length. The counter 1 is configured to generate output signals C ₁ and C ₂ from output terminals Q _x and Q _y , respectively, when the count values reach Q _x and Q _y .
2 is an OR gate that inputs the output signals C ₁ and C ₂ of counter 1; 3 is a D-type flip-flop circuit that takes in the output of OR gate 2 through input terminal D, and inputs the input pulse B to clock input terminal C; Import via. 4 is a NAND gate which inputs the signal output from the reset output terminal of the flip-flop circuit 3 and the output signal _C2 generated from the counter 1, and 5 is an R-S which receives the output signal of the NAND gate 4 via the set input terminal S. This is a type of flip-flop circuit.

In the pulse period discrimination circuit configured in this manner, the period _T is input to the reset input terminal R of the counter 1 as shown in _{FIG .}
When input pulses B ₁ to B ₄ that change as (T ₁ < T ₂ < T ₃ ) are supplied, the counter 1 counts the number of clock pulses A between the occurrences of each input pulse B and calculates the number of clock pulses A between the occurrences of each input pulse B. Output signals C ₁ and C ₂ are generated every time the count value reaches Q _x and Q _y . However, in this case, since the period T ₁ is a value at which the count value does not reach Q _x , the output signals C ₁ and C ₂ are as shown in Fig. 2b.
The "L" state continues as shown in c. Then the period
T ₂ means that the count value of counter 1 is greater than or equal to Q _x and Q _y
Since the value is within the following range, the count value from counter 1 reaches time t ₁ to t in the period from the time when the count value reaches _Q An output signal _C1 is generated as shown between ₂ and 3. This output signal _C1 is supplied to the D input terminal of the flip-flop circuit 3 via the OR gate 2, and when the next input pulse _B3 is supplied to the clock input terminal C, it is set, and its reset output becomes the second It is inverted to "L" as shown in Figure c. In this case, since the output signal _C2 of the counter 1 continues to be in the "L" state as shown in FIG. circuit 5
remains in the reset state.

Next, in the period T ₃ between the input pulses B ₃ and B ₄ shown in FIG. 2a, first, the output terminal Q _x of the counter 1
2b, an output signal _C1 is generated between the times _t3 and _t4 , and subsequently from the output _Qy at the time _t4 in FIG.
An output signal _C2 shown between ~ _t5 is generated. but,
Since the flip-flop circuit 3 maintains the set state, its reset output is "L" as shown in FIG. 2c, and therefore the output signal _C2 of the counter 1 becomes as shown in FIG. 2d. Even if it is reversed to "H", the output of the NAND gate 4 continues to be in the "H" state as shown in FIG. 2e. Therefore, in this way, the pulse period is equal to the count value of counter 1.
In response to a change in the pulse period in which the pulse period becomes longer after generating a pulse in the range _{of Q} The discrimination signal F shown in FIG. 2 is no longer generated as shown in FIG. 2f. In other words, the period extension of the input pulse B in this case is that after the input pulse _B3 of the period _T2 belonging to the range of the count value Q _x to Q _y is generated, the input pulse B3 of the period T ₃ exceeding the count value Q _y is generated. With the generation of pulse _B4 , the generation of discrimination signal F is stopped, assuming that the change in the period _T1 to _T3 of input pulse B has gradually become longer.

Next, as shown in FIG. 3a, if the period T of the input pulse B falls below the count value Q _x without generating an input pulse with a period falling within the range of the count value Q _{x to Q y of} the counter 1. Input pulse with period T ₁
When the count value suddenly changes from B ₁ and B ₂ to a cycle exceeding Q _y , first, at time t ₁ when the count value of counter 1 reaches Q _x , the output signal C ₁ as shown in FIG. is inverted to "H". This output signal _C1 is supplied to the flip-flop circuit 3 via the OR gate 2, but since the input pulse B is not supplied during the "H" period of the output signal _C1 , the flip-flop circuit 3 is in the reset state. continue. Next, when the count value of counter 1 reaches Q _y , _{the output signal C 2 shown} in FIG. If it does not occur,
The output of the NAND gate 4 is inverted to "L" as shown in FIG. 3e by the signal output from the reset output terminal of the flip-flop circuit 3 shown in FIG. _3c and the output signal C2 of the counter 1. In this way, when the output of the NAND gate 4 becomes "L", the flip-flop 5 is set and outputs the discrimination signal F indicating that the period of the input pulse B has suddenly become longer until a reset signal is supplied. I will continue.

Therefore, in a circuit configured in this way, if the period of the input pulse B does not fall within the range of the count value Q _x to Q _y of counter 1 but suddenly changes to a period within the range exceeding the count value Q _y . Only in this case, a sudden extension of the input pulse period is detected and a discrimination signal F is generated.

In the above embodiment, a case has been described in which the output of the NAND gate 4 is latched in the flip-flop 5 to maintain the output of the discrimination signal F, but even if the discrimination signal is generated only momentarily, If it is good, the output of the NAND gate 4 may be used as a discrimination signal.

As explained above, the pulse period discrimination circuit according to the present invention stops generation of the discrimination signal as a gradual extension of the pulse period when the input pulse period becomes longer after passing through a predetermined range. If the pulse period becomes longer than a predetermined range, a discrimination signal is generated as a sudden change in the pulse period. Therefore, rapid extension of the input pulse period can be detected quickly, and the present invention has an excellent effect of being able to perform reliable detection despite having an extremely simple configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the pulse period discrimination circuit according to the present invention, FIG. 2 a to f, and FIG. 3 a to
f is an operation waveform diagram of each part of the circuit diagram shown in FIG. 1; 1... Counter, 2... Or gate, 3, 5...
...Flip-flop circuit, 4...NAND gate.

Claims (1)

[Claims] 1. Counts the number of clock pulses between input pulses, outputs a first pulse signal _C1 when the number of clock pulses reaches an arbitrary first value, and sets the number of clock pulses to the arbitrary first value. When counting the number corresponding to a predetermined input pulse period from the point in time, the second
a counter that outputs a pulse signal _C2 , and a flip-flop circuit that is set when the pulse signal _C1 or _C2 matches the input pulse;
A pulse period discrimination circuit comprising: a gate circuit that detects the pulse signal _C2 generated from the counter at the time of resetting the flip-flop circuit and generates a discrimination signal indicating a sudden increase in the input pulse period.