JP3136193B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly to a staggered thin film transistor used as a switching element of an active matrix type liquid crystal display device and a method of manufacturing the same. The active matrix type display device is used as a thin type information terminal display device together with a simple matrix type display device, and liquid crystal is used as a display medium.

Comparing the characteristics of the two, the active matrix type liquid crystal display device can perform the same operation as driving a large number of pixels independently, so that the number of lines increases with an increase in display capacity. Does not cause a problem such as a decrease in driving duty ratio as in a simple matrix type liquid crystal display device, a decrease in contrast and a decrease in viewing angle. For this reason, the active matrix type liquid crystal display device can provide a color display comparable to that of a cathode ray tube (CRT), and is expanding its use as a thin flat display.

Accordingly, a thin film transistor (TFT) used in such an active matrix type liquid crystal display device.
There is a demand for a cost reduction by improving characteristics of a thin film transistor and simplifying a manufacturing process.

[0004]

2. Description of the Related Art FIGS. 7A and 7B show sectional structures of two conventional staggered TFTs, and FIGS. 8A and 8B show current characteristics thereof. 7A, a source electrode 62a and a drain electrode 62b are formed on a glass substrate 60 so as to face each other. These source and drain electrodes 62a and 62b are made of ITO, respectively.
(Indium Tin Oxide) transparent electrode layers 64a, 64b and the ITO transparent electrode layer 64
a, P (phosphorus) doped n + type a formed on 64b
-Si (amorphous silicon) contact layer 66a,
66b.

Here, the ITO transparent electrode layers 64a, 64b
The source and drain electrodes 62a and 62b composed of the n + -type a-Si contact layers 66a and 66b are formed by a single photolithography process after sequentially laminating the ITO layer and the n + -type a-Si layer. Therefore, the n + type a
-Si contact layers 66a, 66b do not overhang ITO transparent electrode layers 64a, 64b,
It has a step-like structure in which the O transparent electrode layers 64a and 64b are partially exposed.

Further, source and drain electrodes 62a, 62
An intrinsic i-type a-Si operating layer 68 is formed on the glass substrate 60 and between the source and drain electrodes 62a and 62b. Therefore, this i-type a-Si
The operation layer 68 includes n + type a-Si contact layers 66a and 66
6b, and is in direct contact with the ITO transparent electrode layers 64a, 64b.

Further, a gate electrode 72 made of Al (aluminum) is formed on the i-type a-Si operation layer 68 via a gate insulating film 70 made of a SiN film (silicon nitride film). On the other hand, in FIG. 7B, similarly to FIG. 7A, a source electrode 74a and a drain electrode 74b are formed on the glass substrate 60 so as to face each other.
It comprises O transparent electrode layers 76a and 76b and n + type a-Si contact layers 78a and 78b.

However, the source and drain electrodes 74a and 74b composed of the ITO transparent electrode layers 76a and 76b and the n + -type a-Si contact layers 78a and 78b are used for depositing and patterning the ITO layer and for forming the n + -type a-Si layer. Is formed by two photolithography steps of depositing and patterning. Therefore, the n + -type a-Si contact layers 78a and 78b overhang the ITO transparent electrode layers 76a and 76b, and
a, 76b are completely covered.

Further, source and drain electrodes 74a, 74
An intrinsic i-type a-Si operating layer 68 is formed on the glass substrate 60 and between the source and drain electrodes 74a and 74b. Therefore, this i-type a-Si
The operation layer 68 includes n + type a-Si contact layers 78a, 78
8b, but not directly with the ITO transparent electrode layers 76a, 76b.

Further, similarly, on the i-type a-Si operation layer 68, a gate electrode 7 is interposed via a gate insulating film 70.
2 are formed. Next, the drain current-gate voltage characteristics of the two types of staggered TFTs of FIGS. 7A and 7B are shown in FIGS. 8A and 8B, respectively. As is clear from the comparison between the two, the current characteristics of the staggered TFT of FIG. 7A are more deteriorated than those of the staggered TFT of FIG. 7B. The reason for this is that the staggered TF shown in FIG.
At T, the I and I of the source and drain electrodes 62a and 62b
The TO transparent electrode layers 64a and 64b are i-type a-Si operation layers 6.
The barrier caused by direct contact with the gate electrode 8 increases the potential of the back channel portion of the i-type a-Si operation layer 68 farther from the gate electrode 72, so that the channel conductance is reduced and the ITO transparency is reduced. In (indium), O (oxygen) in the electrode layers 64a and 64b
It is conceivable that the impurity such as diffuses into the i-type a-Si operation layer 68 to increase the local level density in the i-type a-Si operation layer 68, so that the channel conductance decreases.

[0011]

As described above, in the above-mentioned conventional stagger type TFT, if the source and drain electrodes are formed by a single photolithography step in order to reduce the cost by simplifying the steps, As a result, the ITO transparent electrode layer of the drain electrode comes into direct contact with the i-type a-Si operating layer, resulting in a decrease in TFT characteristics. On the other hand, in order to prevent the ITO transparent electrode layers of the source and drain electrodes from coming into direct contact with the i-type a-Si working layer in order to improve the TFT characteristics, two photo- A lithography process was required.

Accordingly, the present invention provides a TFT that can form a source and a drain electrode in one photolithography process without deteriorating the TFT characteristics, thereby realizing an improvement in TFT characteristics and a cost reduction by simplifying the process. And a method for producing the same.

[0013]

FIG. 1 is a sectional view of a TFT for explaining the principle of the present invention. On a glass substrate 10, a source electrode 12a and a drain electrode 12b are formed facing each other. These source and drain electrodes 12
a and 12b are ITO transparent electrode layers 14a and 1b, respectively.
4b and n + -type a-Si contact layers 16a and 16b formed on the ITO transparent electrode layers 14a and 14b.

Here, the ITO transparent electrode layers 14a, 14b
The source and drain electrodes 12a and 12b composed of the n + -type a-Si contact layers 16a and 16b are formed by a single photolithography process after sequentially laminating an ITO layer and an n + -type a-Si layer. Therefore, the n + type a
-Si contact layers 16a, 16b do not overhang ITO transparent electrode layers 14a, 14b,
It has a stepped structure in which the O transparent electrode layers 14a and 14b are partially exposed.

The source and drain electrodes 12a and 12a
b and the glass substrate 10 between the source and drain electrodes 12a and 12b, the operating semiconductor layer 1 made of an a-Si layer
8 are formed. And this operation semiconductor layer 18
The present invention is characterized in that it has a two-layer structure of an n- type a-Si operating layer 20 having a lower impurity concentration than the n + type a-Si contact layers 16a and 16b and an intrinsic i-type a-Si operating layer 22. There is a feature.

Accordingly, the n − type aS of the operating semiconductor layer 18 is
i operation layer 20 includes source and drain electrodes 12a and 12b
Ohmic contact with the n + -type a-Si contact layers 16a, 16b, and the ITO transparent electrode layers 14a, 14b.
b and the i-type a-Si operating layer 22 and the ITO
There is no direct contact between the transparent electrode layers 14a and 14b.

Further, a gate electrode 26 is formed on the operating semiconductor layer 18 via a gate insulating film 24. It is desirable that the layer thickness of the n − -type a-Si operation layer 20 constituting the operation semiconductor layer 18 be 20 nm or less.
The n + -type a-Si contact layers 16a and 16b constituting the source and drain electrodes 12a and 12b have an n-type impurity content of 1% or more.
Is desirably 1% or less. Furthermore, the content of the n-type impurity in the n − -type a-Si operation layer 20 may be gradually or stepwise reduced from the substrate side.

[0018]

FIG. 2A is an energy band diagram of the operating semiconductor layer of the TFT of FIG. 1, and FIG. 2B is an energy band diagram of the operating semiconductor layer of the conventional TFT. FIG. 7 above
As shown in FIG. 2B, when the ITO transparent electrode layers of the source and drain electrodes are in direct contact with the i-type a-Si working layer as in the conventional staggered TFT shown in FIG. , I-type a-Si in contact with ITO transparent electrode layer
The conduction band Ec of the working layer is raised to create a barrier. As a result, the potential of the back channel portion of the i-type a-Si operating layer increases, and thus the channel conductance of the entire i-type a-Si operating layer decreases.

On the other hand, according to the present invention, since the operating semiconductor layer 18 in contact with the ITO transparent electrode layers 14a and 14b is an n- type a-Si operating layer 20 doped with an n-type impurity, FIG. As shown in (), the Fermi surface Ef of the operating semiconductor layer 18 approaches the conduction band Ec. As a result, n-
Type a-Si working layer 20 and ITO transparent electrode layers 14a, 14
The barrier potential due to the junction with b hardly occurs, and the channel conductance does not decrease due to the back channel portion potential.

The diffusion of impurities such as In and O is blocked by n-type impurities, for example, P contained in the n − -type a-Si operation layer 20. Further, the operation semiconductor layer 18 has a two-layer structure of an n-type a-Si operation layer 20 and an i-type a-Si operation layer 22, and the i-type a-S on the gate insulating layer side.
Since the i operation layer 22 effectively acts as a channel,
There is no reduction in on-current.

The thickness of the n- type a-Si operating layer 20 forming the operating semiconductor layer 18 is set to 20 nm or less, and the n + type a-Si forming the source / drain electrodes 12a and 12b is formed.
By making the content of n-type impurities in the -Si contact layers 16a and 16b 1% or more, by making the content of n-type impurities in the n- type a-Si operation layer 20 less than 1%, An off current sufficient to drive the liquid crystal can be obtained.

The n-type a-Si operation layer 20 and the i-type a-Si operation layer 20 are reduced by gradually or stepwise decreasing the content of the n-type impurity in the n-type a-Si operation layer 20 from the substrate side.
Since the gap of the conduction band Ec at the junction with the Si operation layer 22 can be reduced, the off current can be further reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a specific description will be given based on the illustrated embodiment. FIG. 3 shows a staggered TF according to an embodiment of the present invention.
It is sectional drawing which shows T. 80 n film thickness on glass substrate 30
m Cr light-shielding film 32 is formed.
On the Cr light-shielding film 32, an insulating film 34 made of a 300-nm-thick SiN film is formed. On the insulating film 34, ITO layers 38a and 38b are formed facing each other, and a part of each of the ITO layers 38a and 38b has an n + -type a-Si contact layer 40 having a P concentration of 1% or more.
a and 40b are formed.

Thus, the ITO layers 38a, 38b and n
Step-shaped source and drain electrodes 44a and 44b composed of + type a-Si contact layers 40a and 40b are formed. In this stepped structure, the ITO layer 38
The lengths of the portions of the regions a and 38b facing each other that are not covered by the n + -type a-Si contact layers 40a and 40b are about 100 nm.

The source and drain electrodes 44a, 44
b and the insulating film 34 between the source and drain electrodes 44a and 44b, the P impurity concentration is less than 0.1% and the thickness is 10 n.
An n-type a-Si operating layer 46 of m and an intrinsic i-type a-Si operating layer 48 are stacked, and an operating semiconductor layer 50 is formed.
Is composed. Therefore, the ITO layer 38 not covered by the n + type a-Si contact layers 40a, 40b
The a and 38 b are in contact with the n − type a-Si operation layer 46 of the operation semiconductor layer 50, and do not directly contact the i-type a-Si operation layer 48. The operating semiconductor layer 50 is made of Cr
The Cr light shielding film 32 is formed above the light shielding film 32.
This prevents external light from entering.

On the active semiconductor layer 50, a thickness of 30
Through a gate insulating film 52 made of a 0 nm SiN film,
A gate electrode 54 made of an Al film having a thickness of 500 nm is formed. Thus, a stagger type TFT element is formed. Next, a method of manufacturing the staggered TFT shown in FIG. 3 will be described with reference to FIGS.

On a glass substrate 30, a sputtering method is used.
After depositing a Cr film with a thickness of 80 nm,
Patterned by lithography and Cr light-shielding film 3
Form 2 Subsequently, the entirety is formed using a plasma CVD method.
An insulating film 34 made of a 300 nm thick SiN film is formed on the surface.
To achieve. Next, a film thickness of 50 n is formed on the entire surface by sputtering.
m of the ITO layer, and the film thickness is formed by using the plasma CVD method.
30 nm n + type a-Si layer and 70 nm thick SiO
_TwoThe films are respectively laminated. Next, normal photolithography
Patterning of source and drain shapes by ruffy method
Using the patterned resist 36 as a mask,_TwoHook the membrane
Wet etching mainly containing an acid is performed, and n + type a
-Si layer is CCl _FourDry etchin whose main component is gas
And the ITO layer is wetted mainly with hydrochloric acid and nitric acid.
Etching to form source and drain shaped ITO
Layers 38a and 38b, n + type a-Si contact layer 40
a, 40b, SiO_TwoForm films 42a and 42b respectively
I do. At this time, SiO_TwoThe membranes 42a and 42b are
Side-etching in lateral direction by jet etching
(See FIG. 4A).

Next, after removing the resist 36, the Si
Again using the O ₂ films 42a and 42b as a mask,
By dry-etching the Si contact layers 40a and 40b using CCl ₄ as a main component gas, the upper surfaces of the ITO layers 38a and 38b are partially exposed. Here, by appropriately selecting the etching conditions, the ITO layer 38a,
The length t of the exposed portion of 38b is set to about 100 nm. Thus, source and drain electrodes 44a and 44b having a step-like structure of the ITO layers 38a and 38b and the n + -type a-Si contact layers 40a and 40b are obtained (see FIG. 4B).

Next, after removing the SiO ₂ films 42a and 42b by an etching ant containing hydrofluoric acid as a main component, a 0.1% PH in SiH ₄ gas is used by a plasma CVD method.
₃ introduces a P-doped thickness of 10n.
The m of the n- type a-Si active layer 46, and by the SiH ₄ gas, the thickness of 30nm intrinsic i-type a-Si
The operation layers 48 are formed continuously without breaking the vacuum. Thus, the n− type a-Si operation layer 46 and the i−type
An a-Si operation semiconductor layer 50 having a two-layer structure including the Si operation layer 48 is obtained.

Subsequently, without breaking the vacuum, the plasma C
After depositing a gate insulating film 52 made of a 300-nm-thick SiN film by using the VD method, a gate electrode 54 consisting of an 500-nm-thick Al film is deposited by using a sputtering method (see FIG. 5A). ). Next, after patterning the gate electrode 54 by a normal photolithography method, the gate insulating film 52, the a-Si operating semiconductor layer 50 and the n + -type a-Si contact layer 40a are formed with the same resist pattern.
40b is dry-etched. Thus, the staggered TFT device shown in FIG. 3 is formed (see FIG. 5B).

Next, the characteristics of the staggered TFT device thus formed are shown in the graph of FIG. That is, in the drain voltage V _D = 5V, showing a drain current I _D characteristics when changing the gate voltage V _G at the solid line. For comparison, the operating semiconductor layer is replaced by an intrinsic i
The case where only the type a-Si operation layer is formed is indicated by a broken line. As is apparent from the comparison between the two, the staggered TFT device according to the present embodiment has an ON current improved by one digit or more.

As described above, according to this embodiment, the operating semiconductor layer 50 has a two-layer structure of the n-type a-Si operating layer 46 and the i-type a-Si operating layer 48, The n − type a-Si operation layer 46 is formed by the source and drain electrodes 44.
The i-type a-Si operating layer 48 which contacts the ITO layers 38a and 38b of the
By not contacting the TO layers 38a, 38b, the barrier potential due to the junction between the operating semiconductor layer 50 and the ITO layers 38a, 38b hardly occurs, and the channel conductance does not decrease due to the back channel potential. Is improved by one digit or more.

The n-type a-Si of the operating semiconductor layer 50
The thickness of the operation layer 46 is 10 nm, and the content of the P impurity in the n + -type a-Si contact layers 40a and 40b of the source and drain electrodes 44a and 44b is 1% or more. When the content of the n-type impurity in the type a-Si operation layer 46 is less than 1%, an off current sufficient to drive the liquid crystal can be obtained.

In the above embodiment, the operating semiconductor layer 50 has a two-layer structure of the n-type a-Si operating layer 46 and the i-type a-Si operating layer 48. Layer 46
Do not contain a certain concentration of P impurities
By reducing the impurity concentration stepwise from the insulating film 34 side, a multi-layered operating semiconductor layer may be used instead of the two-layered structure.

In this case, PH introduced into SiH ₄ gas
_The amount of ₃ is 0.1%, 0.05%, 0.01%, 0.005%,
By gradually decreasing the P-doping amount to 0.001%, an n-type a-Si working layer having a multilayer structure in which the P doping amount decreases stepwise can be obtained. Furthermore, the concentration of the P impurity contained in the n − -type a-Si operation layer may be continuously reduced instead of being stepwise. In each case, a sufficiently low off-state current is shown as in the case of the above embodiment.

In the above embodiment, P is used as the n-type impurity. However, the present invention is not limited to this.
(Arsenic) or the like.

[0037]

As described above, according to the present invention, the source electrode and the drain electrode of the thin film transistor have the transparent electrode layer mainly composed of ITO and the n-type contact semiconductor layer, and the operating semiconductor layer has at least A transparent electrode containing ITO as a main component by having an n ⁻ -type semiconductor layer having an impurity concentration lower than that of the n-type contact layer provided in a portion in contact with the transparent electrode layer and an i-type semiconductor layer Even when the layer is in direct contact with the operating semiconductor layer, a decrease in TFT characteristics can be prevented.

Further, a step of sequentially laminating a transparent electrode layer mainly composed of ITO, an n-type contact semiconductor layer and an insulating layer on the substrate, and wet-etching the insulating layer into a predetermined shape to form an n-type contact semiconductor layer Dry-etch,
After the transparent electrode layer is wet-etched, the n-type contact semiconductor layer is again dry-etched using the insulating layer side-etched by the wet etching as a mask, and includes a transparent electrode layer and an n-type contact semiconductor layer having a step-like structure. Forming a source electrode and a drain electrode, and, after removing the insulating layer, sequentially stacking an n ⁻ -type semiconductor layer having a lower impurity concentration than the n-type contact layer, an i-type semiconductor layer, a gate insulating film, and a gate electrode. Etching the gate electrode, the gate insulating film, the i-type semiconductor layer and the n ⁻ -type semiconductor layer to form a gate electrode on the operating semiconductor layer including the n ⁻ -type semiconductor layer and the i-type semiconductor layer via the gate insulating film. And forming a source electrode and a drain electrode in one photolithography step. FT characteristics can be obtained.

Therefore, it is important to contribute to realizing cost reduction by improving TFT characteristics and simplifying the process.

[Brief description of the drawings]

FIG. 1 is a sectional view of a TFT for explaining the principle of the present invention.

FIG. 2 is an energy band diagram of an operating semiconductor layer of the TFT of FIG.

FIG. 3 is a cross-sectional view illustrating a staggered TFT according to an embodiment of the present invention.

FIG. 4 is a process chart (1) for explaining a method for manufacturing the staggered TFT shown in FIG.

FIG. 5 is a process chart (part 2) for explaining the method for manufacturing the staggered TFT shown in FIG.

FIG. 6 is a graph showing current characteristics of the staggered TFT shown in FIG.

FIG. 7 is a cross-sectional view showing a conventional staggered TFT.

FIG. 8 is a graph showing current characteristics of the staggered TFT shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Glass substrate 12a ... Source electrode 12b ... Drain electrode 14a, 14b ... ITO transparent electrode layer 16a, 16b ... n + type a-Si contact layer 18 ... Operating semiconductor layer 20 ... n- type a-Si operating layer 22 ... i Type a-Si working layer 24 ... Gate insulating film 26 ... Gate electrode 30 ... Glass substrate 32 ... Cr light shielding film 34 ... Insulating film 36 ... Resist 38a, 38b ... ITO layer 40a, 40b ... n + type a-Si contact layer 42a , 42b ... SiO ₂ film 44a ... source electrode 44b ... drain electrode 46 ... n-type a-Si active layer 48 ... i-type a-Si active layer 50 ... a-Si active semiconductor layer 52 ... gate insulating film 54 ... gate electrode Reference numeral 60: glass substrate 62a, 74a: source electrode 62b, 74b: drain electrode 64a, 64b, 76a, 76b: ITO transparent electrode layer 66 , 66b, 78a, 78b ... n + -type a-Si contact layer 68 ... i-type a-Si active layer 70 ... gate insulating film 72 ... gate electrode

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Tamotsu Wada, Fujitsu Limited (1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture) 58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (5)

(57) [Claims] To 1. A substrate, a source electrode and a drain electrode formed relative, and the source electrode and the active semiconductor layer formed in contact with the drain electrode, the active semiconductor layer and the gate insulating film in the thin film transistor and a gate electrode formed over the source electrode and the drain electrode, respectively, a transparent electrode layer mainly composed of indium tin oxide, is formed in contact with the transparent electrode layer, said operating semiconductor and an n-type contact semiconductor layer to layer and in ohmic contact with the active semiconductor layer, an impurity concentration than the n-type contact semiconductor layer provided in a portion in contact with at least the transparent electrode layer lower n ^- -type semiconductor layer And a i-type semiconductor layer. 2. The thin film transistor according to claim 1, wherein the thickness of the n ⁻ type semiconductor layer constituting the active semiconductor layer is 20 nm or less. 3. The thin film transistor according to claim 1, wherein said n constituting said source electrode and said drain electrode is formed.
A thin film transistor, wherein the content of the n-type impurity in the contact layer is 1% or more, and the content of the n-type impurity in the n ⁻ -type semiconductor layer constituting the active semiconductor layer is less than 1%. 4. The thin film transistor according to claim 1, wherein the content of an n-type impurity in the n ⁻ -type semiconductor layer forming the active semiconductor layer is gradually or stepwise reduced from the substrate side. A thin film transistor characterized by the above-mentioned. 5. A step of sequentially laminating a transparent electrode layer containing indium tin oxide as a main component, an n-type contact semiconductor layer and an insulating layer on a substrate, and using the resist patterned in a predetermined shape as a mask as a mask. Is wet-etched, the n-type contact semiconductor layer is dry-etched, and after the transparent electrode layer is wet-etched, the resist is removed,
Using the insulating layer side-etched by wet etching as a mask, the n-type contact semiconductor layer is again dry-etched to form a source electrode and a drain electrode comprising a transparent electrode layer having a step-like structure and an n-type contact semiconductor layer. Forming, and after removing the insulating layer, sequentially laminating an n ⁻ -type semiconductor layer, an i-type semiconductor layer, a gate insulating film, and a gate electrode layer having a lower impurity concentration than the n-type contact layer on the entire surface. Etching the gate electrode layer, the gate insulating film, the i-type semiconductor layer and the n ⁻ -type semiconductor layer using a resist patterned in a predetermined shape as a mask, and forming the n ⁻ -type semiconductor layer and the i-type semiconductor Forming a gate electrode on the operating semiconductor layer comprising the gate insulating film via the gate insulating film. A method of manufacturing a thin film transistor.