JP3190872B2 - Loop circuit considering loopback for each individual channel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loopback system for individually looping back a specific channel in a state where communication is performed by multiplexing signals of a plurality of channels. The present invention relates to a circuit and a system for simplifying the configuration of a loop circuit that absorbs, multiplexes and loops back.

[0002]

2. Description of the Related Art In a loop circuit incorporated in a conventional system of this kind, downstream data is fixed to a device FP (frame pulse) phase, and upstream data is
Following the transmission line phase, and these phases are shifted,
As shown in FIG. 5, it is necessary to incorporate a buffer 205 for phase absorption at the time of return from the upward to the downward side.

[0003] Referring to FIG. 5, downlink input data is converted into a transmission frame rate by a downlink rate converter 201. The rate-converted data selects the uplink data of the return channel specified from the outside by the uplink return data insertion unit 202, and is multiplexed with the downlink data. The data that has passed through the uplink return data insertion unit 202 is added with a frame signal by the downlink frame creation unit 203 and output.

[0004] The upstream frame is sent to the upstream frame synchronization unit 20.
After recognizing the frame phase in step 4, the data is input to the loop circuit 200 at the phase following the transmission line phase, and the downlink return data insertion unit 206 selects the downlink data of the return channel specified from the outside, and converts the downlink data into uplink data. Multiplexed.

[0005] The data that has passed through the upstream folded data insertion unit 206 is converted in speed into an internal clock in an upstream speed conversion unit 207, and is replaced with a signal that follows the internal FP phase, and is serialized into the device. Output as a signal.

The up / down phase absorption buffer 205 of the loop circuit 200 is a buffer for absorbing the phase difference between the up / down data when the data is turned up / down.

FIG. 6 is a diagram showing the operation timing of the circuit shown in FIG. Referring to FIG. 5 and FIG. 6, in the loop circuit, the phase of the downlink data is fixed to the device FP phase, and at the time of downlink → upturn, the downlink data is shifted to the transmission data phase of the uplink data by the phase absorption buffer 205. After the absorption of the phase difference of
6 and multiplexed with uplink data. Also, at the time of uplink to downlink return, the phase of the uplink data is the transmission line phase, and after the phase absorption buffer 205 absorbs the phase difference to the device FP phase, the downlink return data insertion unit 202
And multiplexed with downlink data.

[0008]

By the way, in the above-mentioned conventional system, the upstream speed conversion unit 207 integrally performs the speed conversion and the function of switching to the phase in the apparatus.

The upstream speed conversion unit 207 is divided into a function of speed conversion and a function of phase shifting in the apparatus, and if the phase after the phase shifting is matched with the data phase on the downstream side (follows the FP in the apparatus), it becomes possible to perform phase absorption. There is no need to add a new buffer. Thereby, the circuit configuration can be simplified.

Accordingly, the present invention has been completed based on the above findings, and an object of the present invention is to provide a loop circuit which facilitates a circuit configuration.

[0011]

In order to achieve the above object, according to the present invention, there is provided a multiplexed system in which the phase of downlink data follows the frame pulse on the device side, and the uplink data follows the phase of the transmission line. Upstream / downstream of serial signal for each channel
A device frame pulse phase changing means for changing the phase of the upstream data from the phase following the transmission path to the phase following the frame pulse in the apparatus is provided at the upstream stage of the loop circuit performing the downward loop, The upstream data of the device frame pulse phase output from the frame pulse phase changing means is multiplexed with the downstream data and turned back.

[0012]

Embodiments of the present invention will be described below. In a preferred embodiment of the loop circuit of the present invention, a downstream frame phase is a device-side frame pulse (hereinafter also referred to as “device FP”), and an upstream frame is a multiplexed serial signal that follows the phase of a transmission path. In order to perform loop wrapping for each individual channel in the signal, an upstream speed conversion unit that converts an upstream serial signal to an internal clock and a device FP phase is provided by a speed conversion unit and a device F.
It is configured such that it is divided into P-phase transfer units and a loop circuit is inserted between them.

According to a preferred embodiment of the present invention, the multiplexed serial signal, in which the phase of the downstream data follows the frame pulse on the device side and the phase of the upstream data follows the phase of the transmission line, is transmitted to each channel. In a method of performing an up / down loop, a device frame pulse phase changing means (FIG. 1) for changing the phase of uplink data from a phase following a transmission path to a phase following a frame pulse in the apparatus.
105) is provided before the loop circuit, and the loop circuit (FIG. 1)
The reference numeral 100) denotes an upstream speed conversion for multiplexing the upstream data of the apparatus frame pulse phase tracking output from the apparatus frame pulse phase changing means (105 in FIG. 1) with the downstream data and converting the multiplexed data into the upstream internal clock. Part (10 in FIG. 1)
7), the upstream data of the apparatus frame pulse phase tracking output from the apparatus frame pulse phase changing means (105 of FIG. 1) output from the downstream folded data insertion means (106 in FIG. 1) and the downstream frame rate conversion. Part (10 in FIG. 1)
1) multiplexing the downlink data output from 1) and outputting the multiplexed data to the downlink frame generator (103 in FIG. 1).

Further, in the embodiment of the present invention, the device frame pulse phase changing means (105 in FIG. 3) comprises:
The phase of the upstream m-channel data is changed from the transmission path following phase to the phase following the in-device frame pulse, and the output m-channel data output from the device frame pulse phase changing means is converted to the phase of the downstream n-channel data. 3. The phase adjusting means (108 in FIG. 3) is provided, and the upstream m-channel data output from the phase adjusting means
A configuration in which the data is looped back on the channel data may be adopted.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. The downstream-side downstream input data is transmitted to the downstream speed conversion unit 10.
In step 1, it is converted to the speed of the transmission frame.

The data whose rate has been converted are selected by the uplink return data insertion section 102 from the externally designated return channel and multiplexed with the downlink data.

The data that has passed through the uplink return data insertion unit 102 is output after adding a frame signal to the downlink frame generation unit 103.

The upstream frame is sent to the upstream frame synchronizing section 10.
After recognizing the frame phase in step 4, the device FP (frame pulse) phase changing unit 105 changes the phase to the phase followed by the device FP.

The data output from the apparatus FP phase change unit 105 selects downlink data of a return channel specified from the outside by a downlink return data insertion unit 106 and is multiplexed with uplink data.

The data that has passed through the upstream return data insertion unit 106 is subjected to speed conversion by the upstream speed conversion unit 107, and then output as a serial signal into the device.

FIG. 2 is a timing chart for explaining the operation of one embodiment of the present invention. The operation of one embodiment of the present invention will be described with reference to FIGS.

(1) The downstream data is transmitted to the downstream speed converter 101
To the speed for the downstream frame, and the loop circuit 1
00 (“down frame phase” in FIG. 2A)
Signal).

(2) The upstream data is transmitted to the upstream frame synchronization unit 1
After recognizing the frame phase through the signal line 04, the signal is input to the device FP phase changing unit 105 (the signal of “upstream frame phase” in FIG. 2B). Device FP phase transfer unit 105
Then, the phase is synchronized with the downstream data and input to the loop circuit 100 (the signal of “replace the upstream frame with the internal phase” in FIG. 2C).

(3) In the loop circuit 100, since the phases of the downlink and uplink are aligned, only the channel to be looped back is multiplexed from downlink data to uplink data / multiplexed from uplink data to downlink data. Perform processing.

(4) The data output from the loop circuit 100 is transmitted and output on the downstream side after adding a frame signal, and is output into the apparatus after data rate conversion on the upstream side.

According to the conventional system shown in FIG. 5, the loop circuit requires a buffer for absorbing the phase difference between the downstream and upstream data and a circuit for controlling the buffer. As described above, since the upstream data is input at the transmission line phase, it is necessary to absorb the phase difference between the downstream and upstream data for any phase, so the buffer control circuit must be able to cope with it. Must. This complicates the control circuit.

On the other hand, in the embodiment of the present invention, originally, the function of changing the phase of the device FP in the upstream speed conversion unit is divided, and the function is simply arranged before the loop circuit 100. It is only necessary to change the phase on the output side of the device FP phase transfer unit to be the same as the read phase for speed conversion of the downstream data.

For this reason, in one embodiment of the present invention,
Buffers for up / down phase absorption and a circuit scale for buffer control can be reduced.

[0030]

As described above, according to the present invention,
Eliminating the need for the buffer for up / down phase absorption and the buffer control unit has the effect of reducing the circuit scale and achieving cost reduction.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional loop circuit.

FIG. 6 is a timing chart for explaining an operation of a conventional loop circuit.

[Explanation of symbols]

Reference Signs List 101 downlink speed conversion unit 102 uplink return insertion unit 103 downlink frame creation unit 104 uplink frame synchronization unit 105 device FP phase transfer unit 106 downlink return insertion unit 107 uplink speed conversion unit 108 phase adjustment unit from uplink m channels to downlink n channels Reference Signs List 201 downlink speed conversion unit 202 uplink return insertion unit 203 downlink frame creation unit 204 uplink frame synchronization unit 205 uplink / downstream phase absorption buffer 206 downlink return insertion unit 207 uplink speed conversion unit

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification code FI H04L 29/14 H04L 11/00 331 (72) Inventor Kosuke Shio 1-403 Kosugi-cho, Nakahara-ku, Nakazaki-ku, Kawasaki-shi, Kanagawa NEC Corporation In-house (56) References JP-A-2-119335 (JP, A) JP-A-58-36043 (JP, A) JP-A-57-81760 (JP, A) JP-A-62-268246 (JP, A A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04J 3/00 H04L 7/00 H04L 12/437 H04L 29/14

Claims (2)

(57) [Claims] 1. The phase of downstream data follows the frame pulse on the device side, and the upstream data follows the phase of the transmission path.
In the loop-back system in which the multiplexed serial signal is looped back / up for each channel, the up-stream serial signal is replaced with the clock in the device and the frame pulse phase in the device in order to loop-back for each individual channel. Is divided into a speed conversion unit and a device frame pulse phase change unit,
In the meantime, a loop-back method is provided in which a loop circuit for returning the uplink / downlink data is inserted. 2. The phase of the downstream data follows the frame pulse on the device side, and the upstream data follows the phase of the transmission path.
In a loopback system in which a multiplexed serial signal is looped up / down for each channel, an apparatus for changing the phase of m-channel data of upstream from a phase following a transmission path to a phase following a frame pulse in the apparatus. A frame pulse phase changing means; a loop circuit for adjusting the phase of the m-channel data output from the apparatus frame pulse phase changing means to the phase of the downlink n-channel data; and an output from the phase adjusting means. And looping back the overlapped m-channel data on the downlink n-channel data.