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JP3221114B2 - Magnetoelectric conversion element - Google Patents
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JP3221114B2 - Magnetoelectric conversion element - Google Patents

Magnetoelectric conversion element

Info

Publication number
JP3221114B2
JP3221114B2 JP33315992A JP33315992A JP3221114B2 JP 3221114 B2 JP3221114 B2 JP 3221114B2 JP 33315992 A JP33315992 A JP 33315992A JP 33315992 A JP33315992 A JP 33315992A JP 3221114 B2 JP3221114 B2 JP 3221114B2
Authority
JP
Japan
Prior art keywords
type
input
hall element
gaas
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33315992A
Other languages
Japanese (ja)
Other versions
JPH06181348A (en
Inventor
良一 竹内
雅彦 臼田
隆 宇田川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
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Filing date
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Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP33315992A priority Critical patent/JP3221114B2/en
Publication of JPH06181348A publication Critical patent/JPH06181348A/en
Application granted granted Critical
Publication of JP3221114B2 publication Critical patent/JP3221114B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Hall/Mr Elements (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は III−V族化合物半導体
材料を用いた磁電変換素子、特に高いサージ耐性を有す
る高信頼性の III−V族化合物磁電変換素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoelectric device using a III-V compound semiconductor material, and more particularly to a highly reliable III-V compound magnetoelectric device having high surge resistance.

【0002】[0002]

【従来の技術】磁界を検知し、その強度をもって電気信
号に変換する、いわゆる磁電変換素子の一つとしてホー
ル(Hall)素子が知られている。ホール素子は従来
からシリコン(Si)、ゲルマニウム(Ge)等の単一
元素からなる単体半導体や、ヒ化ガリウム(GaAs)
やリン化インンジウム(InP)などの元素周期律表の
第 III族並びに第V族に属する元素からなる、いわゆる
III−V族化合物半導体を利用して得られており、これ
らの半導体材料に磁場を印加した際に起こる電子の運動
によって発生するホール(Hall)電圧を被検知量と
した一種のセンサーであり、従来から磁界強度の測定に
は勿論のこと回転体の回転数の測定など、多岐に亘る産
業分野に多用されている。
2. Description of the Related Art A Hall element is known as one type of a so-called magnetoelectric conversion element which detects a magnetic field and converts it into an electric signal with its strength. Conventionally, a Hall element is a single semiconductor made of a single element such as silicon (Si) or germanium (Ge), or gallium arsenide (GaAs).
Consisting of elements belonging to Groups III and V of the periodic table of the elements, such as and indium phosphide (InP).
It is a type of sensor obtained by using a III-V compound semiconductor and using a Hall (Hall) voltage generated by the movement of electrons generated when a magnetic field is applied to these semiconductor materials as a detected amount, 2. Description of the Related Art Conventionally, it is widely used in various industrial fields, such as measurement of the number of revolutions of a rotating body, as well as measurement of magnetic field strength.

【0003】ホール素子には上記の如くSi単体半導体
の他、InSb、InAsやGaAs等の III−V族化
合物半導体が使用されている。実際のホール素子の製造
にあたっては、例えばInSbから成るバルク結晶その
ものをホール素子の感磁部として利用する場合も有る
が、多くは高抵抗のGaAs単結晶基板にイオン注入法
により或はGaAs単結晶基板上にVPE、MOCV
D、MBE法等の気相成長法や液相成長法により形成さ
れたGaAs層が感磁部として利用されている。従来か
らの一般的なホール素子の製造方法は、この様にして形
成された感磁部となる層上に電気信号の入・出力電極と
なるオーミック(Ohmic)特性を有する電極を形成
し、ホール素子を構成する。
[0003] As described above, a III-V group compound semiconductor such as InSb, InAs, or GaAs is used for the Hall element in addition to the Si elemental semiconductor as described above. In actual manufacture of a Hall element, for example, a bulk crystal of InSb itself may be used as a magnetic sensing part of the Hall element. However, in most cases, a high-resistance GaAs single crystal substrate is ion-implanted or a GaAs single crystal. VPE, MOCV on substrate
A GaAs layer formed by a vapor phase growth method such as a D or MBE method or a liquid phase growth method is used as a magnetic sensing part. A conventional general method for manufacturing a Hall element is to form an electrode having ohmic characteristics as input / output electrodes for an electric signal on a layer serving as a magnetic sensing portion formed in this way, and to form a hole. Configure the element.

【0004】ホール素子の構成上、上記のオーミック電
極は必須な構成要素である。通常ホール素子は図1に示
す様に、感磁部 103 となるGaAsエピタキシャ
ル成長層の表面上に設けた一対の入力電極 101 と
一対の出力電極 102 とから形成される。一般的に
感磁部層 103 となる半導体層の電子移動度の高さ
がホール素子の感度特性を決めるため、感磁部として同
じ半導体材料に於いてもp形ではなくn形の伝導形を示
すn形半導体層が用いられてる。このためこの様なn形
伝導体について電極材料としてオーミック電極となり易
い、例えば金ーゲルマニウム合金などがもっぱら利用さ
れている。
The above-mentioned ohmic electrode is an essential component in the structure of the Hall element. Normally, as shown in FIG. 1, a Hall element is formed from a pair of input electrodes 101 and a pair of output electrodes 102 provided on the surface of a GaAs epitaxial growth layer that will be the magnetically sensitive portion 103. In general, the high electron mobility of the semiconductor layer serving as the magnetosensitive layer 103 determines the sensitivity characteristics of the Hall element. The n-type semiconductor layer shown is used. For this reason, for such an n-type conductor, an ohmic electrode, for example, a gold-germanium alloy, is easily used as an electrode material.

【0005】実際にホール素子を動作させるにあって
は、例えば上記の金ーゲルマニウム合金によって構成さ
れる一対のオーミック性入力電極に電圧を適宣印加す
る。しかし、単にn形の伝導を示す半導体感磁部層上に
形成されたオーミック電極では、動作電圧を印加するに
際し許容値を越えるサージ的な電圧により、或はまた素
子の動作中に起こる突発的な過剰な動作電圧の印加によ
ってもホール素子の機能が破壊される難点があった。こ
のためこの様なサージ的に入力する電圧によるホール素
子の破壊を防御するために、ホール素子の駆動用電気回
路にサージ的な入力を吸収するダイオード等の電気部品
を具備してなる、いわばプロテクト回路を組み込むのが
従来から行われている一般的な方法であった(たとえ
ば、「最新カ−エレクトロニクスと車載電子機器の信頼
性対策」 P.255〜227、1989年 技術情報
協会刊 参照)。
In actually operating the Hall element, a voltage is appropriately applied to a pair of ohmic input electrodes made of, for example, the above-mentioned gold-germanium alloy. However, in the case of an ohmic electrode formed on a semiconductor magneto-sensitive layer simply showing n-type conduction, a surge voltage exceeding an allowable value when an operating voltage is applied, or a sudden occurrence occurring during the operation of the element. There is a problem that the function of the Hall element is destroyed even by applying an excessively high operating voltage. Therefore, in order to protect the Hall element from destruction due to such a surge-input voltage, an electrical component such as a diode for absorbing a surge-like input is provided in an electric circuit for driving the Hall element. Incorporating a circuit has been a general method that has been conventionally performed (for example, see “Reliability Measures for Latest Car Electronics and In-Vehicle Electronic Devices”, pp. 255-227, published by Technical Information Association, 1989).

【0006】[0006]

【発明が解決しようとする課題】しかしながら上記の様
な従来からの方法は、電気部品の構成数を単に増加させ
ると共に電気回路上の構成を複雑化し、結果的にはホー
ル素子の小型化に支障を来す等の欠点があり、微小領域
での磁界測定、2次元的な磁界強度の分布測定には差し
支えを生じていた。
However, the conventional methods as described above simply increase the number of electrical components and complicate the configuration on the electrical circuit, and consequently hinder miniaturization of the Hall element. This has the disadvantage that the measurement of the magnetic field in a minute area and the measurement of the two-dimensional distribution of the magnetic field strength are hindered.

【0007】 本発明は上記の欠点に鑑み、突発的な動
作用電源の入力から素子を保護するための特別な外部回
路を必要とせず、安定的な動作をもたらす高信頼性のし
かも小型化が容易な磁電変換素子を提供することを目的
としてなされたものある。
In view of the above drawbacks, the present invention does not require a special external circuit for protecting the element from sudden input of a power supply for operation, and achieves high reliability and downsizing that provides stable operation. It has been made for the purpose of providing easy magnetoelectric transducer.

【0008】[0008]

【課題を解決するための手段】本発明者は従来のホール
素子に見られる感磁部を構成するn形半導体層にオーミ
ック接触を構成する一対の入力電極の構成手段に検討を
加えた。その結果化合物半導体からなるホール素子に於
いて一対を成すオーミック性入力電極の一つにp/n接
合を設けることにより、突発的な動作電源の入力から素
子を保護し、継続して安定な特性を発揮し得る高い信頼
性を有する化合物半導体ホール素子を提供するものであ
る。
Means for Solving the Problems The present inventor has studied the means for forming a pair of input electrodes forming an ohmic contact with the n-type semiconductor layer forming the magnetically sensitive portion as seen in a conventional Hall element. As a result, by providing a p / n junction at one of a pair of ohmic input electrodes in a Hall element made of a compound semiconductor, the element is protected from a sudden input of an operation power supply, and a stable characteristic is continuously provided. It is intended to provide a compound semiconductor Hall element having high reliability capable of exhibiting the following.

【0009】 上記p/n接合は、例えば入力電極が形
成されるn型半導体層に接合させてp形半導体を介在さ
せれば容易に形成され得る。例えば、GaAs、In
P、ヒ化インジウム(InAs)やアンチモン化インジ
ウム(InSb)等のIII−V族2元化合物、または
それらの混晶半導体を利用したホール素子にあっては、
元素の周期律表に掲げられる第II族元素である亜鉛
(Zn)やマグネシウム(Mg)のイオンを適量注入す
るいわゆるイオン注入を施し、然る後適宜熱処理を施す
ことによりn形半導体領域内にp形の伝導形を有する化
合物半導体層を形成することが出来る。一方、n形の伝
導形を呈するIII−V族2元化合物またはそれらの混
晶半導体は、p形半導体層領域内に元素周期律表の第I
V族に属するシリコン(Si)、ゲルマニウム(G
e)、もしくは第VI族の硫黄(S)やセレン(Se)
等の元素をイオン注入すれば容易に得ることが出来る。
また、上述のp形、またはn形化合物半導体は、イオン
注入法に限らず有機金属熱分解気相成長法(MOCV
D)法、分子線エピタシャル法(MBE)法等の気相
成長、或はまた液相エピタキシャル法などの成長法によ
っても形成できる。
The p / n junction can be easily formed, for example, by bonding the p / n junction to an n-type semiconductor layer on which an input electrode is formed and interposing a p-type semiconductor. For example, GaAs, In
P, a Hall element using a III-V group binary compound such as indium arsenide (InAs) or indium antimonide (InSb), or a mixed crystal semiconductor thereof,
A proper amount of ions of zinc (Zn) or magnesium (Mg), which is a Group II element listed in the periodic table of the elements, is implanted, and then an appropriate heat treatment is applied to the n-type semiconductor region. A compound semiconductor layer having a p-type conductivity can be formed. On the other hand, a group III-V binary compound exhibiting an n-type conduction type or a mixed crystal semiconductor thereof is contained in the p-type semiconductor layer region in the element I of the periodic table.
Silicon (Si) and germanium (G
e) or Group VI sulfur (S) or selenium (Se)
Such an element can be easily obtained by ion implantation.
In addition, the above-mentioned p-type or n-type compound semiconductor is not limited to the ion implantation method but may be a metal organic chemical vapor deposition (MOCV) method.
D) method, a molecular beam Epita key Interstitial method (MBE) method, or the like vapor deposition, or also can be formed by a deposition method such as liquid phase epitaxial method.

【0010】Si、Ge等の単体半導体から成るホール
素子に於いても、上記の様な方法でp/n接合を形成す
ることが出来る。但し、これら第VI族の半導体にあって
は上記の III−V族化合物半導体とは異なり、p形層の
形成には第 III族に属する元素を、n形層の形成にはリ
ン(P)、ヒ素(As)等の第V族の元素をイオン注入
するか、或はドーピング(添加)するエピタキシャル成
長法により得られる。
A p / n junction can be formed by the above-described method even in a Hall element made of a simple semiconductor such as Si or Ge. However, these group VI semiconductors are different from the above group III-V compound semiconductors in that elements belonging to group III are formed for forming the p-type layer and phosphorus (P) is formed for forming the n-type layer. , Arsenic (As), etc., by ion implantation or doping (addition) by epitaxial growth.

【0011】更に、GaAsから成るホール素子をイオ
ン注入法を利用して得る場合を例に挙げ、本発明に説明
を加える。従来と同様GaAsから成るホール素子を得
るには半絶縁性のいわゆる高抵抗のGaAs単結晶を基
板として用いる。先ずこの高抵抗GaAs基板表面の素
子を形成する領域以外、即ち入・出力電極部、感磁部と
なる領域以外の領域を、公知のフォトリソグラフィー
法、エッチング法等に従って一般的なレジスト剤、酸化
ケイ素(SiO2 )、窒化ケイ素(SiN)などの膜で
被覆する。然る後、GaAsに対しn形不純物となるS
iイオンを適量注入する。次に、上述の素子の機能部と
なる領域以外を被覆していた膜材をエッチングにより除
去する。その後、Siイオンが注入されたGaAs結晶
基板に適宣熱処理を施し、注入されたSiイオンを電気
的に活性化させてn形GaAsから成る感磁部、及び各
々一対をなす入力並びに出力電極部を形成する。次にS
iをイオン注入した一対をなす入力電極部の片方に、p
/n接合を成す様に例えばZnイオンなどのp型不純物
を注入する。然る後に再び適宣熱処理を施し、注入され
たZnイオンを電気的に活性化してp/n接合を形成す
る。最終的には各々一対をなす入・出力電極部に金ーゲ
ルマニウム合金等の、n形GaAsに対し、オーミック
接触をもたらす電極材を真空蒸着法などにより被着して
電極を形成すれば、本発明に係わるホール素子が得られ
る。
Further, the present invention will be described with reference to an example in which a Hall element made of GaAs is obtained by using an ion implantation method. In order to obtain a GaAs Hall element as in the prior art, a so-called semi-insulating so-called high-resistance GaAs single crystal is used as a substrate. First, areas other than the element forming area on the surface of the high-resistance GaAs substrate, that is, the areas other than the areas serving as the input / output electrode section and the magnetic sensing section, are exposed to a general resist material, oxidation method, or the like according to a known photolithography method, etching method, or the like. It is covered with a film such as silicon (SiO 2 ) or silicon nitride (SiN). Thereafter, S, which becomes an n-type impurity for GaAs,
An appropriate amount of i-ion is injected. Next, the film material covering the region other than the region that becomes the functional portion of the element is removed by etching. Thereafter, a suitable heat treatment is applied to the GaAs crystal substrate into which the Si ions have been implanted, and the implanted Si ions are electrically activated to make the magneto-sensitive portion made of n-type GaAs and a pair of input and output electrode portions. To form Then S
i is ion-implanted into one of a pair of input electrode portions,
A p-type impurity such as, for example, Zn ions is implanted to form a / n junction. Thereafter, an appropriate heat treatment is performed again to electrically activate the implanted Zn ions to form ap / n junction. Eventually, an electrode is formed by forming a pair of input / output electrode portions by applying an electrode material that provides ohmic contact to n-type GaAs, such as a gold-germanium alloy, by a vacuum deposition method or the like. A Hall element according to the invention is obtained.

【0012】上記の例ではn形不純物のSiを先ず注入
し、活性化のための熱処理を施し、然る後、p形不純物
のZnイオンを注入し、熱処理する工程手順であった
が、本発明に係わるホール素子にあっては別段この手順
に限定されることはなく、上記の例とは逆にp形不純物
を注入し熱処理を施した後、n形不純物を注入し熱処理
を実施しても良い。また、各イオンの注入の度に熱処理
を施すのではなく、p形、n形不純物を先ずイオン注入
し、然る後同時に熱処理を行う簡略化された工程でも本
発明に係わるホール素子が得られる。
In the above example, the process procedure is such that the n-type impurity Si is first implanted, heat treatment for activation is performed, and then the p-type impurity Zn ion is implanted and heat-treated. The Hall element according to the present invention is not particularly limited to this procedure. Conversely to the above example, a p-type impurity is implanted and heat treatment is performed, and then an n-type impurity is implanted and heat treatment is performed. Is also good. In addition, the Hall element according to the present invention can be obtained by a simplified process in which p-type and n-type impurities are first ion-implanted, and then heat treatment is performed simultaneously, instead of performing heat treatment each time each ion is implanted. .

【0013】以上、化合物半導体の例としてGaAs
を、並びに単体半導体の例としてSiを例に挙げて本発
明に係わる新たなホール素子につき概略を記したが、I
nP、InAs、InSb或はそれらの混晶を材料とし
ても、またGeの様なSi以外の単体半導体に於いても
上述の方法により本発明に記載のp/n接合をもってな
る新たなホール素子を得ることは可能である。
As described above, GaAs is an example of a compound semiconductor.
And a new Hall element according to the present invention by taking Si as an example of a simple semiconductor.
Even if nP, InAs, InSb or a mixed crystal thereof is used as a material, or a simple semiconductor other than Si such as Ge, a new Hall element having the p / n junction according to the present invention can be obtained by the above-described method. It is possible to get.

【0014】[0014]

【作用】本発明に記載のp/n接合を一対の入力電極の
内、一方の入力電極にp/n接合を設けることにより、
ホール素子を動作させるための動作・制御電圧等の入力
には何等支障を与えず、許容を越える動作電圧の入力に
対しては機能破壊から素子を防護する作用が得られる。
The p / n junction according to the present invention is provided by providing a p / n junction to one of the pair of input electrodes.
The input of the operation / control voltage for operating the Hall element does not interfere at all, and the action of protecting the element from functional destruction is obtained with respect to the input of the operating voltage exceeding the allowable level.

【0015】[0015]

【実施例】以下、本発明に係わるホール素子について、
実施例を基に詳細に説明する。 (実施例1)ここでは、 III−V族2元化合物であるG
aAsを母体材料とするホール素子を例に挙げ説明を加
える。先ず、本発明に係わるホール素子の平面の概略図
を図2に示し、断面図を図3に示す。先に記載した如
く、GaAsから成るホール素子にあってはクロム(C
r)などの遷移金属または酸素(O2 )などを添加して
なる、或は無添加(アンドープ)の半絶縁性を有する高
抵抗のGaAs結晶を基板として使用する。本実施例で
は比抵抗が約107 Ω・cmの無添加の半絶縁性GaA
s単結晶を基板204 として使用した。また、基板
204 の面方位は(100)±0.5度の範囲内にあ
った。但し、使用する基板の比抵抗値並びに面方位共に
上述の値に限定されることはなく、例えば比抵抗が10
6 Ω・cm程度であっても良く、面方位も(100)面
から2度程度傾斜させた方位であっても差し支えはな
い。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a Hall element according to the present invention will be described.
This will be described in detail based on an embodiment. (Example 1) Here, G which is a group III-V binary compound is used.
A description will be given by taking a Hall element using aAs as a base material as an example. First, FIG. 2 shows a schematic plan view of a Hall element according to the present invention, and FIG. 3 shows a cross-sectional view thereof. As described above, in a Hall element made of GaAs, chromium (C
A high resistance GaAs crystal having a semi-insulating property, to which a transition metal such as r) or oxygen (O 2 ) is added or not added (undoped) is used. In this embodiment, undoped semi-insulating GaAs having a specific resistance of about 10 7 Ω · cm
An s single crystal was used as the substrate 204. Also, the substrate
The plane orientation of 204 was in the range of (100) ± 0.5 degrees. However, neither the specific resistance value nor the plane orientation of the substrate to be used is limited to the above values.
It may be about 6 Ω · cm, and the plane direction may be a direction inclined about 2 degrees from the (100) plane.

【0016】次に、上述のGaAs単結晶基板 204
表面に感磁部 203、入力電極部 201 及び出
力電極部 202 となるn形の伝導形を呈するGaA
s層を形成すべく、該GaAs結晶 204 表面を一
般的なフォトレジスト材で全面に亘り被覆し、その後公
知のフォトリソグラフィー法及びエッチング法を駆使し
て素子形成領域部に相当する部分(201〜203)の
フォトレジストを選択的に剥離し、同領域に於てGaA
s結晶 204 の表面を露出させた。
Next, the above-mentioned GaAs single crystal substrate 204
GaAs having n-type conduction type on the surface to be the magnetic sensing part 203, the input electrode part 201, and the output electrode part 202
In order to form an s layer, the surface of the GaAs crystal 204 is covered with a general photoresist material over the entire surface, and thereafter, by using a well-known photolithography method and an etching method, portions (201 to 201) corresponding to the element formation region portion are formed. 203) The photoresist is selectively removed, and GaAs is formed in the same region.
The surface of the s crystal 204 was exposed.

【0017】然る後、上記の如く加工されたGaAs結
晶 204 を一般のイオン注入装置内に載置し、質量
数28、もしくは29のSiイオンを加速電圧200K
V、ドーズ量2×1012cm-2の条件で上記素子形成領
域(202〜204)に選択的に注入しn形GaAs注
入層を形成した。次いで、マスキング材として利用した
フォトレジスト材を剥離した後、このイオン注入を施し
たGaAs結晶 204 を、所定の分圧のアルシン
(AsH3 )ガスを含む雰囲気内に於て温度850℃で
15分間熱処理した。
Thereafter, the GaAs crystal 204 processed as described above is placed in a general ion implantation apparatus, and Si ions having a mass number of 28 or 29 are charged at an accelerating voltage of 200K.
V and a dose of 2 × 10 12 cm −2 were selectively implanted into the element formation regions (202 to 204) to form an n-type GaAs implanted layer. Next, after the photoresist material used as the masking material is removed, the ion-implanted GaAs crystal 204 is removed at a temperature of 850 ° C. for 15 minutes in an atmosphere containing a prescribed partial pressure of arsine (AsH 3 ) gas. Heat treated.

【0018】次に再び該GaAs結晶 204 の表面
全体にフォトレジスト材を塗布し、一対のn形GaAs
から成る入力電極 201 の一方 201−a との
p/n接合を形成するため、p形GaAs層を形成すべ
き該当領域 205 を公知のフォトリソグラフィー法
とエッチング法により加工し、当該p形GaAs形成領
域(205)に在るフォトレジスト材を選択的に除去し
た。然る後、Znイオンを加速電圧100KVで、ドー
ズ量8.0×1013cm-2で注入した。先述の如くフォ
トレジスト材を剥離した後、所定の分圧のアルシンガス
を含む雰囲気中に於て温度650℃で20分間の第2回
目の熱処理をGaAs結晶に施した。
Next, a photoresist material is applied again on the entire surface of the GaAs crystal 204 to form a pair of n-type GaAs.
In order to form a p / n junction with one of the input electrodes 201-a composed of a p-type GaAs layer, a corresponding region 205 where a p-type GaAs layer is to be formed is processed by a known photolithography method and an etching method to form the p-type GaAs layer. The photoresist material in the region (205) was selectively removed. Thereafter, Zn ions were implanted at an acceleration voltage of 100 KV and a dose of 8.0 × 10 13 cm −2 . After removing the photoresist material as described above, the GaAs crystal was subjected to a second heat treatment at a temperature of 650 ° C. for 20 minutes in an atmosphere containing arsine gas at a predetermined partial pressure.

【0019】更に、上記Si並びにZnイオンを注入し
たGaAs結晶 204 の表面を、一般的なフォトレ
ジスト材で全面に亘り被覆し、入力電極部 201 と
出力電極部 202 となるn形GaAs層の領域を被
覆しているフォトレジスト材のみを剥離し、同領域(2
01及び202)に於て該n形GaAs層が露出する様
に加工を施した。然る後、n形GaAsとオーミック接
触をもたらす金ーゲルマニウム(Au−Ge)合金を真
空蒸着し、各々一対をなす計4個の入力用電極206
及び出力用電極 207 を構成した。ここではn形の
オーミック電極材料としてGeの含有量が12重量%の
Au−Ge合金を使用したが、Au−Ge合金に於ける
Geの含有量はこれに固定されることはなく、またAu
−Ge合金以外の物質を用いても構わない。
Further, the entire surface of the GaAs crystal 204 into which the Si and Zn ions have been implanted is covered with a general photoresist material, and the region of the n-type GaAs layer which becomes the input electrode portion 201 and the output electrode portion 202 is formed. Only the photoresist material covering the area is peeled off and the same area (2
01 and 202), processing was performed such that the n-type GaAs layer was exposed. Thereafter, a gold-germanium (Au-Ge) alloy providing ohmic contact with the n-type GaAs is vacuum-deposited, and a pair of the four input electrodes 206 is formed.
And the output electrode 207. Here, an Au-Ge alloy having a Ge content of 12% by weight was used as the n-type ohmic electrode material. However, the Ge content in the Au-Ge alloy is not fixed thereto, and the Au content is not fixed.
-A substance other than the Ge alloy may be used.

【0020】p形GaAs注入領域 205 には、熱
処理された金ー亜鉛(Au−Zn)合金からなp形Ga
As用のオーミック入力電極 209 を設けた。次
に、図2に示す如くAuからなる配線 208 を、Z
nイオン注入によるp形オーミック電極 209 と入
力用電極 206 のうちp形注入層 205 を設け
てない側の入力電極 206−b に連結させて構成し
た。
In the p-type GaAs implantation region 205, a p-type Ga made of a heat-treated gold-zinc (Au-Zn) alloy is provided.
An ohmic input electrode 209 for As was provided. Next, as shown in FIG.
The p-type ohmic electrode 209 formed by n-ion implantation and the input electrode 206 are connected to the input electrode 206-b on the side where the p-type implanted layer 205 is not provided.

【0021】(比較例)また、本発明による効果をより
よく対比させるため、本発明に依るp/n接合を含まな
い従来のホール素子を作成した。その手順はp形GaA
s注入層の注入は実施せず、その他はすべて同一とし
た。
Comparative Example In order to better compare the effects of the present invention, a conventional Hall element according to the present invention, which does not include a p / n junction, was prepared. The procedure is p-type GaAs
The injection of the s injection layer was not performed, and all others were the same.

【0022】表1に本発明に係わるホール素子の特性、
特に耐サージ特性につき従来のホール素子のそれと比較
して纏める。
Table 1 shows the characteristics of the Hall element according to the present invention,
In particular, the surge resistance is summarized in comparison with that of the conventional Hall element.

【0023】[0023]

【表1】 [Table 1]

【0024】本発明によるp/n接合の有無に係わら
ず、入力並びに出力抵抗値、積感度、ホール電圧の温度
依存性、ホール電圧の不平衡率の諸特性に顕著な差は認
められなかった。一方、入力電極に瞬時に所定の電圧を
印加する手法で入力電圧に対するサージ耐性を調査した
結果、本発明に係わるp/n接合を設けて成るホール素
子については、同接合を有しない従来のホール素子に比
較し格段に優れたサージ耐性を示した。一例として、p
/n接合を含まない従来のホール素子では、25Vのパ
ルス電圧の印加に対し、被検体の総数8200個の52
%に相当する数の検体が、電極部の破壊に基づくと思わ
れるホール出力電圧の不安定性、入力抵抗値の均一性の
悪化等の以上をもたらした。また、35Vのパルス電圧
の入力では実に83%の数に及ぶ被検体が何等かの電気
的特性に異常を来した。これとは全く逆に本発明に基づ
くp/n接合を入力電極側に有するホール素子にあって
は、35Vのパルス電圧の瞬時入力に対しても被検体総
数7500の内、素子特性上何等かの異常を来したもの
は皆無であった。
Regardless of the presence or absence of the p / n junction according to the present invention, no remarkable difference was observed in the characteristics of the input and output resistance values, the product sensitivity, the temperature dependency of the Hall voltage, and the unbalance rate of the Hall voltage. . On the other hand, as a result of investigating surge resistance against an input voltage by a method of instantaneously applying a predetermined voltage to an input electrode, a Hall element having a p / n junction according to the present invention has a conventional hole element having no p / n junction. The surge resistance was much better than that of the device. As an example, p
In a conventional Hall element that does not include the / n junction, a total of 8200 specimens of 52
% Of samples caused instability of the Hall output voltage, deterioration of the uniformity of the input resistance value, and the like, which are considered to be due to the destruction of the electrode portion. In addition, when a pulse voltage of 35 V was input, as many as 83% of the subjects had abnormalities in some electrical characteristics. Contrary to this, in the Hall element having the p / n junction on the input electrode side according to the present invention, even if an instantaneous input of a pulse voltage of 35 V is performed, some of the characteristics of the element out of the total number of subjects are 7,500. None of them had any abnormalities.

【0025】尚、本発明に係わる実施例では、GaAs
半導体を材料とするホール素子を例に挙げたが、本発明
による効果は、InP、InAs、InSbなどの2元
系化合物半導体、並びにSi、Ge等の単体半導体を使
用した場合でも発揮され得るのは明かである。
In the embodiment according to the present invention, GaAs is used.
Although the Hall element using a semiconductor as a material has been described as an example, the effect of the present invention can be exerted even when a binary compound semiconductor such as InP, InAs, and InSb, and a single semiconductor such as Si and Ge are used. Is clear.

【0026】[0026]

【発明の効果】本発明に基づくp/n接合を内蔵したホ
ール素子に於いては、上述の如く耐サージ特性が向上す
るのは明白であり、従来に無い高い信頼性を発揮するホ
ール素子を与える効果をもたらすものである。加えて、
サージ耐性を有する機能を素子に内蔵させることによっ
て、従来の如くサージ吸収機能をもった外部電気回路を
具備させる必要もないため、素子自体を小型化すること
も可能であり、よって、微小領域に於ける磁界センサ
ー、回転センサー等として産業界への応用が図られ、高
信頼性、高精度が要求される制御工学分野等の発展に寄
与するところ大である。
As described above, in the Hall element incorporating the p / n junction according to the present invention, it is clear that the surge resistance is improved as described above. It has the effect of giving. in addition,
By incorporating a function having surge resistance into the element, it is not necessary to provide an external electric circuit having a surge absorbing function as in the conventional case, so that the element itself can be downsized. It is applied to the industrial field as a magnetic field sensor, a rotation sensor, and the like in the field, and greatly contributes to the development of control engineering fields and the like that require high reliability and high accuracy.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来のホール素子の回路構成例を示す図であ
る。
FIG. 1 is a diagram showing a circuit configuration example of a conventional Hall element.

【図2】本発明に係わるp/n接合を内蔵してなるホー
ル素子の概略を示す平面図である。
FIG. 2 is a plan view schematically showing a Hall element having a built-in p / n junction according to the present invention.

【図3】図2の平面図をA−A’ラインで切断した断面
構造図である。
FIG. 3 is a sectional structural view of the plan view of FIG. 2 taken along line AA ′.

【符号の説明】[Explanation of symbols]

101・・・・入力電極 102・・・・出力電極 103・・・・感磁部 104・・・・結晶基板 201・・・・入力電極の形成領域 202・・・・出力電極の形成領域 203・・・・感磁部 204・・・・結晶基板 205・・・・p形層の形成領域 206・・・・n形入力電極 207・・・・n形出力電極 208・・・・Au配線 209・・・・p形入力電極 101, an input electrode 102, an output electrode 103, a magnetic sensing part 104, a crystal substrate 201, an input electrode formation area 202, an output electrode formation area 203 ... Magnetic sensing part 204... Crystal substrate 205... P-type layer formation region 206... N-type input electrode 207... N-type output electrode 208. 209 ··· p-type input electrode

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−27075(JP,A) 特開 昭63−151090(JP,A) 特開 昭56−96886(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 43/06 G01R 33/07 G11B 5/37 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-27075 (JP, A) JP-A-63-151090 (JP, A) JP-A-56-96886 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 43/06 G01R 33/07 G11B 5/37

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半絶縁性GaAs基板の表面に形成され
たn形のGaAs層からなる感磁部および各々一対をな
す入力電極部並びに出力電極部と、該入力電極部並びに
出力電極部の表面にそれぞれオーミック接触をなすよう
に形成された一対の入力電極および一対の出力電極とを
有するホール素子において、前記入力電極部の一方のn
形GaAs層とpn接合をなしてp型のGaAs層が形
成され、該p型GaAs層の表面にp形オーミック電極
が形成され、該p形オーミック電極と前記入力電極部の
他の一方に形成された入力電極とが配線により電気的に
結ばれていることを特徴とするホール素子。
1. A magnetic sensing part comprising an n-type GaAs layer formed on a surface of a semi-insulating GaAs substrate, and a pair of input and output electrode parts, and surfaces of the input and output electrode parts. A Hall element having a pair of input electrodes and a pair of output electrodes formed so as to make ohmic contact with each other.
A p-type GaAs layer is formed by forming a pn junction with the p-type GaAs layer; a p-type ohmic electrode is formed on the surface of the p-type GaAs layer; and a p-type ohmic electrode is formed on the other of the input electrode portion and the other side. Characterized in that the input element is electrically connected to the input electrode by a wiring.
JP33315992A 1992-12-14 1992-12-14 Magnetoelectric conversion element Expired - Fee Related JP3221114B2 (en)

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JP33315992A JP3221114B2 (en) 1992-12-14 1992-12-14 Magnetoelectric conversion element

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Publication Number Publication Date
JPH06181348A JPH06181348A (en) 1994-06-28
JP3221114B2 true JP3221114B2 (en) 2001-10-22

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JP (1) JP3221114B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656547A (en) * 1994-05-11 1997-08-12 Chipscale, Inc. Method for making a leadless surface mounted device with wrap-around flange interface contacts

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