JP3287048B2 - Heterojunction magnetoelectric transducer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoelectric transducer using a heterojunction of GaInAs and an InP compound semiconductor material,
In particular, the present invention relates to a novel and highly reliable heterojunction magnetoelectric conversion element having excellent surge resistance and capable of maintaining the stability of element characteristics for a long period of time.

[0002]

2. Description of the Related Art A hole (Ha) is used as one of so-called magneto-electric conversion elements for detecting a magnetic field and converting the intensity into an electric signal.
11) Elements are known. The Hall element usually has a periodic elemental rule such as silicon (Si) or germanium (Ge).
Group IV elemental (elemental) semiconductors and gallium arsenide (G
aAs), indium arsenide (InAs), etc., a so-called III compound obtained by combining a group III element and a group V element of the periodic table.
Group V binary compound semiconductors or mixed crystal semiconductors thereof are used. Regardless of which semiconductor material is used, a Hall element is a type of sensor that utilizes the Hall voltage generated by the movement of electrons in these semiconductors when the semiconductor material that composes it is placed in a magnetic field. Yes, it is often used for rotation detection.

[0003] As described above, in addition to a simple substance semiconductor of Si as described above, a group III-V compound semiconductor such as InSb, InAs or GaAs is used. In an actual Hall element, for example, an InSb Hall element is used. Like InS
b In some cases, the bulk crystal itself is used as the magnetic sensing part of the device, but in most cases, VP is implanted into a high-resistance GaAs single crystal substrate or the like, or a similar VP is deposited on a similar single crystal substrate.
A semiconductor layer formed by a vapor phase growth method such as E, MOCVD, MBE or a liquid phase growth method is used as a magnetically sensitive portion. Conventionally, an element such as an ohmic electrode serving as an input / output electrode is formed by directly depositing a gold / germanium alloy or the like on the layer serving as the magnetic sensing portion thus formed. Is a general Hall element.

[0004] Recently, attempts have been made to form a heterojunction between GaInAs and InP, which is a kind of mixed crystal of III-V compound semiconductors, and to use this as a new high-sensitivity Hall element (for example, see Japanese Patent Application Laid-Open (JP-A) no. 60-198877). MOCVD for such new Hall elements
Ohmic input / output electrodes are deposited on the thin film layer grown by the method or the like to form a Hall element.

The above-mentioned ohmic electrode is an indispensable element in the configuration of the Hall element irrespective of the material of the semiconductor. However, it is needless to say that the electrical characteristics of the Hall element affect the characteristics of the Hall element. Further, from the viewpoint of the reliability of the device, the surge resistance characteristics of the ohmic electrode and the like are important in operating the device stably for a long period of time.

[0006] A general method that has been conventionally performed with the aim of improving the surge resistance is to form an external circuit including a component having a function of absorbing or mitigating an electric surge by:
This is to accompany a drive circuit for the Hall element. In this conventional method, although a surge resistance function can be added to the Hall element, the increase in the area occupied by the Hall element itself cannot be avoided, and the precise distribution of the magnetic field strength in a minute area cannot be avoided. There has not been provided a small Hall element having a shape required for measurement or the like.

On the other hand, the present inventors have proposed to provide, for example, a p / n junction on the input electrode side in order to provide surge resistance inside the Hall element (see Japanese Patent Application No. 4-333159). Taking a Hall element made of a III-V group compound semiconductor such as GaAs as an example, a semiconductor layer exhibiting n-type conduction is usually employed as the magnetic sensing part due to mobility. Here, in order to obtain a p / n junction, zinc (Zn), magnesium (Mg), beryllium (B) of group II of the periodic table, which is a p-type impurity for a group III-V compound semiconductor, is used.
e), cadmium (Cd), or the like may be implanted into a desired region of the n-type magnetosensitive layer by a diffusion method or an ion implantation method. However, by any of the process methods, Zn and M, which are Group II elements of the periodic table, are used as p-type impurities.
As long as g, Be, Cd, and the like are used, these elements generally have a large diffusion constant in a group III-V compound semiconductor, so that the junction interface becomes unstable, and a good p / n junction is easily and stably formed. There were drawbacks that could not be obtained.

In addition, when a predetermined amount of Zn in the group II element is ion-implanted into a desired region in order to form a good p / n junction, since Zn is relatively large in mass, it is difficult to perform ion implantation. Implants often suffer crystallographic damage. Furthermore, in order to recover such damage, the implanted body is subjected to heat treatment. However, the temperature of the heat treatment cannot be set to a very high temperature for Zn or the like having a large diffusion constant.
Therefore, a situation in which damage remains inside the implanted body is inevitably caused, and as a result, it has been hindered to improve the characteristics of the Hall element.

[0009]

SUMMARY OF THE INVENTION In view of the above-mentioned conventional disadvantages, the present invention has been made to improve the reliability of a heterojunction Hall element having a heterojunction of GaInAs and InP. The purpose of the present invention is to provide a simple and more easily surge-resistant function inside the element.

[0010]

That is, the present inventors have proposed Ga
In a Hall element provided with a hetero (heterogeneous) junction between an InAs layer and an InP layer, a group III-V compound is added to the GaInAs layer and the InP layer in a region where one of a pair of input electrodes is to be formed. Carbon (C) that is difficult to diffuse in semiconductors
The problem is solved by forming a p / n junction at a portion where the input electrode is formed by adding the ion by ion implantation or the like.

Normally, in forming a heterojunction composed of GaInAs and InP in consideration of the application to the above-mentioned hole element, a semi-insulating high-resistance InP single crystal substrate is used. Practically, In with a specific resistance of about 10 ⁴ Ω · cm or more
In general, a P substrate is used, and these can be easily manufactured by a vertical Bridgman method called an LEC method, a VB method, or the like, and there is no difficulty in obtaining a material for implementing the present invention.

On such a high-resistance InP substrate, InP and Ga _x In ₁ -x As (x
Represents a mixed crystal ratio, and usually 0.4 ≦ x ≦ 0.6 is desirable. Are not particularly limited in the growth method, and a liquid phase epitaxial growth method (LPE method)
Also by the molecular beam epitaxial growth method (MBE
Method) and metal-organic thermal decomposition chemical vapor deposition, so-called MOCVD
MO (also called MOVPE, OMCVD or OMVPE method), MO that is a combination of both MBE method and MOCVD method
-The MBE method may be used. However, at present In
MOCVD is often used exclusively for P growth,
In particular, in an atmospheric pressure (atmospheric pressure) MOCVD method using cyclopentadienyl indium (C ₅ H ₅ In) having a monovalent valence as a starting material of In, high-quality InP and G are used.
aInAs can be obtained.

When forming a heterojunction, In
The order of laminating the P layer and the Ga _X In _1-X As layer is not particularly limited, but in order to obtain a high quality Ga _X In _1-X As layer, first, the InP layer is formed on the above-described InP substrate. It is common to deposit and then grow a Ga _x In _1-x As layer. By providing such a heterojunction, for example, Ga _x In which is required to have high electron mobility is used.
An effect is obtained such that diffusion of impurities from the substrate crystal into the _1-x As epitaxial growth layer can be suppressed. Further, since an effect such as suppression of propagation of crystal defects or the like existing in the substrate to the epitaxial growth layer is produced, there is an advantage that electron mobility is improved and thus sensitivity of the Hall element is increased.

Although the number of junctions is not limited in this heterojunction, the total thickness of the layers deposited on the InP crystal substrate generally exceeds 5 μm in consideration of the mesa etching and the like in forming the device. It would be reasonable to prevent the unbalance rate from worsening.

A Hall element is manufactured using an epitaxial wafer having such a configuration as a base material. To form a Hall element, first, a pair of ohmic input and output electrodes are formed on the wafer. In a general Hall element, gold (Au) / germanium capable of forming an ohmic electrode with respect to the n-type layer corresponding to the use of a layer exhibiting n-type conduction as the magnetosensitive layer from the viewpoint of mobility. Metal electrode materials such as (Ge) alloys are used exclusively.

In the present invention, when forming the above-mentioned ohmic electrode, the GaInAs layer and the InIn layer existing in the region where one of the pair of input electrodes for input is formed.
In the P layer, carbon (C) belonging to Group IV of the periodic table of elements in advance
Is added by making full use of ion implantation or the like. Here, carbon is used as an impurity for GaInAs and InP.
Considering the effect on conduction type of carbon, carbon is GaInAs
Acts as a p-type impurity, while InP acts as an n-type impurity. That is, taking the ion implantation method as an example, by implanting carbon ions, it is possible to simultaneously and simply form a p / n junction composed of GaInAs and InP. Further, carbon has a much smaller diffusion constant of the III-V compound semiconductor than that of the group II element, and thus can constantly obtain a p / n junction having stable characteristics. It is necessary to implant carbon up to the crystal layer forming the heterojunction, and although it depends on the thickness of the heterojunction, it is possible to implant carbon to a depth of 5000 ° or more by implanting with energy of 200 to 400 kV. The dose may be 10 ¹³ cm ^-2 or more.

The method of forming a p / n junction utilizing the difference in the effect of carbon on the conductivity types of GaInAs and InP does not need to be limited to the above-described ion implantation method. For example, M
By doping carbon by OCVD or the like, p
GaInAs and n-type InP may be obtained. Furthermore, if those layers are selectively grown in a desired region by an epitaxial growth method, a p / n junction can be easily formed with less troublesome process.

In addition, when a p / n junction is formed in a specific region by applying buried growth with carbon doping by an epitaxial growth method or selective growth, ap / n junction is formed by ion-implanting carbon. In doing so, generally, the implanted element does not become electrically active only by implantation, but needs to be activated by performing a subsequent heat treatment called implantation annealing or the like.
Since this annealing is performed at a relatively high temperature of about 600 ° C. to 900 ° C. for several minutes to several tens of minutes, impurities such as Zn, Mg, Be, and Cd which have been frequently used as p-type impurities are easily diffused. In this case, the metal is diffused during annealing, and is a factor that causes instability of the bonding characteristics. Even when a p / n junction is formed by ion implantation of carbon according to the present invention, it is needless to say that annealing for electrically activating the implanted carbon is required. In diffusion, carbon is Zn, M
It has a diffusion constant about two orders of magnitude smaller than that of g, etc., so that it hardly diffuses under almost the above-mentioned common-sense annealing conditions, and thus has the advantage of being able to reproduce excellent junction characteristics. .

In manufacturing a Hall element using a wafer having a p / n junction as described above as a base material, no special special device is required, and a well-known processing technique such as photolithography and etching is used. Then, the above-mentioned Au / Ge alloy or the like may be applied to the surface of the wafer by, for example, a vacuum evaporation method to form an ohmic electrode. However, the p-type semiconductor layer is not Au / Ge alloy but Au / Zn alloy or Au.
In general, a Be alloy or the like is used as an electrode material. In any case, providing the p / n junction of carbon according to the present invention does not limit the electrode material and the electrode forming method.

Next, the present inventors have studied the conventional GaInAs /
The electrical characteristics of the InP Hall element and a new Hall element using a GaInAs layer containing carbon in a specific region and an InP layer according to the present invention were compared. In the Hall element according to the present invention, a so-called undoped InP layer is first deposited on a semi-insulating InP crystal substrate having a specific resistance of about 10 ⁷ Ω · cm to a thickness of about 1000 °, and then the thickness is reduced. About 4000% of undoped Ga _0.47 In
An epitaxial wafer on which a _0.53 As layer (mixed crystal ratio = 0.47) was grown was used. On this wafer, carbon having a mass number of 12 was ion-implanted into one of the regions where the input electrodes were formed. At the time of the implantation, the wafer was covered with a usual photoresist material so that carbon ions were not implanted into other regions of the wafer. Thereafter, an ohmic electrode was formed through a known process to obtain a Hall element.

The outline of the result of comparing the electrical characteristics will be described here. According to the present invention, a GaInAs layer containing carbon and an InP layer containing carbon are provided in a region where an input electrode is to be formed.
By forming the junction, a GaInAs / InP Hall element having excellent non-conventional withstand voltage characteristics was manufactured. In addition, the characteristics of the p / n junction of the Hall element according to the present invention were investigated and examined in detail from the general current-voltage characteristics, and the results of the investigation show that there is a high breakdown that is unconventional so as to match the implantation conditions of carbon ions. The voltage was shown, and the reproducibility and uniformity of the voltage were good, demonstrating the superiority of providing a p / n junction using carbon.

Further, as a result of intensive studies by the present inventors, for the purpose of comparing the above-mentioned electrical characteristics, the present invention is not limited to the manufacturing conditions of the Hall element. The order is not limited, and the film thickness of each layer is not limited thereto. A clear difference in characteristics appears depending on whether or not a p / n junction is provided by carbon, and the present invention is applied to wafers having the same configuration. In the Hall element in which the p / n junction made of the layer containing carbon based on the input electrode portion was provided, the surge resistance was clearly improved.

Further, the growth method of the epitaxial layer is not necessarily required to be the same. For example, the InP layer is grown by normal pressure or reduced pressure MOCVD, and GaInAs for heterojunction with them is grown by another method such as MBE. There is no problem.

[0025]

By utilizing the fact that carbon acts as a p-type impurity with respect to GaInAs and acts as an n-type impurity with respect to InP, a region for forming an input electrode of a Hall element having a GaInAs / InP heterojunction is utilized. GaI containing carbon
A layer composed of an nAs layer and an InP layer is provided.
By providing the / n junction, an effect of increasing the electrical resistance of the Hall element, particularly the surge resistance, than ever before is brought about.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail based on two embodiments. <Embodiment 1> FIG. 1 shows GaInAs / I in which GaInAs containing carbon and InP are provided in a specific region according to the present invention.
It is the figure which showed typically the plane of the nP heterojunction Hall element. FIG. 2 is a line A- of the schematic plan view shown in FIG.
It is the schematic of the cross section along A '. In forming the heterojunction, first, a semi-insulating high-resistance InP single-crystal substrate (101) having a plane orientation (100) having a specific resistance of about 10 ⁷ Ω · cm, to which iron (Fe) is added, is added to the heterojunction. An undoped InP layer (102) to which no impurity (dopant) is intentionally added as a first layer for forming
Grown in thickness. The carrier concentration of the InP layer (102) is about 2 × 10 ¹⁵ cm ⁻³ . Thereafter, undoped Ga _0.47 In is used as a second layer for forming a heterojunction.
_0.53 As (103) (Carrier concentration is about 2 × 10 ¹⁶ cm
^-3 ) is deposited to a thickness of 4000 °, and GaInAs and I
A heterojunction consisting of nP was formed. In this embodiment, the InP layer (102) and the GaInAs layer (103)
Atmospheric pressure MOCVD using monovalent cyclopentadienyl indium (C ₅ H ₅ In) as an In source
However, the growth method of both layers does not need to be limited to this, and the growth method may be different between the InP layer and the GaInAs layer. Should be formed.

Next, the outermost GaInAs layer (103)
Over the entire surface with a normal organic photoresist agent,
Thereafter, the GaInAs layer (103) was exposed only in the region (105) where carbon ions were to be implanted by a known photolithography technique. Thereafter, carbon having a mass number of 12 is ion-implanted using a usual implantation apparatus, and carbon-containing I
An nP layer (106) and a GaInAs layer (107) were formed. For this injection, the accelerating voltage is 300 KV
And the dose was set to 5 × 10 ¹³ cm ⁻² , respectively. In the present embodiment, the injection condition is set, but of course, the injection condition is not fixed. After the implantation, the above-mentioned resist agent used as a mask material at the time of covering the whole surface is peeled off with a mixed solution of an organic solvent, and then the carbon-implanted wafer is annealed at a temperature of 750 ° C. for 20 minutes ( (Activation heat treatment) to electrically activate the implanted carbon. Thereby, p inside the GaInAs layer (103)
GaInAs layer (107) and surrounding n-type GaInA
A p / n junction can be formed planarly with the s layer (103).
When the outermost layer is GaInAs as described in this embodiment,
In this way, a p / n junction can be formed without having to remove a specific layer before and after the implantation of carbon (compare with Example 2 described later).

Thereafter, the surface of the annealed wafer was again covered entirely with an organic resist agent. Next, only the resist agent existing in the region where the input electrodes (108a and 108b) and the output electrode (109) are to be formed is removed by using a known photolithography technique to expose the surface of the GaInAs layer (103). I was sorry. Thereafter, an Au.Ge alloy containing about 13% by weight of Ge was vacuum-deposited. Thereafter, the wafer was immersed in an organic solvent mixed solution, and the resist was peeled off. At the same time, an alloy film which was not necessary for the production of the device applied on the resist agent by vapor deposition was removed by a so-called lift-off method. Next, the wafer on which the alloy film serving as an electrode was adhered was subjected to alloying (heat treatment to obtain an ohmic electrode) at a temperature of 420 ° C. for several minutes.

Further, the region (1
05) and the other input electrode (108b) were provided with a metal wiring (110). This wiring (110) is formed by an n-type GaInAs existing immediately below the input electrode (108a) and a p-type GaInAs layer formed by implanting carbon.
An excessive current flowing when a voltage higher than the allowable voltage is suddenly applied to the / n junction is released to the electrode at the ground potential ((108b) in this embodiment) to protect the element from destruction. Plays the role of road.

In comparison with the electrical characteristics of the new Hall element manufactured as described above, especially the resistance of the new Hall element, that of the conventional Hall element not depending on the present invention, in the present invention, even when a voltage of 45 V is applied instantaneously in a pulsed manner. About 87% or more elements remain,
After that, normal operation was demonstrated. On the other hand, in the conventional Hall element, almost half or more were destroyed by the application of the instantaneous voltage of 32 to 35 V, showing the fragility with respect to the surge resistance and the effect according to the present invention.

<Embodiment 2> FIG. 3 is a diagram schematically showing a plane view of a Hall element according to Embodiment 2 of the present invention. FIG. 4 is a schematic cross-sectional view taken along line BB ′ of the plane of the device shown in FIG. Unlike the first embodiment, the present embodiment differs from the first embodiment in the order of stacking the epitaxially grown layers on the InP substrate crystal. That is, in this embodiment, the plane orientation is (100),
First, on a semi-insulating InP single crystal substrate (301) having a thickness of about 350 μm and a specific resistance of 10 ⁷ Ω · cm, undoped Ga _0.47 In _0.53 As having a carrier concentration of about 2 × 10 ¹⁶ cm ^-3.
(Mixed crystal ratio = 0.47) (302) was grown to a film thickness of 4000 °. Next, an InP layer (303), also undoped, having a carrier concentration of about 2 × 10 ¹⁵ cm ⁻³ and a thickness of 1000 ° was grown to form a heterointerface (304).

Next, prior to forming the carbon-containing GaInAs layer by the carbon ion implantation method as described in Example 1, the InP layer in the region (305) where the carbon-containing p-type layer is to be formed (303) is selectively removed using a known photolithography technique and etching technique, and the GaInAs layer (30) immediately below the InP layer (303) is removed.
2) was exposed. This can be seen from a schematic sectional view of FIG.
As shown in FIG. 3, the GaInAs layer (302) and the InP are formed at the end face of the p-type layer formation region (305) by carbon ion implantation.
The structure has a step between the layer (303).

Thereafter, through a process similar to that described in Example 1, an InP layer portion (307) containing the same carbon as the GaInAs layer portion (306) containing carbon is provided. An n-junction was formed. Further, an input electrode (308a) (308b) and an output electrode (309) were formed. Metal wiring (31) from the GaInAs layer (302) to the input electrode (308b) having no p / n junction
0) was also provided. This metal wiring (310) was formed using Au as in the first embodiment.

When the electrical characteristics, especially the durability, of the new Hall element manufactured in this way are compared with those of the conventional Hall element which does not depend on the present invention, about the same conditions as in the first embodiment under the condition of applying a 45V voltage pulse. 82% or more of the elements remained, and normal operation was maintained thereafter. On the other hand, in the case of the conventional Hall element, almost half or more were destroyed by the application of an instantaneous voltage of about 30 V, and almost the same result as the comparison result with the conventional Hall element described in Example 1 was obtained. It showed fragility to resistance and clearly showed the effect according to the present invention.

In the case where the InP layer is on the outermost surface as in this embodiment, it is necessary to consider the element forming process in consideration of the fact that carbon impurities act as n-type impurities with respect to InP. That is, for example, it is possible to simultaneously form a GaInAs layer containing carbon and an InP layer by ion implantation if the conditions for implanting carbon are appropriately selected and selected, or multiple implantations are performed. Since the n-type impurity carbon is further ion-implanted into the magnetic layer, only the n-type InP layer appears on the outermost surface, and the p-type GaInA formed simultaneously by the implantation of carbon ions is formed.
Special measures are required to form an electrode that is in electrical contact with the s layer.

In this regard, in the present embodiment, the n-type InP layer ((303) in the second embodiment) in a predetermined region is removed before carbon ion implantation, and the n-type InP layer existing immediately below the n-type InP layer is removed. By exposing the GaInAs layer (302) in advance, the wiring (310) is brought into contact with the GaInAs (306) converted into p-type by direct carbon ion implantation later. In the case where n-type InP is present in the outermost layer, the method of electrically contacting the GaInAs layer immediately below is not limited to this. For example, carbon ions are implanted into a predetermined region, and After that, some n in a predetermined area
The p-type GaInAs layer whose conductivity type has been converted to p-type by carbon ion implantation may be exposed by removing the -InP layer.

When n-type InP is present in the outermost layer as described above, it is good to remove the n-type InP layer, but the area to be removed is made smaller in plane area than the area into which carbon ions are implanted. There is a need. If the n-type InP where the carbon ions are implanted or the InP layer formed by implanting the carbon ions is removed over the entire region where the carbon ions are implanted, the n-type InP is formed directly under the appropriate process. This is because a portion overlapping with a p-type GaInAs layer containing a certain carbon is eliminated, and thus a p / n junction cannot be formed.

[0038]

According to the GaInAs / InP heterojunction Hall element, there is an effect of remarkably improving surge resistance.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a plane of a Hall element according to the present invention.

FIG. 2 shows a line A of the Hall element according to the present invention shown in FIG.
It is a figure which shows the cross section along -A 'typically.

FIG. 3 is a view schematically showing a plane of a Hall element according to the present invention.

FIG. 4 shows a line B of the Hall element according to the present invention shown in FIG.
It is a figure which shows the cross section along -B 'typically.

[Explanation of symbols]

 (101) Fe-doped high-resistance InP single-crystal substrate (102) InP growth layer (103) GaInAs growth layer (104) GaInAs / InP heterojunction interface (105) Carbon ion implantation region (106) Carbon-doped InP layer portion (107) Carbon-doped GaInAs portion (108a) Input electrode (108b) Input electrode (109) Output electrode (110) Metal wiring (301) Fe-doped high-resistance InP single crystal substrate (302) GaInAs growth layer (303) InP growth layer (304) GaInAs / InP heterojunction interface (305) Carbon ion implantation region (306) Carbon-doped GaInAs portion (307) Carbon-doped InP layer portion (308a) Input electrode (309) Output electrode (309b) Input electrode (310) Metal wiring

Continued on the front page (72) Inventor Takashi Udagawa 1505 Shimokagemori, Chichibu City, Saitama Prefecture Showa Denko KK Chichibu Laboratory (56) References JP-A-60-198877 (JP, A) JP-A-4-229666 ( JP, A) JP-A-64-57755 (JP, A) JP-A-5-29716 (JP, A) JP-A-1-132184 (JP, A) JP-A-63-27075 (JP, A) JP-A-63-151090 (JP, A) JP-A-56-96886 (JP, A) JP-A-62-254473 (JP, A) JP-A-6-181348 (JP, A) Journal of Applied Physics, Vol. 70, No. 2, pp. 894-900 (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 43/06 G01R 33/07 JICST file (JOIS)

Claims (2)

(57) [Claims] An InP layer and an n-type GaInAs layer are sequentially formed on an InP single crystal substrate, and the n-type GaInA layer is formed.
In a Hall element having a pair of input electrodes and a pair of output electrodes formed on the surface of an s layer, a p-type GaInAs layer portion containing carbon as an impurity is adjacent to an n-type GaInAs layer in contact with one of the input electrodes. Is formed, and n-type GaI
A p / n junction is formed between the nAs layer and the p-type GaInAs layer, and a metal wiring is provided between the p-type GaInAs layer and the other of the input electrodes. element. 2. A Hall element in which a GaInAs layer and an InP layer are sequentially formed on an InP single crystal substrate, and a pair of input electrodes and a pair of output electrodes are formed on the surface of the InP layer. An n-type InP layer containing carbon is provided in contact with one of the electrodes;
A p-type GaInAs layer containing carbon is provided below the layer, and a p / n junction is formed between the n-type InP layer and the p-type GaInAs layer, and the p-type GaInA is formed.
A part of the InP layer on the s layer is removed to remove p-type GaIn.
A part of the surface of the As layer is exposed, and the p-type GaI
A Hall element, wherein a metal wiring is provided between the nAs layer portion and the other of the input electrodes.