JP3246401B2 - Heterojunction bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor excellent in high speed and high frequency.

[0003]

2. Description of the Related Art FIG. 8 shows a conventional NPN type A as an example.
1 shows a structural cross-sectional view of an lGaAs / GaAs heterojunction bipolar transistor. On a semi-insulating GaAs substrate 1,
n ⁺ -GaAs collector contact layer 2, n-GaAs
A collector layer 3, a p ⁺ -AlGaAs composition gradient base layer 4, an n-AlGaAs emitter layer 5, and an emitter contact layer 6 made of n ⁺ -GaAs are formed in this order.
A collector electrode 7c, a base electrode 7b, and an emitter electrode 7e are provided on the collector contact layer 2, the base layer 4, and the emitter contact layer 6. Further, the insulating region 1a is formed by proton implantation, and separates from other devices.

FIG. 9 shows an energy band structure diagram in an operating state in which a bias is applied to the heterojunction bipolar transistor shown in FIG. An emitter-base voltage V _BE is applied between the emitter layer and the base layer, and a base-collector voltage V _CB is applied between the base layer and the collector layer. Electrons flow sequentially from the emitter layer to the collector layer via the base layer. Holes are injected from the base layer,
It flows to the emitter layer. When the base layer has a composition gradient base structure, an internal electric field for accelerating electrons is generated, and the base transit time is significantly reduced as compared with a composition uniform base structure in which electrons move by diffusion.

[0005]

As described above, in a heterojunction bipolar transistor, a reduction in base transit time has been realized. Therefore, in order to further improve the speed of the heterojunction bipolar transistor, it is important to shorten the collector transit time. High-energy electrons that have passed through the base layer enter the collector layer, and a high electric field of 50 kV / cm or more is applied to the collector depletion layer, so that the electrons have a large effective mass from the Γ valley of the conduction band. There is a problem that the state transits to the L valley (scattering between valleys), the drift speed is reduced, and the high-speed performance is impaired. Therefore, in order to reduce the collector running time, it is necessary to run at high speed while suppressing the scattering between valleys.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to shorten the carrier transit time of carriers and improve the high-speed operation of a heterojunction bipolar transistor.

[0007]

In the heterojunction bipolar transistor according to the present invention, the first collector layer and the second collector layer are alternately formed on the base layer side of the collector layer which is depleted in a bias application state. The first collector layer was composed of a semiconductor layer whose composition was graded so that the forbidden band width increased toward the semi-insulating substrate.

Further, the second collector layer is formed of a semiconductor layer having a thickness shorter than a moving distance of carriers in a relaxation time of inter-valley scattering.

Alternatively, the second collector layer is composed of a semiconductor layer having a composition gradient such that the forbidden band width decreases toward the substrate.

[0010]

According to the hetero-junction bipolar transistor of the present invention, the composition gradient in the first collector layer is such that the forbidden band width increases toward the semi-insulating substrate, so that the electric field is reduced. The energy of carriers entering with high energy is reduced. Carriers having low energy passing through the first collector layer enter the second collector layer, are accelerated by a high electric field, and run at high speed with an overshoot of the drift velocity as shown in FIG. This overshoot occurs during the time when valley carriers gain high energy and inter-valley scattering occurs.

Further, if the second collector layer is shorter than the carrier movement distance during the inter-valley scattering relaxation time, the carriers enter the next first collector layer before undergoing inter-valley scattering, and the energy is relaxed. You. It again enters the next second collector layer again with low energy. FIG. 7 shows how the drift speed changes during this time. FIG.
Indicates the drift velocity of carriers in one set of the first and second collector layers. In the collector layer in which the first and second collector layers are repeatedly stacked, the carrier repeats the above-described movement in the collector layer, so that the collector transit time of the heterojunction bipolar transistor is greatly reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to the drawings.

FIG. 1 is a cross-sectional view showing the structure of a first embodiment of the present invention, which is constituted by the parts indicated by the reference numerals in the figure. FIG. 2 is an enlarged view of the structure of the base layer and the collector layer. Here, the collector layer of the first conductivity type is n-In _x Ga _{1 -x} As, and the base layer of the second conductivity type is p-type.
-In _x Ga _{1 -x} As, the first conductivity type emitter layer is n-
An example of an NPN heterojunction bipolar transistor composed of Al _x Ga _{1 -x} As will be described.

On a GaAs semi-insulating substrate 1, the dopant is Si, the impurity concentration is 5 × 10 ¹⁸ cm ^-3 and the thickness is 500.
Collector contact layer 2 of ⁰ ° n ⁺ -GaAs
Is formed by a crystal growth method such as the MBE method or the MOVPE method. Next, the impurity concentration is 5 × with Si as the dopant.
The lower collector layer 3d of the normal structure made of n-GaAs having a thickness of 10 ¹⁶ cm ^-3 and a thickness of 2000 ° is formed by MBE or MOV.
It is formed by a PE method or the like.

An n-In _x G layer having a dopant concentration of Si and an impurity concentration of 5 × 10 ¹⁶ cm ^-3 and a thickness of 3000 ° is formed thereon.
An upper collector layer 3u made of a _1-x As is formed.
The upper collector layer 3u has a thickness that is shorter than the carrier movement distance during the relaxation time of inter-valley scattering with the first collector layer 3a whose composition is graded so that the band gap increases toward the semi-insulating substrate. This is a layer in which second collector layers 3b having a uniform composition having the following structure are alternately stacked.

In order to increase the maximum oscillation frequency f _max , it is necessary to use a high base-collector voltage in order to reduce the base-collector capacitance. This device structure requires about 1.5 V. And for that reason,
Since the built-in voltage between the base and collector is 1.3V,
In the operating state, a voltage of about 3 V is applied between the base and the collector. This indicates that the collector depletion layer thickness in the operating state of this device is about 2500 °. The thickness of the upper collector layer corresponds to the collector depletion layer thickness in the operating state of the device. In a GaAs-based material, a valley transition from the Γ valley of the conduction band occurs at an energy of about 0.3 eV. In the present structure, about 3 V is applied to the depletion layer portion between the base and the collector of about 3000 ° in the operating state, including the applied voltage and the built-in voltage. Therefore, about 3
It is considered that a voltage of 0.3 V or more is applied at a thickness of 00 ° or more, and electrons obtain energy of 0.3 eV or more, causing inter-valley scattering. Therefore, the scattering relaxation distance between valleys is estimated to be about 300 ° or less, and the thickness of the second collector layer is set to 300 °. If the thickness of the first collector layer is set to the same level, it is necessary to form five layers. In _x Ga _1-x A gradually in the five first collector layers
The composition of s at the interface between the base layer and the collector layer, x = 0.
Move closer to 1. FIG. 3 shows the composition structure of the base layer and the collector layer of the first embodiment.

Further, p ⁺ -In _x having a dopant concentration of Be and an impurity concentration of 6 × 10 ¹⁹ cm ^-3 and a thickness of 400 ° is further provided.
Ga _1-x As (x: 0.1 → 0) composition gradient base layer 4
Is formed by the MBE method. When the dopant is C,
It is formed by the MOVPE method. Here, → in the parenthesis is a direction toward the semi-insulating substrate side.

On this base layer, n-type silicon having a dopant concentration of Si and an impurity concentration of 6 × 10 ¹⁷ cm ^-3 and a thickness of 200 ° is formed.
Al _x Ga _{1 -x} As (x: 0 → 0.25), Si as dopant, impurity concentration of 6 × 10 ¹⁷ cm ^-3 and thickness of 15
N-Al _x Ga _{1 -x} As (x = 0.25) with a dopant of Si and an impurity concentration of 6 × 10 ¹⁷ cm
Thickness 500Å by _{^{-3 n-Al x Ga 1-}} x As (x: 0 →
0.25) by MBE or MOV
It is formed by a PE method or the like. On top of that, the dopant is S
As i, the impurity concentration is 6 × 10 ¹⁸ cm ⁻³ and the thickness is 1200.
Å of n ⁺ -GaAs, a thickness of 500Å at an impurity concentration of the dopant as ^{Si 2 × 10 18 cm -3 n} + -In x G
a _1-x As (x: 0 → 0.5), n ⁺ having a dopant concentration of Si and an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of 500 °
An emitter contact layer 6 made of -In _x Ga _{1 -x} As (x = 0.5) is formed by MBE or MOVPE.

This is processed into a mesa shape using an etching technique, and a collector electrode 7c, a base electrode 7b, and an emitter electrode 7e are formed on the collector contact layer, the base layer, and the emitter contact layer using a vapor deposition technique. . Further, the insulating region 1a is formed by proton implantation, and separates from other devices.

FIG. 4 shows an energy band structure in an operating state in which a bias is applied to the heterojunction bipolar transistor of the first embodiment. In the first collector layer, the electric field is relaxed because the composition is graded so that the forbidden band width increases toward the semi-insulating substrate side, and the energy of carriers entering with high energy is relaxed. You. Carriers having a small energy having passed through the first collector layer enter the second collector layer, are accelerated by a high electric field, cause an overshoot of the drift speed, and travel at high speed.

Since the second collector layer is shorter than the carrier travel distance during the inter-valley scattering relaxation time, the carriers enter the next first collector layer before undergoing inter-valley scattering and relax the energy. Is done. It again enters the next second collector layer again with low energy. The carrier transit time in the heterojunction bipolar transistor is greatly reduced by the carrier repeating the above-described movement in the collector layer. Also, in this structure, the collector layer is formed in the above-mentioned multilayer structure, so that the collector layer thickness is sufficient, and it is not necessary to introduce the same second conductivity type layer as the base layer into the collector layer. The breakdown voltage between the collectors is not reduced.

FIG. 5 shows the composition of the base layer and the collector layer of the second embodiment. The structural sectional view is the same as that of the first embodiment. In this structure, the second collector layer of the first embodiment was constituted by a layer whose composition was inclined so that the band gap became smaller toward the semi-insulating substrate. In this embodiment, the collector layer of the first conductivity type is n-Al _x Ga _1-x
As, the base layer of the second conductivity type is p-Al _x Ga _1-x A
s, the emitter layer of the first conductivity type is n-Al _x Ga _1-x A
An example of an NPN heterojunction bipolar transistor composed of S.s.

On a GaAs semi-insulating substrate 1, the dopant is Si, the impurity concentration is 5 × 10 ¹⁸ cm ^-3 and the thickness is 500.
Collector contact layer 2 of ⁰ ° n ⁺ -GaAs
Is formed by a crystal growth method such as the MBE method or the MOVPE method. Next, the impurity concentration is 5 × with Si as the dopant.
The lower collector layer 3d of the normal structure made of n-GaAs having a thickness of 10 ¹⁶ cm ^-3 and a thickness of 2000 ° is formed by MBE or MOV.
It is formed by a PE method or the like.

On top of this, n-Al _x G having an impurity concentration of 5 × 10 ¹⁶ cm ^-3 and a thickness of 3000 ° using Si as a dopant.
An upper collector layer 3u made of a _1-x As is formed.
The upper collector layer 3u has a thickness that is shorter than the carrier movement distance during the relaxation time of inter-valley scattering with the first collector layer 3a whose composition is graded so that the band gap increases toward the semi-insulating substrate. And a second collector layer 3b having a composition inclined so that the forbidden band width decreases toward the semi-insulating substrate side. The thickness of the second collector layer was 300 °. If the thickness of the first collector layer is set to the same level, it is necessary to form five layers.
The first collector layer is n-Al _x Ga _{1 -x} As (x: 0 →
0.1), the second collector layer is n-Al _x Ga _1-x As
(X: 0.1 → 0).

Further, p ⁺ -Al _x having a dopant concentration of Be and an impurity concentration of 6 × 10 ¹⁹ cm ^-3 and a thickness of 400 ° is further provided.
A composition gradient base layer 4 of Ga _1-x As (x: 0.12 → 0) is formed by MBE. When the dopant is C, it is formed by the MOVPE method.

[0026] The base layer, a dopant of Si as an impurity concentration of thickness 200Å by 6 × 10 ¹⁷ cm ^-3 n-
Al _x Ga _{1 -x} As (x: 0.3 → 0.12), n-Al _x Ga _{1 -x} As (x = 1.3 × 0.17 cm ⁻³ , impurity concentration 6 × 10 ¹⁷ cm ⁻³ and thickness 1500 °) 0.3),
And an impurity concentration of 6 × 10 ¹⁷ c using Si as a dopant.
m thick 500Å at _{^{-3 n-Al x Ga 1-}} x As (x: 0
→ 0.3) by the MBE method or MOV
It is formed by a PE method or the like. On top of that, the dopant is S
i is an impurity concentration of 6 × 10 ¹⁹ cm ^-3 and a thickness of 1200
Å of n ⁺ -GaAs, a thickness of 500Å at an impurity concentration of the dopant as ^{Si 2 × 10 19 cm -3 n} + -In x G
a _1-x As (x: 0 → 0.5), n ⁺ having a dopant concentration of Si and an impurity concentration of 2 × 10 ¹⁹ cm ⁻³ and a thickness of 500 °
An emitter contact layer 6 made of -In _x Ga _{1 -x} As (x = 0.5) is formed by MBE or MOVPE.

This is processed into a mesa shape using an etching technique, and a collector electrode 7c, a base electrode 7b, and an emitter electrode 7e are formed on the collector contact layer, the base layer, and the emitter contact layer by using a vapor deposition technique. . Further, the insulating region 1a is formed by proton implantation, and separates from other devices.

FIG. 6 shows an energy band structure in an operating state in which a bias is applied to the heterojunction bipolar transistor of the second embodiment. In the first collector layer, the electric field is relaxed because the composition is graded so that the forbidden band width increases toward the semi-insulating substrate side, and the energy of carriers entering with high energy is relaxed. You. Carriers having a small energy having passed through the first collector layer enter the second collector layer, are accelerated by a high electric field, cause an overshoot of the drift speed, and travel at high speed. Since the second collector layer is shorter than the carrier travel distance during the inter-valley scattering relaxation time, the carriers enter the next first collector layer before undergoing inter-valley scattering and are relaxed in energy. It again enters the next second collector layer again with low energy. The carrier transit time in the heterojunction bipolar transistor is greatly reduced by the carrier repeating the above-described movement in the collector layer.

In the present structure, the collector layer is formed in the above-mentioned multilayer structure, so that the collector layer can have a sufficient thickness, and it is not necessary to introduce the same second conductivity type layer as the base layer into the collector layer. The breakdown voltage between the base and the collector is not reduced.

In the second embodiment, since the second collector layer has a structure in which the forbidden band width decreases toward the semi-insulating substrate side, the forbidden band width in which the composition is graded in the first collector layer is increased. Therefore, it is more advantageous than in the first embodiment to reduce the energy of electrons to suppress inter-valley scattering. In the second embodiment, the second collector layer has a structure in which the forbidden band width decreases toward the semi-insulating substrate, and the electric field for accelerating electrons in this layer is larger than that in the first embodiment. This is more advantageous for speeding up.

In the above description, an example in which five layers of a multilayer structure are inserted is shown, but of course, any number of layers may be inserted. Although the collector contact layer is made of GaAs in the above description, it may be made of InGaAs or AlGaAs. In the above description, the structure is realized using the material manufactured on the GaAs substrate. However, a similar structure may be realized using the material InGaAs, InAlAs or the like formed on the InP substrate or the material SiGe on the Si substrate. .

[0032]

As described above, according to the present invention, a portion of the collector layer on the base layer side which is depleted in a bias application state is formed by alternately stacking the first collector layer and the second collector layer. The first collector layer was composed of a semiconductor layer whose composition was graded so that the band gap became larger toward the semi-insulating substrate. Further, the second collector layer is formed of a semiconductor layer having a thickness shorter than a moving distance of carriers in a relaxation time of inter-valley scattering. In the first collector layer, the electric field is relaxed because the composition is graded so that the forbidden band width increases toward the semi-insulating substrate side, and the energy of carriers entering with high energy is relaxed. And the scattering between valleys can be suppressed.

Further, since the second collector layer is shorter than the carrier moving distance during the relaxation time of inter-valley scattering, carriers having low energy passing through the first collector layer are not subjected to inter-valley scattering. The vehicle is accelerated by the electric field, and further runs at high speed with overshoot. In this way, carriers having high energy again enter the next first collector layer, and the energy is relaxed, so that inter-valley scattering can be suppressed. The carrier transit time in the heterojunction bipolar transistor is greatly reduced by the carrier repeating the above-described movement in the collector layer.

Further, in this structure, the collector layer has a sufficient thickness, and it is not necessary to introduce the same layer of the second conductivity type as the base layer in the collector layer. Therefore, the breakdown voltage between the base and the collector is not reduced. . Considering an NPN heterojunction bipolar transistor, electrons that have passed through the base layer drift drift (in the case of GaAs, 1-1.5 × 10 ⁷ cm /
s) Then, when traveling through the depletion layer portion of the 3000 ° collector layer, considering the influence of valley scattering, the traveling time is considered to be 1.8 ps or more. If the vehicle runs overshoot while suppressing valley scattering, the average velocity of electrons reaches 5 × 10 ⁷ cm / s or more, and the transit time of this depletion layer portion becomes 0.6 ps or less. It is considered that the running time of the portion is less than 1/3. This results in the effect with respect to a significant improvement in the current gain _cut-off frequency f _T and the maximum oscillation frequency f _max of the heterojunction bipolar transistor.

In this structure, the collector layer is formed in the above-mentioned multilayer structure, so that the collector layer can have a sufficient thickness, and it is not necessary to introduce the same second conductivity type layer as the base layer into the collector layer. The breakdown voltage between the base and the collector is not reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a heterojunction bipolar transistor according to first and second embodiments of the present invention.

FIG. 2 is a diagram showing a structure of a base layer and a collector layer of a heterojunction bipolar transistor according to first and second embodiments of the present invention.

FIG. 3 is a diagram showing a composition structure of a base layer and a collector layer of the hetero-junction bipolar transistor according to the first embodiment of the present invention. 3A is a table illustrating a structure, and FIG. 3B is a diagram illustrating an In composition of an upper collector layer.

FIG. 4 is a diagram showing an energy band structure in an operating state of the heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a composition structure of a base layer and a collector layer of a heterojunction bipolar transistor according to a second embodiment of the present invention. FIG. 3A is a table illustrating a structure, and FIG. 3B is a diagram illustrating an Al composition of an upper collector layer.

FIG. 6 is a diagram showing an energy band structure in an operating state of a heterojunction bipolar transistor according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a drift velocity of carriers in a first collector layer and a second collector layer of an upper collector layer.

FIG. 8 is a cross-sectional view of a conventional heterojunction bipolar transistor.

FIG. 9 is a diagram showing an energy band structure during operation of a conventional heterojunction bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating substrate, 1a ... Insulated area, 2 ... Collector contact layer, 3 ... Collector layer, 3u ... Upper collector layer (3
a ... first collector layer, 3b ... first collector layer), 3d ...
Lower collector layer, 4 ... Base layer, 5 ... Emitter layer, 6 ...
Emitter contact layer, 7b base electrode, 7c collector electrode, 7e emitter electrode.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 29/205 H01L 29/73

Claims (4)

(57) [Claims] A first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer having a forbidden band width larger than the base layer are sequentially laminated on a semi-insulating substrate;
A portion of the collector layer on the base layer side which is depleted in a bias applied state is composed of a first collector layer and a second collector layer alternately stacked, and the first collector layer has a semi-insulating property. consists semiconductor layer is inclined composition as the forbidden band width toward the substrate side is increased, the second Kore
Kuta layer transports carriers during relaxation time of inter-valley scattering
A heterojunction bipolar transistor having a thickness shorter than a moving distance and having the same composition at a boundary with a first collector layer. 2. The semiconductor device according to claim 1, wherein the second collector layer has a uniform composition.
2. The heterojunction bipolar transistor according to claim 1, comprising a body layer . 3. A collector layer of a first conductivity type, a base layer of a second conductivity type, and an emitter layer of a first conductivity type having a forbidden band width larger than the base layer are sequentially stacked on a semi-insulating substrate,
A portion of the collector layer on the base layer side which is depleted in a bias applied state is composed of a first collector layer and a second collector layer alternately stacked, and the first collector layer has a semi-insulating property. The second collector layer is composed of a semiconductor layer whose composition is graded so that the forbidden band width increases toward the substrate side, and the second collector layer transfers carriers during the relaxation time of inter-valley scattering.
A hetero-junction bipolar transistor comprising a semiconductor layer having a thickness shorter than a moving distance and having a composition inclined so that a forbidden band width decreases toward a semi-insulating substrate. 4. The hetero-junction bipolar transistor according to claim 3, wherein the second collector layer has the same composition at the boundary with the first collector layer.