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JPH0620070B2 - Heterojunction bipolar transistor - Google Patents
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JPH0620070B2 - Heterojunction bipolar transistor - Google Patents

Heterojunction bipolar transistor

Info

Publication number
JPH0620070B2
JPH0620070B2 JP62158101A JP15810187A JPH0620070B2 JP H0620070 B2 JPH0620070 B2 JP H0620070B2 JP 62158101 A JP62158101 A JP 62158101A JP 15810187 A JP15810187 A JP 15810187A JP H0620070 B2 JPH0620070 B2 JP H0620070B2
Authority
JP
Japan
Prior art keywords
layer
collector
bipolar transistor
base layer
heterojunction bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62158101A
Other languages
Japanese (ja)
Other versions
JPH012359A (en
JPS642359A (en
Inventor
和彦 本城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62158101A priority Critical patent/JPH0620070B2/en
Priority to DE8787119044T priority patent/DE3780284T2/en
Priority to EP87119044A priority patent/EP0273363B1/en
Priority to US07/136,589 priority patent/US4929997A/en
Publication of JPH012359A publication Critical patent/JPH012359A/en
Publication of JPS642359A publication Critical patent/JPS642359A/en
Publication of JPH0620070B2 publication Critical patent/JPH0620070B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Bipolar Transistors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はヘテロ接合バイポーラトランジスタに関する。The present invention relates to a heterojunction bipolar transistor.

〔従来技術〕[Prior art]

ヘテロ接合バイポーラトランジスタにおいてはエミッタ
層の禁制帯幅がベース層より大きく設定できるので、ベ
ース抵抗を低減するためにベース層を高濃度にドーピン
グしてもエミッタ注入効率が低下しないという優れた特
徴がある。このため、近年の、分子線エピタキシャル
(MBE)技術や有機金属CVD(MOCVD)技術の
進展に伴い化合物半導体を用いたヘテロ接合バイポーラ
トランジスタの研究開発が盛んに行なわれるようになっ
てきている。
In the heterojunction bipolar transistor, the forbidden band width of the emitter layer can be set larger than that of the base layer. Therefore, even if the base layer is heavily doped to reduce the base resistance, the emitter injection efficiency does not decrease. . For this reason, with the recent progress of molecular beam epitaxial (MBE) technology and metal organic chemical vapor deposition (MOCVD) technology, research and development of heterojunction bipolar transistors using compound semiconductors have been actively conducted.

このような優れた特性を有する化合物半導体のヘテロ接
合バイポーラトランジスタをより高周波化・高速化する
ためには、例えばnpnトランジスタの場合では、ベー
ス層での電子走行時間を短縮することだけでなくコレク
タ層の空乏層の部分での電子走行時間を短縮することも
重要である。
In order to further increase the frequency and speed of a compound semiconductor heterojunction bipolar transistor having such excellent characteristics, for example, in the case of an npn transistor, not only the electron transit time in the base layer is shortened but also the collector layer is shortened. It is also important to shorten the electron transit time in the depletion layer part of the.

第3図は従来例のヘテロ接合バイポーラトランジスタの
一例のバンド構成図である。
FIG. 3 is a band configuration diagram of an example of a conventional heterojunction bipolar transistor.

この従来例は、n型のコレクタ層3′上にp型のベース
層5′とベース層5′よりも電子親和力が小さくかつ禁
制帯幅の広いn型のエミッタ層6′とを順次設けた構造
をしており、エミッタ層6′から注入されベース層5′
を通過した後にコレクタ層3′の空乏層に至った電子
9′は、矢印10′に示すように、空乏層内の高電界に
より加速されドリフト走行する。
In this conventional example, a p-type base layer 5'and an n-type emitter layer 6 'having a smaller electron affinity and a wider band gap than the base layer 5'are sequentially provided on an n-type collector layer 3'. It has a structure and is injected from the emitter layer 6'and the base layer 5 '.
Electrons 9 ', which have reached the depletion layer of the collector layer 3'after passing through, are accelerated by the high electric field in the depletion layer and drift as shown by an arrow 10'.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来のヘテロ接合バイポーラトランジスタで
は、コレクタ層のベース層に接する部分の空乏層内の電
界強度が10〜50kV/cmとなるので伝導帯の電子は谷
間散乱を受け、平均ドリフト速度が低下して高速・高周
波性能を損うという欠点がある。
In the above-mentioned conventional heterojunction bipolar transistor, the electric field strength in the depletion layer in the portion in contact with the base layer of the collector layer is 10 to 50 kV / cm, so electrons in the conduction band are subjected to valley scattering and the average drift velocity is reduced. However, it has the drawback of impairing high-speed and high-frequency performance.

このようなドリフトによる電子速度の最大値υsatは、
例えばGaAsの場合でも高々1〜1.5×10cm/secで
あり、空乏層の厚みを1000Åとすると、ドリフト電子の
その空乏層中の走行時間はベース層の走行時間と同程度
の0.7〜1psecとなり、無視できない値である。
The maximum electron velocity υsat due to such drift is
For example, even in the case of GaAs, it is at most 1 to 1.5 × 10 7 cm / sec. If the thickness of the depletion layer is 1000 Å, the transit time of drift electrons in the depletion layer is 0.7 to 1 psec, which is the same as the transit time of the base layer. Is a value that cannot be ignored.

本発明の目的は、電子をコレクタ層の空乏層内でいわゆ
るパリスティック飛行させることにより空乏層内の走行
時間を大幅に低減した超高速動作が可能な高速・高周波
性能の優れたヘテロ接合バイポーラトランジスタを提供
することにある。
An object of the present invention is to provide a heterojunction bipolar transistor excellent in high-speed and high-frequency performance capable of ultra-high-speed operation in which the transit time in the depletion layer is significantly reduced by causing electrons to fly so-called paristically in the depletion layer of the collector layer. To provide.

〔問題を解決するための手段〕[Means for solving problems]

本発明のヘテロ接合バイポーラトランジスタは、一導電
型のコレクタ層上に形成した反対導電型のベース層と該
ベース層上に形成した禁制帯幅が前記ベース層より広い
エミッタ層とを有するヘテロ接合バイポーラトランジス
タにおいて、前記コレクタ層及び前記ベース層の界面に
所定の厚さで一導電型の不純物層を少くとも一層設け、
電子親和力が前記コレクタ層,前記不純物層及び前記ベ
ース層と順次小さくなってる。
The heterojunction bipolar transistor of the present invention comprises a heterojunction bipolar transistor having a base layer of opposite conductivity type formed on a collector layer of one conductivity type and an emitter layer formed on the base layer and having a band gap wider than the base layer. In the transistor, at least one impurity layer of one conductivity type having a predetermined thickness is provided at the interface between the collector layer and the base layer,
The electron affinity decreases in the order of the collector layer, the impurity layer, and the base layer.

〔作用〕[Action]

このような本発明のヘテロ接合バイポーラトランジスタ
によると、ベース層を通過した電子は、先づ、ベース・
コレクタ界面に存在する伝導帯のエネルギーの不連続分
だけを運動エネルギーとして受けとりコレクタ側に注入
される。この注入された電子は、次に、平均自由行程だ
けバリスティック飛行して運動エネルギーの大部分を失
なうが、そのとき次の伝導帯のエネルギーの不連続部分
に達し、再び運動エネルギーをもらってバリスティック
飛行による伝導をする。以上のようにバリスティック飛
行をくり返しながらコレクタ層の空乏層内を電子が通過
するため、谷間散乱による速度の低下を防止できて空乏
層内の走行時間を大幅に低減することができる。
According to such a heterojunction bipolar transistor of the present invention, the electrons that have passed through the base layer are
Only the discontinuity of the conduction band energy existing at the collector interface is received as kinetic energy and injected into the collector side. The injected electrons then fly ballistically over the mean free path to lose most of the kinetic energy, at which time they reach the energy discontinuity in the next conduction band and receive kinetic energy again. Conducts by ballistic flight. As described above, since electrons pass through the depletion layer of the collector layer while repeating ballistic flight, it is possible to prevent a decrease in velocity due to valley scattering and to significantly reduce the transit time in the depletion layer.

〔実施例〕〔Example〕

次に、本発明の実施例を図面を参照して説明する。 Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

この実施例はあ、半絶縁性基板1表面にプロトンのイオ
ン注入によって形成された絶縁領域1aで仕切られ、ド
ーパントをSiとし不純物濃度が5×1018atom/cm3
厚さ5000Åのn−GaAs層からなる高濃度層2をMB
E法又はMOCVD法等により形成して設け、高濃度層
2上にドーパントをSiとし不純物濃度が5×1016at
om/cm3で厚さ3000Åのn−GaAs層からなるコレクタ
層3,ドーパンドをSiとし不純物濃度が5×1016at
om/cm3で厚さが500Åのn−Al0.075Ga0.925As層か
らなるコレクタ層4,ドーパントをBeとし不純物濃度
が2×1019atom/cm3で厚さが1500Åのp−Al0.15
Ga0.85As層からなるベース層5,ドーパントをSiと
し不純物濃度が3×1017atom/cm3で厚さが500Åのn
−AlxGa1-xAs層(x:0.15→0.3)からなるエミッタ
層6a,ドーパントをSiとし不純物濃度が3×1017
atom/cm3で厚さが200Åのn−Al0.3GAl0.7
s層からなるエミッタ層6b及びドーパントをSiとし
不純物濃度が5×1018atom/cm3で厚さが1000Åのn
−GaAs層からなる高濃度層7をMBE法又はMOCV
D法等により所定のパターンに順次形成して設け、更
に、高濃度層2及び7並びにベース層5の上にそれぞれ
コレクタ及びエミッタ並びにベース電極8c及び8e並
びに8bを設けた構造をしている。
In this embodiment, a semi-insulating substrate 1 is partitioned by an insulating region 1a formed by ion implantation of protons, Si is used as a dopant, an impurity concentration is 5 × 10 18 atom / cm 3 , and a thickness of 5000 Å n +. -MB for the high concentration layer 2 composed of GaAs layer
It is formed by the E method or the MOCVD method, and the dopant concentration is Si on the high concentration layer 2 and the impurity concentration is 5 × 10 16 at
The collector layer 3 is an n -- GaAs layer having a thickness of 3000 Å at om / cm 3 , and the dopant is Si and the impurity concentration is 5 × 10 16 at
Collector layer consisting of n −Al 0.075 Ga 0.925 As layer having a thickness of om / cm 3 and 500Å 4, a dopant of Be, an impurity concentration of 2 × 10 19 atom / cm 3 and a thickness of 1500 Å p + −Al 0.15
Base layer 5 consisting of Ga 0.85 As layer 5, Si as dopant, n with impurity concentration of 3 × 10 17 atom / cm 3 and thickness of 500Å
An emitter layer 6a made of an Al x Ga 1-x As layer (x: 0.15 → 0.3), the dopant concentration is Si, and the impurity concentration is 3 × 10 17
n-Al 0.3 GAl 0.7 A with atom / cm 3 and thickness of 200Å
n + with an impurity concentration of 5 × 10 18 atom / cm 3 and a thickness of 1000Å with Si as the emitter layer 6b composed of the s layer and a dopant
-High concentration layer 7 made of GaAs layer is processed by MBE method or MOCV
It has a structure in which it is sequentially formed in a predetermined pattern by the D method or the like, and further, collectors and emitters and base electrodes 8c, 8e and 8b are provided on the high concentration layers 2 and 7 and the base layer 5, respectively.

第2図は本発明の一実施例のバンド構成図である。FIG. 2 is a band configuration diagram of an embodiment of the present invention.

この実施例では、エミッタ層6b及び6aから注入され
ベース層5を通過した電子9は、先ず、ベース層5とコ
レクタ層4との間の電子親和力の差に基づくエネルギー
の不連続δEc(約0.05eV)を初期運動エネルギーとして
空乏層中を電子の平均自由行程(約500Å)程度いわ
ゆるハリスティック飛行して運動エネルギーを失い、次
に、コレクタ層4とコレクタ層3との間の電子親和力の
差に基づくエネルギーの不連続δEc′(約0.05eV)を初
期運動エネルギーとして空乏層中を再びバリスティック
飛行して平均自由行程(約500Å)走行したところで
運動エネルギーを失い、コレクタ層4及び3の空乏層を
通りぬける。このように、電子が、コレクタ層の空乏層
中をバリスティック飛行して伝導することにより、谷間
散乱による伝導速度の低下を防止して、空乏層中の電子
の走行時間を短縮できる。
In this embodiment, the electrons 9 injected from the emitter layers 6b and 6a and passing through the base layer 5 firstly have energy discontinuity δEc (about 0.05) due to the difference in electron affinity between the base layer 5 and the collector layer 4. eV) is the initial kinetic energy, and the mean free path (about 500 Å) of electrons in the depletion layer causes so-called halistic flight to lose kinetic energy, and then the difference in electron affinity between collector layer 4 and collector layer 3 Based on the energy discontinuity δEc ′ (about 0.05 eV) as the initial kinetic energy, the ballistic flight in the depletion layer is performed again, and the kinetic energy is lost when traveling on the mean free path (about 500 Å) and the collector layers 4 and 3 are depleted. Go through the layers. As described above, the electrons are ballistic-flyed and conducted in the depletion layer of the collector layer, so that the conduction velocity is prevented from lowering due to the valley scattering, and the transit time of the electrons in the depletion layer can be shortened.

なお、本発明の実施例においては、コレクタ3とベース
層5との界面にコレクタ層4を押入してコレクタ層の空
乏層部分を2つの区間に分割しているがこの区間数は2
つに限るものではなくもっと増やしてもよい。
In the embodiment of the present invention, the depletion layer portion of the collector layer is divided into two sections by pushing the collector layer 4 into the interface between the collector 3 and the base layer 5, but the number of sections is two.
The number is not limited to one and may be increased.

又、本発明の実施例においては、半導体材料は互いに格
子整合しているAlGaAsとGaAsとの組合せを用いているが
これに限らず電子親和力に差がある材料なら格子不整合
系のものでもよい。
In the embodiment of the present invention, the semiconductor material is a combination of AlGaAs and GaAs which are lattice-matched with each other, but the material is not limited to this, and a lattice-mismatched material may be used as long as the material has a difference in electron affinity. .

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明では、コレクタ層とベース層
との界面にコレクタ層と同一導電型の不純物層からなる
他のコレクタ層を少くとも一層設け、電子親和力がコレ
クタ層、不純物層及びベース層の順に小さくなるように
することによつて、エミッタ層から注入されベース層を
通過した後の電子が、コレクタ層と空乏層の部分をいわ
ゆるバリスティック飛行によって走行するので、谷間散
乱による移動速度の低下を防止して、空乏層部分の走行
時間の短い高速・高周波特性の優れたヘテロ接合バイポ
ーラトランジスタを提供できるという効果がある。
As described above, in the present invention, at least one other collector layer made of an impurity layer having the same conductivity type as that of the collector layer is provided at the interface between the collector layer and the base layer, and the electron affinity is set to the collector layer, the impurity layer, and the base layer. Since the electrons injected from the emitter layer and passing through the base layer travel in the collector layer and the depletion layer by so-called ballistic flight, the movement speed of the valley scattering is reduced. There is an effect that it is possible to provide a heterojunction bipolar transistor which is excellent in high-speed and high-frequency characteristics in which the depletion layer portion has a short transit time by preventing the deterioration.

このようなバリスティック飛行を利用したヘテロ接合バ
イポーラトランジスタでは、コレクタ層の空乏層の部分
での電子の平均速度は5×107cm/sec以上に達し、空
乏層部分の走行時間は0.3psec以下となるので、従来に
比べて1/3以下の走行時間で済む。
In the heterojunction bipolar transistor using such ballistic flight, the average velocity of electrons in the depletion layer portion of the collector layer reaches 5 × 10 7 cm / sec or more, and the transit time of the depletion layer portion is 0.3 psec or less. Therefore, the traveling time is 1/3 or less as compared with the conventional one.

【図面の簡単な説明】[Brief description of drawings]

第1図及び第2図はそれぞれ本発明の一実施例の断面図
及びバンド構造図、第3図は従来のヘテロ接合バイポー
ラトランジスタの一例のバンド構造図である。 1……半絶縁性基板、1a……絶縁領域、2……高濃度
層、3,3′,4……コレクタ層、5,5′……ベース
層、6a,6b,6′……エミッタ層、7……高濃度
層、8b……ベース電極、8c……コレクタ電極、8e
……エミッタ電極、11,11′,12,12′,13,13′……
フェルミレベル。
1 and 2 are a sectional view and a band structure diagram of an embodiment of the present invention, and FIG. 3 is a band structure diagram of an example of a conventional heterojunction bipolar transistor. 1 ... Semi-insulating substrate, 1a ... Insulating region, 2 ... High concentration layer, 3, 3 ', 4 ... Collector layer, 5, 5' ... Base layer, 6a, 6b, 6 '... Emitter Layer, 7 ... High-concentration layer, 8b ... Base electrode, 8c ... Collector electrode, 8e
...... Emitter electrode, 11, 11 ', 12, 12', 13, 13 '......
Fermi level.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一導電型のコレクタ層上に形成した反対導
電型のベース層と該ベース層上に形成した禁制帯幅が前
記ベース層より広いエミッタ層とを有するヘテロ接合バ
イポーラトランジスタにおいて、前記コレクタ層及び前
記ベース層の界面に所定の厚さで一導電型の不純物層を
少くとも一層設け、電子親和力が前記コレクタ層,前記
不純物層及び前記ベース層と順次小さくなることを特徴
とするヘテロ接合バイポーラトランジスタ。
1. A heterojunction bipolar transistor having a base layer of opposite conductivity type formed on a collector layer of one conductivity type and an emitter layer formed on the base layer and having a forbidden band width wider than that of the base layer. At least one layer of one conductivity type impurity layer having a predetermined thickness is provided at the interface between the collector layer and the base layer, and the electron affinity is sequentially reduced to the collector layer, the impurity layer, and the base layer. Junction bipolar transistor.
JP62158101A 1986-12-22 1987-06-24 Heterojunction bipolar transistor Expired - Fee Related JPH0620070B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP62158101A JPH0620070B2 (en) 1987-06-24 1987-06-24 Heterojunction bipolar transistor
DE8787119044T DE3780284T2 (en) 1986-12-22 1987-12-22 BIPOLAR HETEROUISITION TRANSISTOR WITH BALLISTIC OPERATION.
EP87119044A EP0273363B1 (en) 1986-12-22 1987-12-22 Heterojunction bipolar transistor with ballistic operation
US07/136,589 US4929997A (en) 1986-12-22 1987-12-22 Heterojunction bipolar transistor with ballistic operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62158101A JPH0620070B2 (en) 1987-06-24 1987-06-24 Heterojunction bipolar transistor

Publications (3)

Publication Number Publication Date
JPH012359A JPH012359A (en) 1989-01-06
JPS642359A JPS642359A (en) 1989-01-06
JPH0620070B2 true JPH0620070B2 (en) 1994-03-16

Family

ID=15664324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62158101A Expired - Fee Related JPH0620070B2 (en) 1986-12-22 1987-06-24 Heterojunction bipolar transistor

Country Status (1)

Country Link
JP (1) JPH0620070B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3200550B2 (en) * 1995-10-13 2001-08-20 矢崎総業株式会社 Connection terminal for ignition cable

Also Published As

Publication number Publication date
JPS642359A (en) 1989-01-06

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