JP4880903B2 - Optoelectronic integrated circuit and manufacturing method thereof - Google Patents

Description

  The present invention relates to a technology for mounting an optical integrated circuit and a semiconductor integrated circuit on the same substrate, and in particular, includes an optical element such as a photodiode or an optical modulator and a heterojunction bipolar transistor as a semiconductor element on the same substrate. The present invention relates to an optoelectronic integrated circuit and a manufacturing method thereof.

  As an applied technology of a semiconductor device, there is a so-called opto-electronic integrated circuit (OEIC) in which a semiconductor element (electronic element) and an optical element are provided on the same substrate. As a specific example, there is an OEIC in which a heterojunction bipolar transistor (HBT) which is a kind of electronic element and an optical device are mixedly mounted on a semi-insulating substrate made of InP. In general, InP-based materials have excellent electronic properties such as high electron transport mobility and various band designs. Further, the HBT has characteristics unique to bipolar transistors such as high current drive and compact element size. Therefore, an InP-based HBT, which is an HBT provided on an InP substrate, combines the characteristics of the InP-based material and the bipolar transistor described above, and is an electronic device that is excellent in high speed and high integration. Further, InP-based semi-insulating substrates are generally used when manufacturing long-wavelength optical elements. Therefore, the InP-based HBT has an advantage that it can be integrated with an optical element for a long wavelength on an InP-based crystal substrate manufactured by an epitaxial growth method.

  In recent years, research on OEIC in which the above-described InP-based HBT and an optical device are integrated on an InP-based substrate has been actively conducted. For example, an OEIC in which an InP-based HBT and a pin photodiode are integrated on an InP-based substrate has been reported (for example, see Non-Patent Document 1). FIG. 25 shows a cross-sectional view of the OEIC 101 in which the InP-based HBT 103 and the pin photodiode 104 are integrated on the semi-insulating InP substrate 102. In this OEIC 101, the left side of the alternate long and short dash line in FIG. 25 is a semiconductor element formation region (HBT formation region), and the right side of the alternate long and short dash line is an optical element formation region (pin photodiode formation region). The OEIC 101 has the following configuration and characteristics.

  As shown in FIG. 25, in the OEIC 101, the InP-based HBT 103 and the pin photodiode 104 share the semi-insulating InP substrate 102. The InP-based HBT 103 is provided on the semi-insulating InP substrate 102 via a collector contact layer (sub-collector layer) 105 made of n-type InGaAs. The InP-based HBT 103 includes a collector layer 106 made of undoped InGaAs and n-type InP, a base layer 107 made of p-type InGaAs, and an emitter layer 108 made of n-type InP. The collector contact layer 105 is provided with a collector electrode 109, the base layer 107 is provided with a base electrode 110, and the emitter layer 108 is provided with an emitter electrode 111.

  Also, as shown in FIG. 25, the pin photodiode 104 is fabricated in substantially the same configuration as the InP-based HBT 103. That is, the pin photodiode 104 is provided on the semi-insulating InP substrate 102 via the collector contact layer 105. The collector contact layer 105 becomes a cathode contact layer that is one electrode of the pin photodiode 104. Further, the active layer of the pin photodiode 104 is formed using the collector layer 106. At the same time, in the pin photodiode 104, an anode contact layer which is the other electrode is formed using the base layer 107. The cathode contact layer 105 is provided with a cathode electrode 112, and the anode contact layer 107 is provided with an anode electrode 113.

  According to such a structure, the pin photodiode 104 can be manufactured using the base layer 107, the collector layer 106, and the collector contact layer (high-concentration n-type InP layer) 105 included in the InP-based HBT 103. That is, it is possible to manufacture a pin photodiode 104 having a light absorption region in the 1.55 μm band using the undoped InGaAs layer in the active layer 106 as a light absorption layer. As described above, the OEIC 101 can be manufactured on the same epitaxial crystal substrate 102 by making the manufacturing process of the InP-based HBT 103 and the pin photodiode 104 common. Thereby, the manufacturing process of the OEIC 101 can be greatly simplified.

Further, as one of OEIC manufacturing methods, there is a manufacturing method called a so-called selective regrowth method. In this selective regrowth method, an insulating film such as a silicon oxide film or a silicon nitride film is formed in the optical element formation region as a mask, a portion not covered by this mask is removed, the substrate is exposed, and this exposed In this method, an epitaxial layer of an electronic circuit is selectively regrown on a substrate. The selective regrowth method has an advantage that an epitaxial layer of an electronic circuit can be designed independently of an optical element and selectively regrown (for example, see Non-Patent Document 2).
E. Sano et al., IEEE Electron Devices, 43, 1826 (1996) M. Ida et al., Journal of Crystal Growth, 158,437 (1996)

  However, in the above-described OEIC 101, the diode 104 is fabricated using the base layer 107, the collector layer 106, and the collector contact layer 105 of the HBT 103, and therefore, the light receiving sensitivity of the diode 104 and the operating speed of the HBT 103 are between. A trade-off occurs. Specifically, when the collector layer 106 of the HBT 103 is thinned to increase the speed of the HBT 103, the InGaAs light absorption layer of the diode 104 becomes thin, and the light receiving sensitivity of the diode 104 decreases. In addition, if the InGaAs light absorption layer of the diode 104 is made thick to increase the sensitivity of the diode 104, the collector layer 106 of the HBT 103 becomes thick and the operation speed of the HBT 103 becomes slow.

  In the selective regrowth method described above, the thickness of the InGaAs film in the vicinity of the mask increases by about 1.3 to 1.6 times that of a general crystal growth method, and the composition becomes In-rich. It has been reported. Therefore, in order to obtain a composition in which the InGaAs layer is lattice-matched with the InP layer, the epitaxial layer (electronic element forming region) of the electronic circuit must be separated from the mask (optical element forming region) by at least 150 μm. This means that in the selective regrowth method, it is impossible to set the physical closest distance between the electronic circuit and the optical element within 150 μm. As a result, in the OEIC manufactured using the selective regrowth method, a wiring delay occurs between the electronic circuit and the optical element, and it is difficult to increase the operation speed.

  The present invention has been made to solve the above-described problems, and the object of the present invention is to provide a bipolar transistor and an optical element that are properly provided with the possibility that the performance of the bipolar transistor and the optical element cancel each other out. It is an object of the present invention to provide an optoelectronic integrated circuit having a high operating speed and high light receiving sensitivity. Another object of the present invention is to provide a method of manufacturing an optoelectronic integrated circuit capable of efficiently and easily manufacturing such an optoelectronic integrated circuit.

To solve the previous SL problem, opto-electronic integrated circuit according to an embodiment of the present invention is semi-insulating and the substrate, the semi-insulating independently and on a substrate of at least two is provided adjacent the first and one of the first electrode layer, and an optical element consisting of active layer and a second electrode layer provided to be stacked on one of the first electrode layer of the electrode layer, wherein each first electrode A conductive layer provided on the other first electrode layer of the layers, a collector layer provided on the conductive layer, a base layer provided on the collector layer, and provided on the base layer In addition to the emitter layer, the conductive layer, the collector layer, the base layer, and the emitter layer are separately stacked from the active layer and the second electrode layer, respectively, and adjacent to the optical element. Bipolar transistor provided It is characterized in that it comprises a Njisuta, the.

  In this optoelectronic integrated circuit, an optical element and a bipolar transistor are not in electrical contact, and the first electrode layer of the optical element and the first electrode layer provided with the bipolar transistor are formed using the same material. ing. That is, the optical element and the bipolar transistor are provided close to each other. At the same time, the first electrode layer, the active layer, and the second electrode layer of the optical element and the conductive layer, collector layer, base layer, and emitter layer of the bipolar transistor are formed independently of each other. ing. According to such a structure, there is almost no risk of a trade-off between the light receiving sensitivity of the optical element and the operation speed of the bipolar transistor. In addition, there is almost no risk of wiring delay between the optical element and the bipolar transistor.

  In order to solve the above problems, a method for manufacturing an optoelectronic integrated circuit according to another aspect of the present invention includes sequentially stacking a first electrode layer, an active layer, and a second electrode layer on a semi-insulating substrate. And providing a first mask so as to selectively cover part of the surface of the second electrode layer and moving from the first mask side toward the first electrode layer side The first mask of the second electrode layer and the active layer from the first mask side toward the first electrode layer side while leaving a large amount of the second electrode layer and the active layer The second electrode layer and the portion of the active layer not covered by the first mask are sequentially removed from the portion covered by A step of selectively exposing a portion, and after removing the first mask, Covering the exposed surface of the first electrode layer, the second electrode layer, and the active layer, a conductive layer, a collector layer, a base layer, and an emitter layer are entirely formed on the semi-insulating substrate. A step of sequentially stacking the conductive layer, the collector layer, and the base on the first electrode layer without passing through the second electrode layer and the active layer in the region on the semi-insulating substrate; In the first region where the emitter layer and the emitter layer are provided, a part of the surface of the emitter layer is selectively covered to provide a second mask, and the emitter layer is covered by the second mask. Unexposed portions are completely removed from the semi-insulating substrate to expose the surface of the base layer, and the second mask is removed, and then left on the base layer in the first region. The emitter layer on the entire surface A third mask is selectively provided on the surface of the base layer exposed over the substrate, and a portion of the base layer, the collector layer, and the conductive layer not covered by the third mask is formed on the surface of the base layer. A step of sequentially removing the entire surface from the semi-insulating substrate to selectively expose at least part of the surface of the first electrode layer in the first region, and after removing the third mask Providing a fourth mask so as to selectively cover a part of the surface of the second electrode layer, and forming a portion of the second electrode layer and the active layer not covered by the fourth mask as described above. A part of the surface of the first electrode layer in the second region excluding the first region is selected from the region on the semi-insulating substrate by sequentially removing the entire surface from the semi-insulating substrate. After the step of exposing and removing the fourth mask , Selectively on the surface of the first electrode layer exposed to cover the entire surface of the conductive layer, the collector layer, the base layer, and the emitter layer remaining in the first region. 5 is provided, and a sixth mask independent of the fifth mask is exposed to cover the active layer and the second electrode layer left in the second region. After selectively providing on the surface of the first electrode layer, a portion of the first electrode layer that is not covered by the fifth mask and the sixth mask is entirely exposed from above the semi-insulating substrate. The first electrode layer, the conductive layer, the collector layer, the base layer, and the emitter layer left in the first region and left in the second region. The first electrode layer, the active layer, and the second electrode layer are electrically connected. It is characterized in that comprising the steps of disconnecting a manner.

  In this method of manufacturing an optoelectronic integrated circuit, the first electrode layer, the active layer, and the second electrode layer of the optical element, the conductive layer, the collector layer, the base layer, and the emitter layer of the bipolar transistor Can be formed independently of each other. In addition, since the conductive layer, collector layer, base layer, and emitter layer are formed over the entire surface of the semi-insulating substrate and then formed into a predetermined shape, the composition of the film in the vicinity of the mask that is likely to occur in the selective regrowth method is achieved. There is almost no risk of defects. Furthermore, by providing a bipolar transistor on the first electrode layer that is electrically disconnected independently from the first electrode layer of the optical element, the optical element and the bipolar transistor are brought into close proximity without being in electrical contact. Can be provided. According to such a method, there is almost no possibility that a trade-off occurs between the light receiving sensitivity of the optical element and the operation speed of the bipolar transistor. In addition, there is almost no possibility of wiring delay between the optical element and the bipolar transistor. Furthermore, the first electrode layer of the optical element and the first electrode layer provided with the bipolar transistor can be formed in the same process.

  In the optoelectronic integrated circuit according to the present invention, there is almost no risk of a trade-off between the light receiving sensitivity of the optical element and the operating speed of the bipolar transistor. In addition, there is almost no risk of wiring delay between the optical element and the bipolar transistor. That is, in the optoelectronic integrated circuit according to one embodiment of the present invention, the bipolar transistor and the optical element are appropriately provided with the possibility of canceling the performances of each other, the operating speed is high, and the light receiving sensitivity is high. .

  In addition, according to the method of manufacturing an optoelectronic integrated circuit according to the present invention, there is almost no possibility of causing a trade-off between the light receiving sensitivity of the optical element and the operation speed of the bipolar transistor. In addition, there is almost no possibility of wiring delay between the optical element and the bipolar transistor. Furthermore, the first electrode layer of the optical element and the first electrode layer provided with the bipolar transistor can be formed in the same process. Therefore, according to the method of manufacturing an optoelectronic integrated circuit of the present invention, the bipolar transistor and the optical element are appropriately provided with the possibility of canceling the performances of each other, and the operation speed is high, and the light receiving sensitivity is high. A high optoelectronic integrated circuit can be manufactured efficiently and easily.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment according to the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing an optoelectronic integrated circuit according to this embodiment. 2 to 5 are process cross-sectional views illustrating a method for manufacturing an optoelectronic integrated circuit according to the present embodiment. FIG. 6 is a graph showing characteristics of the optoelectronic integrated circuit manufacturing method according to this embodiment and characteristics of the optoelectronic integrated circuit manufacturing method according to the background art.

  The present embodiment relates to a technique for manufacturing an optoelectronic integrated circuit by providing a layer constituting a semiconductor element by being completely regrown on a substrate. In particular, the present invention relates to a technique for forming a heterojunction bipolar transistor and an optical element on the same epitaxial crystal substrate by forming each of these layers in an epitaxial layer structure while individually optimizing each layer. With this technology, an optoelectronic integrated circuit (optical transmission / reception circuit) can be realized at higher speed, higher sensitivity, and higher integration. This will be described in detail below.

  First, an optoelectronic integrated circuit 1 according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, in an opto-electronic integrated circuit (OEIC) 1, the right side of the alternate long and short dash line in FIG. 1 is an optical element formation region, and the left side of the alternate long and short dash line is a semiconductor element formation region. In the present embodiment, a photodiode 2 is provided as an optical element (optical integrated circuit). In addition, a hetero-junction bipolar transistor (HBT) 3 is provided as a semiconductor element (semiconductor integrated circuit, electronic element). The photodiode 2 and the HBT 3 are mounted on the same semi-insulating substrate 4 made of InP. That is, in the OEIC 1, the photodiode 2 and the InP-based HBT 3 share the semi-insulating InP substrate 4.

  The photodiode 2 includes a cathode contact layer 5 as a first electrode layer made of n-type InP, an active layer 6, and an anode contact layer 7 as a second electrode layer made of p-type InGaAsP. Further, in the present embodiment, the active layer 6 is composed of a traveling layer 6a made of inclined InGaAsP and n-type InP on the lower side and a light absorption layer 6b made of p-type InGaAs on the upper side. The cathode contact layer 5 is provided with a cathode electrode 8, and the anode contact layer 7 is provided with an anode electrode 9.

  The InP-based HBT 3 is mounted on the semi-insulating InP substrate 4 through the conductive layer 10 provided independently of the cathode contact layer 5 using the same material (n-type InP) as the cathode contact layer 5. . The conductive layer 10 becomes a so-called collector contact layer. The InP-based HBT 3 includes a collector layer 11 made of inclined InGaAsP and n-type InP, a base layer 12 made of p-type InGaAs, and an emitter layer 13 made of n-type InP. Thus, the base layer 12 and the emitter layer 13 are formed of different materials and are heterojunctioned. At the same time, the base layer 12 is formed of a material different from that of the anode contact layer 7. The collector contact layer 10 is provided with a collector electrode 14, the base layer 12 is provided with a base electrode 15, and the emitter layer 13 is provided with an emitter electrode 16.

  Next, a method for manufacturing the OEIC 1 will be described with reference to FIGS. 2 to 5 and FIG.

  First, as shown in FIG. 2, the cathode contact layer 5, the active layer 6, and the anode contact layer 7 of the photodiode 2 are sequentially stacked on the semi-insulating InP substrate 4. Each of these layers 5, 6, and 7 is provided by at least one of a metal organic chemical vapor deposition (MOCVD) method and a molecular beam epitaxy (MBE) method. That is, the cathode contact layer 5, the active layer 6, and the anode contact layer 7 of the photodiode 2 are each formed by epitaxial growth on the semi-insulating InP substrate 4.

  Next, as shown in FIG. 3, a mask 17 is provided to cover a part of the surface of the anode contact layer 7 in the optical element formation region. Specifically, the mask 17 is a photoresist film patterned into a predetermined shape by a photolithography technique. The photoresist film 17 is provided on the anode contact layer 7 by, for example, a coating method.

  Next, as shown in FIG. 4, dry etching or wet etching is performed with the photoresist film 17 applied on the anode contact layer 7. As a result, portions of the anode contact layer 7 and the active layer 6 that are not covered with the photoresist film 17 are removed, and a part of the surface of the cathode contact layer 5 is selectively exposed. Thereafter, the photoresist film 17 is removed from the anode contact layer 7.

  Next, as shown in FIG. 5, the InP-based HBT 3 collector layer 11, base layer 12, and emitter layer 13 are semi-insulated so as to cover the exposed surface of the cathode contact layer 5, the active layer 6, and the anode contact layer 7. And sequentially stacked on the entire surface of the InP substrate 4. That is, in this embodiment, the collector layer 11, the base layer 12, and the emitter layer 13 of the InP-based HBT 3 are provided by the entire surface regrowth method. Each of these layers 11, 12, and 13 is also provided by at least one of the MOCVD method and the MBE method, similarly to the cathode contact layer 5, the active layer 6, and the anode contact layer 7 of the photodiode 2. That is, the collector layer 11, the base layer 12, and the emitter layer 13 of the InP-based HBT 3 are each formed by being epitaxially grown on the entire surface of the semi-insulating InP substrate 4.

  Thereafter, the cathode contact layer 5, the active layer 6, and the anode contact layer 7 of the photodiode 2, and the collector layer 11, base layer 12, and emitter layer 13 of the InP-based HBT 3 according to the desired specification of the OEIC 1 and the like. Are adjusted to a predetermined shape by a predetermined photolithography process and an etching process.

  Specifically, the collector layer 11, the base layer 12, and the emitter layer 13 that cover the anode contact layer 7 and the active layer 6 are removed. As a result, the collector layer 11, the base layer 12, and the emitter layer 13 are electrically disconnected from the anode contact layer 7 and the active layer 6 and left only on the cathode contact layer 5. At the same time, the cathode contact layer 5 covered only with the collector layer 11, the base layer 12 and the emitter layer 13 is electrically separated from the cathode contact layer 5 covered only with the anode contact layer 7 and the active layer 6. . Thus, the cathode contact layer 5 covered only with the collector layer 11, the base layer 12, and the emitter layer 13 is used as the collector contact layer 10 with which the collector layer 11 of the InP-based HBT 3 is in electrical contact. That is, the InP-based HBT 3 uses the cathode contact layer 5 of the photodiode 2 as the collector contact layer 10.

  Thereafter, a cathode electrode 8 is provided on the cathode contact layer 5, and an anode electrode 9 is provided on the anode contact layer 7. Similarly, a collector electrode 14 is provided on the collector contact layer 10, a base electrode 15 is provided on the base layer 12, and an emitter electrode 16 is provided on the emitter layer 13. Thereafter, an OEIC 1 having a desired structure is obtained through a predetermined process. That is, as shown in FIG. 1, an OEIC 1 is obtained in which a photodiode 2 and an InP-based HBT 3 are provided close to each other in a predetermined region on a single semi-insulating InP substrate 4.

  Here, with reference to FIG. 6, the characteristics of the method for manufacturing the optoelectronic integrated circuit of the present embodiment described above will be described. FIG. 6 is a graph showing changes in the amount of increase in In concentration in the InGaAs layer (film) with respect to the distance from the optical element formation region. A graph indicated by a solid line in FIG. 6 is a graph showing a change in the In concentration increase amount for the InGaAs layer formed by the entire surface regrowth method according to the present embodiment. Further, the graph shown by the broken line in FIG. 6 is a graph showing a change in the In concentration increase amount for the InGaAs layer formed by the selective regrowth method according to the background art.

  According to the graph shown by the broken line in FIG. 6, in the InGaAs layer formed by the selective regrowth method, the change in the In concentration increase is remarkably increased as the optical element formation region is approached. On the other hand, according to the graph shown by the solid line in FIG. 6, in the InGaAs layer formed by the whole surface regrowth method in which the HBT 3 layer is completely regrown on the substrate 4 without using the growth mask, Regardless of the distance from the formation region, there is almost no change in the In concentration increase. That is, according to the optoelectronic integrated circuit manufacturing method of the present embodiment using the entire surface regrowth method, the InGaAs layer in the vicinity of the optical element region, which is a problem in the background art optoelectronic integrated circuit manufacturing method using the selective regrowth method. It was found that almost no deviation (defect) in the composition occurred. As a result, according to the method of manufacturing the optoelectronic integrated circuit of this embodiment, the physical re-proximity distance between the photodiode 2 and the InP-based HBT 3 can be easily set to about 10 μm or less, which has been almost impossible in the past. It was revealed. Therefore, according to the optoelectronic integrated circuit manufacturing method of the present embodiment, the wiring delay between the photodiode 2 and the InP-based HBT 3 can be easily reduced, and the operation speed of the optoelectronic integrated circuit 1 can be increased. . At the same time, the degree of integration of the optoelectronic integrated circuit 1 can be easily increased.

  As described above, according to the first embodiment, the InP-based HBT 3 uses the cathode contact layer 5 of the photodiode 2 as the collector contact layer 10. As a result, when the InP-based HBT 3 is regrown on the entire surface, the step substantially corresponding to the sum of the thicknesses of the cathode contact layer 5 and the active layer 6 of the photodiode 2 can be reduced to about 0.5 μm. As a result, the InP-based HBT 3 can be grown more smoothly than the selective regrowth method according to the background art.

  Further, the collector layer 11, the base layer 12, and the emitter layer 13 of the InP-based HBT 3 are regrown on the entire surface of the semi-insulating InP substrate 4. Thereby, it is possible to provide the respective epitaxial crystal layers 11, 12, and 13 constituting the InP-based HBT 3 while optimizing the layer structure. At the same time, the collector layer 11 and the base layer 12 of the InP-based HBT 3 are grown separately from the active layer 6 and the anode contact layer 7 of the photodiode 2. Thereby, the layer structures of the respective epitaxial crystal layers 5, 6, 7 of the cathode contact layer 5, the active layer 6, and the anode contact layer 7 constituting the photodiode 2 can be provided while being optimized. As a result, the trade-off between the operating speed of the InP HBT 3 and the light receiving sensitivity of the photodiode 2 described in the background art is almost eliminated, and both the operating speed of the InP HBT 3 is increased and the sensitivity of the photodiode 2 is increased. be able to. That is, the photodiode 2 and the InP-based HBT 3 can be mixedly mounted on the semi-insulating InP substrate 4 with appropriate settings, with almost no risk of canceling out the respective performances.

  Therefore, the OEIC 1 of the present embodiment is appropriately provided with the possibility that the photodiode 2 and the InP-based HBT 3 cancel each other's performances, and has a high operating speed and high light receiving sensitivity. Further, according to the present embodiment, such an OEIC 1 can be efficiently and easily manufactured by using the whole surface regrowth method.

(Second Embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIGS. FIG. 7 is a cross-sectional view showing the optoelectronic integrated circuit according to the present embodiment. FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the optoelectronic integrated circuit according to the present embodiment. In addition, the same code | symbol is attached | subjected to the same part as 1st Embodiment mentioned above, and the detailed description is abbreviate | omitted.

  In the present embodiment, as described above, ion implantation is performed in order to insulate part of the collector contact layer (cathode contact layer) made of n-type InP, and an optical modulator is provided as an optical element. This is different from the first embodiment. This will be described below.

  As shown in FIG. 7, in the optoelectronic integrated circuit (OEIC) 21 according to the present embodiment, an insulating layer 24 is provided on a part of a collector contact layer 23 made of n-type InP on which an InP-based HBT 22 is mounted. ing. Specifically, the insulating layer 24 is formed by the following process.

  First, as shown in FIG. 8, a part of the surface of the collector contact layer 23 is selectively exposed by the same process as that of the first embodiment described above. Thereafter, as shown by the white arrow in FIG. 8, the InP-based HBT 22 inclined InGaAsP and the collector layer 11 made of n-type InP, the base layer 12 made of p-type InGaAs, and the emitter layer 13 made of n-type InP are half-finished. Prior to the overall growth on the insulating InP substrate 4, ions are selectively implanted into a part of the exposed surface of the collector contact layer 23 in the semiconductor element formation region. For example, at least one of H, He, O, and Fe is used as the selectively implanted ions. Subsequently, activation annealing treatment (heating treatment) is performed on the ion-implanted collector contact layer 23 and the like. Thereby, a part of the collector contact layer 23 is insulated and the insulating layer 24 is provided.

  Thereafter, the collector layer 11, the base layer 12, and the emitter layer 13 of the InP-based HBT 22 are entirely regrown on the semi-insulating InP substrate 4. Thereafter, an OEIC 21 having a desired structure is obtained through the same steps as in the first embodiment. That is, as shown in FIG. 7, the photodiode 2 and the InP-based HBT 3 are provided close to each other in a predetermined region on a single semi-insulating InP substrate 4, and the collector contact layer The OEIC 21 in which the insulating layer 24 is provided on a part of the OEIC 21 is obtained.

  In the present embodiment, the optical modulator 25 is provided as an optical element in the optical element formation region. In this case, the active layer 26 is formed in a configuration in which the core layer 26b is sandwiched between the first and second clad layers 26a and 26c. Each of these layers 26a, 26b, and 26c is also an epitaxial crystal layer. Specifically, the active layer 26 is a first clad layer (lower clad layer) 26a made of n-type InP on the side in contact with the cathode contact layer 5 and the side in contact with the anode contact layer 27 is made of undoped InGaAlAs. Two clad layers (upper clad layers) 26c are formed respectively. A core layer 26b made of n-type InP and p-type InP is formed between the first clad layer 26a and the second clad layer 26c. Further, in this optical modulator 25, the anode contact layer 27 is formed of an epitaxial crystal layer made of n-type InP.

  As described above, according to the second embodiment, the same effects as those of the first embodiment described above can be obtained. Further, by providing the insulating layer 24 in a part of the collector contact layer 23, the parasitic collector capacitance component in the external base of the InP HBT 22 can be eliminated, and the operation speed of the InP HBT 22 can be further increased.

(Third embodiment)
Next, a third embodiment according to the present invention will be described with reference to FIGS. FIG. 9 is a cross-sectional view showing the optoelectronic integrated circuit according to the present embodiment. 10 to 23 are process cross-sectional views illustrating the method for manufacturing the optoelectronic integrated circuit according to the present embodiment. FIG. 24 is a graph showing characteristics of the optoelectronic integrated circuit manufacturing method according to the present embodiment and characteristics of the optoelectronic integrated circuit manufacturing method according to the background art. In addition, the same code | symbol is attached | subjected to the same part as each 1st and 2nd embodiment mentioned above, and the detailed description is abbreviate | omitted.

  In the present embodiment, a bipolar transistor is provided via a conductive layer on another first electrode layer that is formed in the same process as the first electrode layer of the optical element and is electrically separated. The first embodiment is different from the first embodiment in that each of the first electrode layers is formed in a two-layer structure. Hereinafter, a detailed description will be given with reference to FIGS.

  First, the optoelectronic integrated circuit 31 according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 9, the OEIC 31 of the present embodiment is also an optical element formation region on the right side of the alternate long and short dash line in FIG. 9, similarly to the OEICs 1 and 21 of the first and second embodiments described above. The left side is a semiconductor element formation region. A photodiode 32 is provided in the optical element formation region. Further, the HBT 33 is provided in the semiconductor element formation region. The photodiode 32 and the HBT 33 are mounted on the same semi-insulating substrate 4 made of InP. That is, in the OEIC 31, the photodiode 32 and the InP-based HBT 33 share the semi-insulating InP substrate 4.

The photodiode 32 includes a cathode contact layer 34 as a first electrode layer made of high-concentration n-type InP and n-type InGaAs, an active layer 6, and an anode contact layer 35 as a second electrode layer made of p-type InGaAs. It is composed of In the present embodiment, the cathode contact layer 34 is formed in a laminated structure including two layers of a high concentration n-type InP layer 34a on the lower side and a high concentration n-type InGaAs layer 34b on the upper side. The n-type InP layer 34a has a doping concentration set to 5 × 10 ¹⁸ cm ⁻³ or more and a film thickness of about 400 to 1000 nm. The n-type InGaAs layer 34b has a doping concentration set to 5 × 10 ¹⁸ cm ⁻³ or more and a film thickness of about 10 to 50 nm. Further, the active layer 6 is formed in a laminated structure including two layers, a traveling layer 6a composed of inclined InGaAsP and n-type InP layers on the lower side and a light absorption layer 6b composed of p-type InGaAs layers on the upper side. The cathode contact layer 34 is provided with the cathode electrode 8, and the anode contact layer 35 is provided with the anode electrode layer 9.

The InP HBT 33 has the same two-layer structure of the n-type InP layer 34a and the n-type InGaAs layer 34b as the cathode contact layer 34 of the photodiode 32, and is electrically separated from the cathode contact layer 34. It is mounted on the semi-insulating InP substrate 4 via another first electrode layer 36 provided independently. The first electrode layer 36 becomes a so-called collector contact layer. The InP-based HBT 33 includes a conductive layer 37 made of a high-concentration n-type InP layer, a collector layer 11 made of inclined InGaAsP and n-type InP, a base layer 38 made of high-concentration p-type InGaAs, and an emitter layer made of n-type InP. 13. Thus, the base layer 38 and the emitter layer 13 are formed of different materials and are heterojunctioned. The conductive layer 37 made of a high-concentration n-type InP layer has a doping concentration set to 5 × 10 ¹⁸ cm ⁻³ or more and a film thickness of about 20 to 100 nm. The collector electrode 14 is provided on the collector contact layer 36, the base electrode 15 is provided on the base layer 38, and the emitter electrode 16 is provided on the emitter layer 13.

  Next, a process of forming the OEIC 31 will be described with reference to FIGS. First, the process of forming the InP-based HBT 33 will be described with reference to FIGS.

  First, as shown in FIG. 10, the cathode contact layer 34, the active layer 6, and the anode contact layer 35 are sequentially stacked on the semi-insulating InP substrate 4. Each of these layers 34, 6 and 35 is provided by at least one of the MOCVD method and the MBE method. That is, the cathode contact layer 34, the active layer 6, and the anode contact layer 35 of the photodiode 32 are each formed by epitaxial growth on the semi-insulating InP substrate 4.

  Next, as shown in FIG. 11, a first mask 39 is provided to cover a part of the surface of the anode contact layer 35 in the optical element formation region. Specifically, the first mask 39 is a photoresist film patterned into a predetermined shape by a photolithography technique. The first photoresist film 39 is provided on the anode contact layer 35 by, for example, a coating method.

  Next, as shown in FIG. 12, with the first photoresist mask 39 applied on the anode contact layer 35, the anode contact layer 35 and the active layer 6 are etched and removed by dry etching. At this time, the anode contact is directed from the first photoresist film 39 side toward the cathode contact layer 34 side and from the portion of the anode contact layer 35 and the active layer 6 covered with the photoresist film 39 toward the outside. The portions of the layer 35 and the active layer 6 that are not covered with the first photoresist film 39 are sequentially etched and removed. That is, the anode contact layer 35 and the first photoresist film 39 of the active layer 6 are covered with the first photoresist film 39 of the anode contact layer 35 and the active layer 6 obliquely downward from the portion covered with the first photoresist film 39 of the anode contact layer 35 and the active layer 6. The parts that are not removed are removed by sequential etching. As a result, unnecessary anode contact layers 35 and active layers are formed on the cathode contact layer 34 while leaving more anode contact layers 35 and active layers 6 from the first photoresist film 39 side toward the cathode contact layer 34 side. 6 is removed. That is, the anode contact layer 35 and the active layer 6 are left on the cathode contact layer 34 in a predetermined shape, and a part of the surface of the cathode contact layer 34 is selectively exposed. Thereafter, the first photoresist film 39 is removed from the anode contact layer 35. Further, after this dry etching, surface treatment is applied to the anode contact layer 35 and the active layer 6 left on the cathode contact layer 34 by wet etching.

  By applying dry etching to the etching of the anode contact layer 35 and the active layer 6 as in the present embodiment, all the surfaces of the layers 35 and 6 are inclined regardless of the crystal orientation of the anode contact layer 35 and the active layer 6. The angles can be made almost the same size. In the present embodiment, the etching is performed so that the inclination angle of the anode contact layer 35 and the active layer 6 left on the cathode contact layer 34 is about 45 °.

  Next, as shown in FIG. 13, the exposed surface of the cathode contact layer 34, the active layer 6, and the anode contact layer 35 are covered, and the conductive layer 37, the collector layer 11, the base layer 38, and the emitter layer of the InP-based HBT 33. 13 are sequentially stacked on the semi-insulating InP substrate 4 by regrowth over the entire surface. Each of these layers 37, 11, 38, 13 is also provided by at least one of the MOCVD method and the MBE method, like the cathode contact layer 34, the active layer 6, and the anode contact layer 35 of the photodiode 2. That is, the conductive layer 37, the collector layer 11, the base layer 38, and the emitter layer 13 of the InP-based HBT 33 are each formed by epitaxial growth over the entire surface of the semi-insulating InP substrate 4. Further, as described above, the mesa in the optical element forming region has an inclination of about 45 °. Therefore, the layer thicknesses of the layers 37, 11, 38, 13 covering flat regions on the cathode contact layer 34 and the anode contact layer 35, and the layers 37, 11, 11 covering the inclined portions of the anode contact layer 35 and the active layer 6, The layer thicknesses 38 and 13 are almost the same.

  Next, as shown in FIG. 14, the conductive layer 37, collector layer 11, base layer 38 on the cathode contact layer 34 without the anode contact layer 35 and the active layer 6 in the region on the semi-insulating InP substrate 4. In the first region where the emitter layer 13 is provided, a second mask is provided to selectively cover part of the surface of the emitter layer 13. Specifically, the second photoresist mask 40 is provided so as to selectively cover a part of the surface of the emitter layer 13 in the region where the InP-based HBT 33 is formed in the region on the semi-insulating InP substrate 4.

  Next, as shown in FIG. 15, the portion of the emitter layer 13 that is not covered with the second photoresist mask 40 is entirely exposed from above the semi-insulating InP substrate 4 (base layer 38) by dry etching and wet etching. And the surface of the base layer 13 is exposed. Therefore, by this etching process, not only the emitter layer 13 not covered with the second photoresist mask 40 in the HBT formation region (first region) but also the first of the regions on the semi-insulating InP substrate 4. The emitter layer 13 in the photodiode formation region, which is the second region excluding the first region, is also removed.

  Next, as shown in FIG. 16, after the second photoresist mask 40 is removed, the emitter layer 13 left on the base layer 38 in the first region is entirely covered to expose the exposed base. A third photoresist mask 41 as a third mask is selectively provided on the surface of the layer 38. Thereafter, wet etching is performed with the third photoresist mask 41 applied on the surface of the base layer 38. As a result, portions of the base layer 38, the collector layer 11, and the conductive layer 37 that are not covered by the third photoresist mask 41 are sequentially and entirely removed from the semi-insulating InP substrate 4 (cathode contact layer 34). Thus, at least a part of the surface of the cathode contact layer 34 in the HBT formation region is selectively exposed. At this time, not only the base layer 38, the collector layer 11 and the conductive layer 37 that are not covered with the third photoresist mask 41 in the HBT formation region, but also the base layer 38, the collector layer 11 in the photodiode formation region, The conductive layer 37 is also removed. As a result, the anode contact layer 35 and the active layer 6 provided on the cathode contact layer 34 in the photodiode formation region are exposed. Thereafter, the third photoresist mask 41 is removed from the base layer 38. The anode contact layer 35 made of InGaAs in the photodiode formation region serves as an etching stopper layer when the conductive layer 37 is etched. Therefore, the conductive layer 37 covering the anode contact layer 35 and the active layer 6 can be selectively removed to expose the anode contact layer 35 and the active layer 6.

  Next, as shown in FIG. 17, in the HBT formation region, the collector electrode 14 is formed on the cathode contact layer 34 to be the collector contact layer 36, the base electrode 15 is formed on the base layer 38, and the emitter layer 13 is formed. Are each provided with an emitter electrode 16. As a result, an InP-based HBT 33 having the structure described above is obtained. Further, the anode electrode 9 is provided on the anode contact layer 35 in the photodiode formation region.

  Next, a process of forming the photodiode 32 will be described with reference to FIGS.

  The inclined portions of the anode contact layer 35 and the active layer 6 exposed by the above-described processes may be deteriorated in quality due to an increase in defect density in the epitaxial layer due to a thermal history due to regrowth. A defect generated in the inclined portion causes an increase in leakage current in the photodiode 32, resulting in a decrease in reliability of the photodiode 32. Therefore, the epitaxial layer in the inclined portion of the anode contact layer 35 and the active layer 6 left on the cathode contact layer 34 is removed, and the photodiode 2 is formed using an internal epitaxial layer that hardly causes quality degradation. There is a need to.

  First, as shown in FIG. 18, the entire exposed surface of the cathode contact layer 34, the entire InP-based HBT 33, a part of the upper surface of the anode contact layer 35, and the running layer (graded InGaAsP and n-type InP) 6a of the active layer 6 are formed. A fourth photoresist mask 42 as a fourth mask is provided so as to cover a part of the inclined portion.

  Next, as shown in FIG. 19, the anode contact layer 35 and the light absorption layer (p-type InGaAs layer) 6b of the active layer 6 that are not covered with the fourth photoresist mask 42 by sulfuric acid-based wet etching are semi-insulating. The entire surface is sequentially removed from the InP substrate 4 (running layer 6a) to selectively expose a part of the surface of the running layer 6a of the active layer 6. The width of the anode contact layer 7 and the active layer 6 removed by this etching process is indicated by W1 in FIG. In the present embodiment, the width W1 is set to about 5 μm or less.

  Next, as shown in FIG. 20, the running layer 6a of the active layer 6 that is not covered with the fourth photoresist mask 42 by hydrochloric acid-based wet etching is sequentially applied from the semi-insulating InP substrate 4 (cathode contact layer 34). By removing the entire surface, a part of the surface of the cathode contact layer 5 in the photodiode formation region is selectively exposed. Thereafter, the fourth photoresist mask 42 is removed from the cathode contact layer 34.

  Next, as shown in FIG. 21, the cathode electrode 8 is provided on the cathode contact layer 34 in the photodiode formation region. As a result, the photodiode 32 having the above-described structure is obtained.

  Next, as shown in FIG. 22, a fifth photoresist mask 43 as a fifth mask is selectively formed on the exposed cathode contact layer 34 by covering the entire surface of the InP-based HBT 33 in the HBT formation region. Is provided. At the same time, a sixth photoresist mask 44 as a sixth mask independent of the fifth photoresist mask 43 covers the entire surface of the photodiode 32 in the photodiode formation region, and is exposed to the cathode contact layer. 34 is selectively provided.

  Next, as shown in FIG. 23, the cathode contact layer 34 that is not covered with the fifth photoresist mask 43 and the sixth photoresist mask 44 is entirely removed from the semi-insulating InP substrate 4 by wet etching. Remove. As a result, the cathode contact layer 34 on the semi-insulating InP substrate 4 is electrically separated from each other in the HBT formation region and the photodiode formation region and left independent from each other. As a result, the photodiode 32 and the InP-based HBT 33 are electrically disconnected. The cathode contact layer 34 left in the HBT formation region becomes the collector contact layer 36 of the InP-based HBT 33.

  Thereafter, an OEIC 31 having a desired structure is obtained through a predetermined process. That is, as shown in FIG. 23, an OEIC 31 is obtained in which a photodiode 32 and an InP-based HBT 33 are provided close to each other in a predetermined region on a single semi-insulating InP substrate 4.

  Here, with reference to FIG. 24, the effect of the entire surface regrowth, which is a feature of the above-described method for manufacturing the optoelectronic integrated circuit of the present embodiment, will be described. FIG. 24 is a graph showing changes in the In concentration increase in the InGaAs layer with respect to the distance from the optical element formation region. A graph indicated by a solid line in FIG. 24 is a graph showing a change in the In concentration increase amount for the InGaAs layer formed by the entire surface regrowth method according to the present embodiment. A graph indicated by a broken line in FIG. 24 is a graph showing a change in the In concentration increase in the InGaAs layer formed by the selective regrowth method according to the background art.

  According to the graph shown by the broken line in FIG. 24, in the InGaAs layer formed by the selective regrowth method, the change in the In concentration increase amount becomes remarkably large as it approaches the optical element formation region. On the other hand, according to the graph shown by the solid line in FIG. 24, in the InGaAs layer formed by the entire surface regenerating method in which the HBT 3 layer is completely regrown on the substrate 4 without using the growth mask, Regardless of the distance from the formation region, there is almost no change in the amount of increase in In concentration. That is, according to the optoelectronic integrated circuit manufacturing method of the present embodiment using the entire surface regrowth method, the InGaAs layer in the vicinity of the optical element, which is a problem in the background art optoelectronic integrated circuit manufacturing method using the selective regrowth method, is used. It was found that almost no compositional deviation (defect) occurred. As a result, according to the method of manufacturing the optoelectronic integrated circuit of this embodiment, the physical closest distance between the photodiode 32 and the InP-based HBT 33 indicated by W2 in FIG. 23 is within 10 μm, which was almost impossible in the past. It became clear that it was easy to set. Therefore, according to the optoelectronic integrated circuit manufacturing method of the present embodiment, the wiring delay between the photodiode 32 and the InP-based HBT 33 can be easily reduced, and the operation speed of the optoelectronic integrated circuit 1 can be increased. . At the same time, the degree of integration of the optoelectronic integrated circuit 1 can be easily increased. That is, also in this embodiment. It has been found that the same effect as in the first embodiment described above can be obtained.

  As described above, according to the third embodiment, the InP-based HBT 33 uses the same electrode layer as the cathode contact layer 34 of the photodiode 32 as the collector contact layer 36. Thus, when the InP-based HBT 33 is regrown on the entire surface, the step substantially corresponding to the sum of the thicknesses of the cathode contact layer 34 and the active layer 6 of the photodiode 32 can be reduced to about 0.5 μm. it can. As a result, the InP-based HBT 33 can be grown more smoothly than the selective regrowth method according to the background art.

In the present embodiment, the upper layer 34b of the cathode contact layer 34 as the first electrode layer serving as the regrowth interface is a high concentration n-type InGaAs layer having a doping concentration of 5 × 10 ¹⁸ cm ⁻³ or more. It has become. For this reason, even if impurities that can be n-type dopants such as carbon, oxygen, and silicon are mixed in the cathode contact layer 34 due to the cathode contact layer 34 coming into contact with the atmosphere, the impurities in the cathode contact layer 34 There is little risk of affecting the doping concentration. That is, there is almost no influence on the resistance of the cathode contact layer 34. At the same time, in the present embodiment, the high-concentration n-type InP layer having a doping concentration of 5 × 10 ¹⁸ cm ⁻³ or more is formed on the high-concentration n-type InGaAs layer 34 b of the cathode contact layer 34. The conductive layer 37 is grown to a thickness of about 20 to 100 nm. For this reason, even if impurities such as carbon, oxygen, and silicon are mixed in the cathode contact layer 34, these impurities are taken into the conductive layer 37. Therefore, there is almost no possibility that these impurities will affect the doping concentration of the collector layer 11 grown on the conductive layer 37. That is, there is almost no possibility that the quality of the collector layer 11 as an epitaxial layer which is epitaxially grown on the conductive layer 37 by regrowth will deteriorate. As a result, there is almost no possibility that the operation speed of the InP-based HBT 33 is lowered, and there is almost no possibility that the performance of the InP-based HBT 33 is deteriorated.

  In this embodiment, the conductive layer 37, the collector layer 11, the base layer 38, and the emitter layer 13 of the InP-based HBT 33 are regrown on the semi-insulating InP substrate 4 over the entire surface. Thereby, it is possible to provide the respective epitaxial crystals 37, 11, 38, and 13 constituting the InP-based HBT 33 while optimizing the layer structure. At the same time, the collector layer 11 and the base layer 38 of the InP-based HBT 33 are grown separately from the active layer 6 and the anode contact layer 35 of the photodiode 32. Thereby, the layer structures of the epitaxial crystal layers 34, 6 and 35 of the cathode contact layer 34, the active layer 6 and the anode contact layer 35 constituting the photodiode 32 can be provided while being optimized. As a result, the trade-off between the operating speed of the InP-based HBT and the light receiving sensitivity of the photodiode described in the background art is almost eliminated, and both the operating speed of the InP-based HBT 33 is increased and the sensitivity of the photodiode 32 is increased. Can do. That is, the photodiode 32 and the InP-based HBT 33 can be mixedly mounted on the semi-insulating InP substrate 4 with appropriate settings, with almost no risk of canceling out the respective performances.

  Therefore, the OEIC 31 of this embodiment is appropriately provided with the possibility that the photodiode 32 and the InP-based HBT 33 cancel each other's performances, and has a high operating speed and high light receiving sensitivity. In addition, according to the present embodiment, such an OEIC 31 can be efficiently and easily manufactured by using the whole surface regrowth method.

  Note that the optoelectronic integrated circuit and the manufacturing method thereof according to the present invention are not limited to the first to third embodiments described above. Without departing from the spirit of the present invention, a part of the configuration or manufacturing process can be changed to various settings, or various settings can be appropriately combined and used. .

  For example, in each of the first to third embodiments, the semi-insulating substrate made of InP is used as the semi-insulating substrate, but the present invention is not limited to this. A semi-insulating substrate may be formed using various materials other than InP as appropriate depending on the specifications of a desired optoelectronic integrated circuit.

  Further, for example, the cathode contact layer 5 (collector contact layer 10), the active layer 6, and the anode contact layer 7 of the photodiode 2 of the first embodiment are respectively formed of the n-type InP, the p-type InGaAs, the inclined InGaAsP, and the n-type. It is not necessarily formed from InP and p-type InGaAsP. Similarly, the collector layer 11, the base layer 12, and the emitter layer 13 of the InP-based HBT 3 are not necessarily formed from the above-described inclined InGaAsP, n-type InP, p-type InGaAs, and n-type InP, respectively. Similarly, the active layer 26 and the anode contact layer 27 of the optical modulator 25 are not necessarily formed from the above-described n-type InP, p-type InP, undoped InGaAlAs, and n-type InP, respectively. These layers 5 to 7, 10 to 13, 26, and 27 may be formed using various materials other than the above materials as appropriate according to the desired specifications of the optoelectronic integrated circuit.

  Similarly, for example, the cathode contact layer 34, the active layer 6, and the anode contact layer 35 of the photodiode 32 of the third embodiment are the high-concentration n-type InP layer 34 a and the high-concentration n-type InGaAs layer 34 b, respectively. It is not necessarily formed of the traveling layer 6a made of inclined InGaAsP and n-type InP, the light absorption layer 6b made of p-type InGaAs layer, and the p-type InGaAs layer. Similarly, the collector contact layer 36 (cathode contact layer 34), the conductive layer 11, the collector layer 12, the base layer 13 and the emitter layer 14 of the InP-based HBT 33 also have the above-described high concentration n-type InP layer 34a and high concentration, respectively. The n-type InGaAs layer 34b, the high-concentration n-type InP layer, the layer composed of inclined InGaAsP and n-type InP, the high-concentration p-type InGaAs layer, and the n-type InP are not necessarily formed. Each of these layers 34, 6, 35, 36, 37, 11, 38, and 13 may be made of various materials other than the above materials as appropriate according to the desired specifications of the optoelectronic integrated circuit.

  Moreover, elements other than the photodiodes 2 and 32 may be included in the optical element that the present invention may be provided. For example, a light composed of a first contact layer made of an n-type InP layer, an active layer made of a p-type InP layer, an undoped InP layer, and an InGaAIAsMQW layer, and a second contact layer made of an n-type InP layer Such as a modulator.

  Further, the cathode contact layer 34 (collector contact layer 36) composed of the high concentration n-type InP layer 34a and the high concentration n-type InGaAs layer 34b used in the third embodiment is replaced with the cathode contact layer 5 ( Of course, it may be applied to the collector contact layer 10).

1 is a cross-sectional view showing an optoelectronic integrated circuit according to a first embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 1st Embodiment. The figure which shows the characteristic of the manufacturing method of the optoelectronic integrated circuit which concerns on 1st Embodiment, and the characteristic of the manufacturing method of the optoelectronic integrated circuit which concerns on background art as a graph, respectively. Sectional drawing which shows the optoelectronic integrated circuit which concerns on 2nd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 2nd Embodiment. Sectional drawing which shows the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. Process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment. The figure which shows the characteristic of the manufacturing method of the optoelectronic integrated circuit which concerns on 3rd Embodiment, and the characteristic of the manufacturing method of the optoelectronic integrated circuit which concerns on background art as a graph, respectively. Sectional drawing which shows the optoelectronic integrated circuit which concerns on background art.

Explanation of symbols

1, 21, 31 ... OEIC (optoelectronic integrated circuit)
2, 32 ... Photodiode (optical integrated circuit, optical element)
3, 22, 33 ... InP-based HBT (semiconductor integrated circuit, semiconductor element, electronic element)
4 ... Semi-insulating InP substrate (semi-insulating substrate)
5 ... Cathode contact layer (first electrode layer, n-type InP layer, epitaxial crystal layer)
6 ... Active layer (p-type InGaAs layer, inclined InGaAsP layer, n-type InP layer, epitaxial crystal layer)
6a ... traveling layer (gradient InGaAsP layer, n-type InP layer)
6b: Light absorption layer (p-type InGaAs layer)
7 ... anode contact layer (second electrode layer, p-type InGaAsP layer, epitaxial crystal layer)
10 ... Collector contact layer (conductive layer, n-type InP layer)
11 ... Collector layer (gradient InGaAsP layer, n-type InP layer, epitaxial crystal layer)
12 ... Base layer (p-type InGaAs layer, epitaxial crystal layer)
13 ... Emitter layer (n-type InP layer, epitaxial crystal layer)
17 ... Photoresist film (mask)
23 ... Collector contact layer 24 ... Insulating layer 25 ... Optical modulator (optical integrated circuit, optical element)
26 ... Active layer (n-type InP layer, p-type InP layer, undoped InGaAlAs layer, epitaxial crystal layer)
26a: first cladding layer (n-type InP layer, lower cladding layer)
26b ... Core layer (n-type InP layer, p-type InP layer)
26c ... second clad layer (undoped InGaAlAs layer, upper clad layer)
27 ... Anode contact layer (second electrode layer, n-type InP layer, epitaxial crystal layer)
34 ... cathode contact layer (one first electrode layer, high-concentration n-type InP layer, high-concentration n-type InGaAs layer, epitaxial crystal layer)
34a: Lower layer of cathode contact layer (high concentration n-type InP layer, lower layer of first electrode layer)
34b ... Upper layer of cathode contact layer (high concentration n-type InGaAs layer, upper layer of first electrode layer)
35 ... Anode contact layer (second electrode layer, p-type InGaAs layer, epitaxial crystal layer)
36 ... Collector contact layer (cathode contact layer, other first electrode layer, high concentration n-type InP layer, high concentration n-type InGaAs layer, epitaxial crystal layer)
37. Conductive layer (high-concentration n-type InP layer, epitaxial crystal layer)
38 ... Base layer (high concentration p-type InGaAs layer, epitaxial crystal layer)
39: First photoresist mask (first mask)
40. Second photoresist mask (second mask)
41 ... Third photoresist mask (third mask)
42 ... Fourth photoresist mask (fourth mask)
43 ... Fifth photoresist mask (fifth mask)
44 ... Sixth photoresist mask (sixth mask)

Claims (24)

A semi-insulating substrate;
One of the first electrode layers of at least two first electrode layers provided independently and adjacent to each other on the semi-insulating substrate, and one of the first electrode layers are stacked. An optical element composed of an active layer and a second electrode layer,
A conductive layer provided on the other first electrode layer among the first electrode layers, a collector layer provided on the conductive layer, a base layer provided on the collector layer, and the base The conductive layer, the collector layer, the base layer, and the emitter layer are separately laminated with the active layer and the second electrode layer, respectively. A bipolar transistor provided adjacent to the optical element;
An optoelectronic integrated circuit comprising: 2. The optoelectronic integrated circuit according to claim 1, wherein the first electrode layer is formed in a laminated structure including two layers of a high concentration n-type InP layer and a high concentration n-type InGaAs layer. The conductive layer, optoelectronic integrated circuit according to any of claims 1 or 2, characterized in that it consists of high-concentration n-type InP layer. The optoelectronic integrated circuit according to any one of claims 1 to 3 , wherein the first electrode layer, the active layer, and the second electrode layer are epitaxial crystal layers. Said conductive layer, said collector layer, said base layer, and the emitter layer, optoelectronic integrated circuit according to any of claims 1-4, characterized in that the epitaxial crystal layer. It said semi-insulating substrate, an optoelectronic integrated circuit according to any one of claims 1-5, characterized in that it is formed by InP. The optoelectronic integrated circuit according to any one of claims 1 to 6 , wherein the bipolar transistor is a heterojunction bipolar transistor in which the base layer and the emitter layer are formed of different materials. The bipolar transistor, optoelectronic integrated circuit according to any one of claims 1-7, characterized in that said base layer is a heterojunction bipolar transistor formed by a different material as the second electrode layer . Some of the first electrode layer of the other, optoelectronic integrated circuit according to any one of claims 1 to 8, characterized in that the insulating layer is formed by ion implantation. The optoelectronic integrated circuit according to claim 9 , wherein the ion is at least one of H, He, O, and Fe. Optoelectronic integrated circuit according to any one of the optical element, according to claim 1-10, wherein the active layer is characterized in that it is a photodiode comprising a light absorbing layer and transport layer. The optical device is any of the claims 1-10, wherein the active layer is a light modulator comprising sandwiching a core layer between the first cladding layer and the second clad layer An optoelectronic integrated circuit according to 1. A step of sequentially laminating a first electrode layer, an active layer, and a second electrode layer on a semi-insulating substrate;
A first mask is provided to selectively cover a part of the surface of the second electrode layer, and the second electrode layer is moved from the first mask side toward the first electrode layer side. And a portion covered with the first mask of the second electrode layer and the active layer from the first mask side toward the first electrode layer side while leaving a large amount of the active layer The portions of the second electrode layer and the active layer that are not covered with the first mask are sequentially removed from the outer surface toward the outside thereof, and a part of the surface of the first electrode layer is selectively exposed. A process of
After removing the first mask, a conductive layer, a collector layer, a base layer, and an emitter layer are formed to cover the exposed surface of the first electrode layer, the second electrode layer, and the active layer. A step of sequentially laminating the entire surface on the semi-insulating substrate,
The conductive layer, the collector layer, the base layer, and the emitter layer are provided on the first electrode layer without the second electrode layer and the active layer in the region on the semi-insulating substrate. A second mask is provided to selectively cover a part of the surface of the emitter layer in the first region formed, and a portion of the emitter layer not covered by the second mask is semi-insulated After removing the entire surface from the conductive substrate to expose the surface of the base layer and removing the second mask, the emitter layer left on the base layer in the first region is entirely exposed. A third mask is selectively provided on the surface of the base layer exposed over the substrate, and a portion of the base layer, the collector layer, and the conductive layer not covered by the third mask is formed on the surface of the base layer. Semi-insulated A step for selectively exposing a portion of the surface of at least said first electrode layer in the first region from the substrate by sequentially entirely removed,
After removing the third mask, a fourth mask is provided so as to selectively cover a part of the surface of the second electrode layer, and the fourth electrode of the second electrode layer and the active layer are provided. The portion not covered by the mask is sequentially and entirely removed from the semi-insulating substrate, and the first region in the second region excluding the first region among the regions on the semi-insulating substrate is removed. Selectively exposing part of the surface of the electrode layer;
The first electrode exposed after covering the conductive layer, the collector layer, the base layer, and the emitter layer left in the first region after removing the fourth mask. A fifth mask is selectively provided on the surface of the layer, and a sixth mask independent of the fifth mask is left in the second region and the second electrode layer. Is selectively provided on the exposed surface of the first electrode layer, and then is not covered by the fifth mask and the sixth mask of the first electrode layer. Is removed from the entire surface of the semi-insulating substrate, and the first electrode layer, the conductive layer, the collector layer, the base layer, and the emitter layer left in the first region; The first electrode layer left in the second region, the active layer, A step of electrically disconnecting the reserve the second electrode layer,
A method of manufacturing an optoelectronic integrated circuit. 14. The method of manufacturing an optoelectronic integrated circuit according to claim 13 , wherein the first electrode layer is formed in a laminated structure including two layers of a high concentration n-type InP layer and a high concentration n-type InGaAs layer. . 15. The method of manufacturing an optoelectronic integrated circuit according to claim 13 , wherein the conductive layer is formed of a high concentration n-type InP layer. It said first electrode layer, the active layer, and the second electrode layer, the claims 13-15, characterized in that provided in succession by at least one of a metal organic vapor phase epitaxy and molecular beam epitaxy The manufacturing method of the optoelectronic integrated circuit in any one of them. Said collector layer, said base layer, and said emitter layer, according to any one of claims 13 to 16, characterized in that provided in succession by at least one of a metal organic vapor phase epitaxy and molecular beam epitaxy Of manufacturing an optoelectronic integrated circuit. The method of manufacturing an optoelectronic integrated circuit according to any one of claims 13 to 17 , wherein the semi-insulating substrate is formed of InP. A heterojunction bipolar transistor comprising the collector layer, the base layer, and the emitter layer is provided on the first electrode layer by forming the base layer and the emitter layer from different materials and performing heterojunction. The method of manufacturing an optoelectronic integrated circuit according to any one of claims 13 to 18 . Photoelectrons according to any one of claims 13 to 19, characterized by providing a heterojunction bipolar transistor in which the base layer is formed of a material different from said second electrode layer on the first electrode layer A method of manufacturing an integrated circuit. After selectively exposing a portion of the surface of the first electrode layer, prior to providing the collector layer, the base layer, and the emitter layer, the collector layer, the base layer, and the emitter Insulating the ion-implanted portion of the first electrode layer by selectively ion-implanting a portion of the first electrode layer covered only by the layer and performing a heat treatment 21. A method of manufacturing an optoelectronic integrated circuit according to any one of claims 13 to 20 . The method of manufacturing an optoelectronic integrated circuit according to claim 21 , wherein at least one of H, He, O, and Fe is used as the ion. The active layer is formed of a light absorption layer and a running layer, and a photodiode having the light absorption layer and the running layer sandwiched between the first electrode layer and the second electrode layer is semi-insulating. the method of manufacturing an optoelectronic integrated circuit according to claims 13 to 22, characterized in that provided on the substrate. The active layer is formed by sandwiching a core layer between a first cladding layer and a second cladding layer, and the first cladding layer, the second cladding layer, and the core layer are formed as the first cladding layer. method of manufacturing an optoelectronic integrated circuit according to claims 13 to 22, characterized in providing an optical modulator formed by interposing between the electrode layer a second electrode layer on the semi-insulating substrate.

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