JP3289415B2 - Method for manufacturing semiconductor device having adjacent contact - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having adjacent contacts, and more particularly, to a method for manufacturing a semiconductor device capable of reducing the distance between adjacent contacts.

[0002]

2. Description of the Related Art A lower conductive layer (including an impurity diffusion layer formed on the surface of a semiconductor substrate) and an upper conductive layer (wiring layer)
And a predetermined pattern, a contact hole is formed in the interlayer insulating layer, and the lower conductive layer and the upper conductive layer are contact-connected through the contact hole.

FIG. 8 shows an example of a bit line contact provided for each memory cell of an SRAM. As shown in FIG. 8, in an SRAM memory cell, an interlayer insulating layer 4 is laminated on the surface of a lower conductive layer 2 on which a selection thin film transistor (TFT) and the like are formed. Holes 6 and 8 are formed. Conductor plugs 10, 1 are provided in contact holes 6, 8, respectively.
2 are embedded, and for each of the conductor plugs 10 and 12,
Wiring layers 14 and 16 such as bit lines wired in a predetermined pattern are connected on the interlayer insulating layer 4.

In the SRAM memory cell, the wiring layers 14 and 16 serving as bit lines are made of an aluminum alloy or the like in order to reduce the resistance, and the conductor plugs 10 and 12 are made of polysilicon or tungsten which is easily embedded. Etc.

[0005]

Each SRAM memory cell requires a pair of adjacent wiring layers 14 and 16 to be used as a bit line and an inverted bit line, and as the memory cell becomes smaller, the wiring layers 14 and 16 become smaller. By the width L and the interval S of
There is a problem that reduction in the size of the memory cell is limited. The width L and the spacing S of the wiring layers 14 and 16 are determined by the minimum processing size and the like limited by the photolithography processing, and cannot be reduced below that. Therefore, one side of the memory cell could not be reduced to 2 × (L + S) or less.

In the SRAM, the wiring layers 14 and 16 serving as bit lines and inverted bit lines are made of an aluminum alloy having relatively low workability. The design rule must be looser than the design rule, which hinders a reduction in cell area.

An object of the present invention is to provide a method of manufacturing a semiconductor device which has been made in view of such a situation and which can reduce the distance between adjacent contacts and achieve high integration. Another object of the present invention is to provide a method of manufacturing an SRAM memory cell capable of reducing the memory cell.

[0008]

[0009]

[0010]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In the method of manufacturing a semiconductor device according to the present invention, a wiring layer connected to a conductor plug embedded in one adjacent contact hole is formed integrally with the conductor plug, and the wiring layer is embedded in the other contact hole. The wiring layer connected to the conductor plug is patterned by photolithography in a process different from the photolithography for patterning the conductor plug.

[0011]

[0012]

[0013]

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device having an adjacent contact according to the present invention will be described based on an embodiment shown in the drawings.
This will be described in detail. FIG. 1 is a sectional view of a main part of a semiconductor device having an adjacent contact according to an embodiment of the present invention, and FIG.
3 (A) to 3 (E) and 4 (F) to 4 (J) are cross-sectional views of a main part showing a method of manufacturing the semiconductor device shown in FIG. 1, and FIG. 6A to 6D and FIGS. 7E and 7F show a method of manufacturing the semiconductor device shown in FIG. 5 according to another embodiment. It is principal part sectional drawing.

A semiconductor device 18 according to an embodiment of the present invention shown in FIGS. 1 and 2 is a semiconductor device having an SRAM memory cell, and the method of the present invention is applied to a bit line contact. As shown in FIG. 2, the SRAM memory cell includes a pair of driving transistors DT1 and DT2 forming a flip-flop circuit, selection transistors ST1 and ST2 for selecting a memory cell, and load transistors LT1 and LT2. Have. Selection transistor ST
1 and ST2 depend on the gate voltage generated on the word line.
The transistor is turned on, and the driving transistor DT
The information stored in the flip-flop circuit composed of ST1 and ST2 is transmitted to the bit line b and the inverted bit line b '.

The selection transistors ST1 and ST2 and the load transistors LT1 and LT2 are thin film transistors (TFTs) made of, for example, a polysilicon thin film.
It consists of. As shown in FIG. 1, the wiring layers 32 and 38 constituting the bit line b and the inverted bit line b ′ are formed by the conductor plugs 2 embedded in the contact holes 24 and 26.
It is connected to the lower conductive layer 20 via 8, 30. In this embodiment, the lower conductive layer 20 is formed with the source / drain regions of the select transistors ST1 and ST2 shown in FIG.

As shown in FIG. 1, on the lower conductive layer 20, a first interlayer insulating layer 22 is formed. One adjacent first wiring layer 32 is formed on the first interlayer insulating layer 22 so as to be connected to the conductor plug 28 buried in the one contact hole 24. The other second wiring layer 38 is formed on the second interlayer insulating layer 3 laminated on the first interlayer insulating layer on which the one first wiring layer 32 is formed.
4 and is connected to the conductor plug 30 through an auxiliary contact hole 36 formed in the second interlayer insulating layer 34.

Next, a manufacturing example for obtaining a bit line contact having the structure shown in FIG. 1 will be described with reference to FIGS. As shown in FIG. 3A, in the present embodiment, first, a first interlayer insulating layer 22 is deposited on the lower conductive layer 20. The manufacturing process up to the formation of the lower conductive layer 20 is a general S
This is the same as the method of manufacturing the RAM. First interlayer insulating layer 22
Is formed of, for example, but not limited to, a silicon oxide film. The thickness of the first interlayer insulating layer 22 is not particularly limited, but is, for example, about 100 to 400 nm.

On the first interlayer insulating layer 22, FIG.
As shown in (B), a resist film 40 is formed, and openings 41 and 42 are subjected to photolithography processing on the resist film 40 in a pattern in which a contact hole is to be formed. Next, as shown in FIG. 3C, dry etching is performed through the openings 41 and 42 to remove the resist film 40 and form contact holes 24 and 26.

Next, as shown in FIG. 1D, a plug forming layer 44 is deposited on the first interlayer insulating layer 22 in which the contact holes 24 and 26 are formed. Plug forming layer 44
Is, for example, polysilicon deposited by a CVD method,
Alternatively, it is made of tungsten or the like. The thickness of the plug forming layer 44 is such that it completely fills the contact holes 24 and 26 formed in the first interlayer insulating layer 22, and is, for example, about 200 to 800 nm.

Next, as shown in FIG. 1E, the plug forming layer 44 is entirely etched back by an etch-back process using a dry etching technique or the like, and the conductor plugs 28 and Leave 30.
Next, as shown in FIG.
The first wiring forming layer 46 is deposited on the first interlayer insulating layer 22 on which 0 is formed. The first wiring forming layer 46 is made of, for example, an aluminum-based alloy and has a thickness of 4 mm.
It is about 00 to 1000 nm.

Next, as shown in FIG. 2G, a pattern for connecting to the conductor plug 28 buried in the adjacent one of the contact holes 24 by a photolithography technique using a resist film 48 and a dry etching technique. so,
The first wiring forming layer 46 is patterned to form the first wiring layer 32.
Get.

Next, as shown in FIG. 2H, the resist film 48 is removed, and a second interlayer insulating layer 34 is deposited on the first interlayer insulating layer 22 on which the first wiring layer 32 is formed. Let it.
Second interlayer insulating layer 34 is made of, for example, silicon oxide deposited by a CVD method. This second interlayer insulating layer 3
On top of this, a resist film 50 is laminated. An opening 52 is formed in the resist film 50 by a photolithography method with a pattern overlapping the other contact hole 26.

Next, using the resist film 50 having the opening 52 as a mask, dry etching is performed to form an auxiliary contact hole 36 in the second interlayer insulating layer 34 as shown in FIG. I do. The auxiliary contact hole 36 is formed so as to communicate with the lower contact hole 26.

Thereafter, a second wiring forming layer 54 is deposited on the second interlayer insulating layer 34. The second wiring forming layer 54 is made of, for example, an aluminum-based alloy, and has a thickness of, for example, about 400 to 1000 nm. A resist film 56 is stacked on the second wiring forming layer 54, and after processing the resist film 56 in a predetermined pattern by photolithography, dry etching is performed as shown in FIG. Then, a second wiring layer 38 is obtained.

In the manufacturing method of the present embodiment, one first wiring layer 32 serving as the bit line b shown in FIG. 2 and the other second wiring layer 38 serving as the inverted bit line b 'shown in FIG. And formed of different wiring layers. That is, the wiring layers 32 and 38 are formed in separate photolithography processing steps. Therefore, in the manufacturing method of the present embodiment, the interval between the wiring layers 32 and 38 can be made as small as possible. In extreme cases, the wiring layers 32, 3
The interval between the eight may be set to 0 or less (overlap) when viewed from the plane side.

However, in this embodiment, as shown in FIG. 1, the width Lb of the second wiring layer 38 may be larger than the width La of the first wiring layer 32. However, since the second wiring layer 38 and the first wiring layer 32 can be arranged so as to overlap each other when viewed from the plane side, the area of the memory cell is reduced as compared with the conventional example shown in FIG. be able to. It is preferable that the width of the second wiring layer 38 be increased from the viewpoint of reducing the resistance.

In this embodiment, the processing of the wiring layers 32 and 38 constituting the bit line is facilitated, and the wiring layers 32 and 3 are formed.
8, it is possible to increase the film thickness, and it can be expected that the wiring resistance is reduced. Next, another embodiment of the present invention will be described.

The semiconductor device 18a according to the embodiment shown in FIG.
Is a semiconductor device having SRAM memory cells,
The method of the present invention is applied to bit line contacts. In the present embodiment, as shown in FIG.
The interlayer insulating layer 62 is formed on the zero. Contact holes 64 and 66 are formed in the interlayer insulating layer 62 at adjacent positions.
Is formed. In each contact hole 64, 66,
Conductor plugs 68 and 72 are embedded.

In this embodiment, the wiring layer 74 connected to the conductor plug 72 embedded in one of the adjacent contact holes 66 is formed integrally with the conductor plug 72. The wiring layer 70 connected to the conductor plug 68 embedded in the other contact hole 64 is formed separately from the conductor plug 68.

Next, a main part of a method of manufacturing a semiconductor device having the bit line contact structure shown in FIG. 5 will be described with reference to FIGS. As shown in FIG. 6A, first, an interlayer insulating layer 62 is deposited on the lower conductive layer 60. The manufacturing process up to the formation of the lower conductive layer 60 is a general SRA
It is the same as the manufacturing method of M. Although not particularly limited, the interlayer insulating layer 62 is made of, for example, a silicon oxide film. The thickness of the interlayer insulating layer 62 is not particularly limited, but is, for example, about 100 to 400 nm.

A resist film 77 is formed on the interlayer insulating layer 62 as shown in FIG.
At 77 , the openings 75 and 76 are photolithographically processed with a pattern in which a contact hole is to be formed. Next, dry etching is performed through the openings 75 and 76 to form contact holes 64 and 66.

Next, as shown in FIG. 3C, a plug forming layer 78 is deposited on the interlayer insulating layer 62 in which the contact holes 64 and 66 are formed. The plug forming layer 78
For example, it is made of polysilicon or tungsten deposited by a CVD method. The thickness of the plug formation layer 78 is such that it completely fills the contact holes 64 and 66 formed in the interlayer insulating layer 62, and is, for example, about 200 to 800 nm.

Next, as shown in FIG. 4D, a resist film 80 is formed on the plug forming layer 78, and this resist film 80 is connected to one adjacent wiring layer (one bit line). Then, the plug forming layer 78 is processed by using the resist film 80 by using the dry etching technique, and as shown in FIG.
The conductor plugs 68 and 72 are left in the 66. In addition, the wiring layer 74 is formed on the one conductor plug 72 and integrally therewith.

Next, as shown in FIG. 3F, a wiring forming layer 82 is deposited on the interlayer insulating layer 62 on which one wiring layer 74 has been formed. The wiring forming layer 82 is made of, for example, an aluminum-based alloy, and has a thickness of, for example, 200
About 1000 nm. A resist film 84 is laminated on the wiring forming layer 82, the resist film 84 is processed in a predetermined pattern by photolithography, and then dry etching is performed, as shown in FIG. A layer 70 is obtained.

In the manufacturing method according to the present embodiment, the interval Sa between the wiring layers 70 and 74 serving as bit lines and inverted bit lines is
It can be as small as possible. For example, this interval Sa
Can be approximated by the sum of the alignment accuracy of the exposure apparatus and the processing variation, and the value is about 0.15 to 0.2 μm. On the other hand, in the conventional method shown in FIG.
0.5 μm was the limit.

The present invention is not limited to the above-described embodiments, but can be variously modified within the scope of the present invention. For example, in the above-described embodiment, the method of the present invention is applied to the bit line contact of the SRAM memory cell. However, the present invention is not limited to these embodiments. Can be applied to the semiconductor device.

[0038]

As described above, according to the present invention, the distance between adjacent wiring layers can be extremely reduced . Therefore, processing margin of the wiring layer becomes large, the processing is easy.

If the bit line contact of the SRAM memory cell is formed by using the method of the present invention, the interval between adjacent bit lines can be reduced, so that the memory cell can be reduced. Further, the processing of the bit line is facilitated, the thickness of the wiring layer can be increased, and a reduction in wiring resistance can be expected.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device having an adjacent contact according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of an SRAM memory cell.

3 (A) to 3 (E) are cross-sectional views of essential parts showing a method for manufacturing the semiconductor device shown in FIG. 1;

4 (F) to 4 (J) are cross-sectional views of essential parts showing a step following that shown in FIG.

FIG. 5 is a cross-sectional view of a main part of a semiconductor device having adjacent contacts according to another embodiment of the present invention.

6 (A) to 6 (D) are cross-sectional views of essential parts showing a method of manufacturing the semiconductor device shown in FIG.

7 (E) and 7 (F) are cross-sectional views of essential parts showing a step following that of FIG.

FIG. 8 is a cross-sectional view of a main part of a semiconductor device according to a conventional example.

[Explanation of symbols]

 18, 18a Semiconductor device 20, 60 Lower conductive layer 22 First interlayer insulating layer 24, 26, 64, 66 Contact hole 28, 30, 68, 72 Conductor plug 32 First wiring layer 34 First Two interlayer insulating layers 36 Auxiliary contact holes 38 Second wiring layers 70 and 74 Wiring layers b Bit lines b 'Inverted bit lines

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/28 H01L 27/11 H01L 21/8244

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a contact in which a contact hole is buried with a conductor plug, the method comprising: forming a wiring layer connected to a conductor plug buried in one adjacent contact hole with the conductor plug. The wiring layer connected to the conductor plug embedded in the other contact hole is formed integrally with the conductor plug, and is patterned by a photolithography process in a step different from the photolithography process for patterning the conductor plug. A method for manufacturing a semiconductor device having an adjacent contact.