JP3311191B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of efficiently cooling a semiconductor chip.

[0002]

2. Description of the Related Art A conventional semiconductor device having a semiconductor chip on which active circuit elements, passive circuit elements, and wiring are formed will be described with reference to a schematic sectional view of FIG.

In FIG. 14, reference numeral 1 denotes a semiconductor chip on which one surface is used as a circuit forming surface 2 to form active circuit elements, passive circuit elements, and wiring. Reference numeral 3 denotes a package, on one side of which a recess 4 for accommodating the semiconductor chip 1 is formed, and the semiconductor chip 1 is fixed to the bottom of the recess 4 so that the other surface is adhered. The opening of the recess 4 in which the semiconductor chip 1 is housed is hermetically closed by a lid 5, and the inside of the recess 4 is filled with an inert gas.

Further, a cooling device 6 such as a radiation fin is provided on the other surface of the package 3. For this reason, the heat generated by the active circuit elements and the like of the semiconductor chip 1 may reach the package 3 from the bonding surface of the semiconductor chip 1 and the package 3 by heat conduction from the circuit forming surface 2 to the inside of the semiconductor chip 1,
Air that is transmitted to the package 3 by natural convection of the inert gas in the concave portion 4 and further follows the heat transfer path to the cooling device 6 by heat conduction inside the package 3, and the air flowing in the cooling device 6 as indicated by the white arrow, etc. And is discharged to the outside. Reference numeral 8 denotes an external lead provided on the other surface of the package 3 and is connected to a corresponding portion of the semiconductor chip 1 by a bonding wire 9.

[0005] However, in the above prior art,
Since the heat resistance of the heat transfer path from the circuit forming surface 2 to the cooling device 6 is large, it is difficult to efficiently cool the temperature of the circuit forming surface 2 which is a heat generating portion by the cooling device 6 and sufficiently lower the temperature. . Further, the temperature difference between the temperature of the circuit forming surface 2 being cooled and the temperature of the cooling device 6 increases as the amount of heat generated in the heat generating portion increases. If the integration density increases, it is expected that the heat generation density will also increase, and even if a liquid is used as the cooling medium, circuit formation will not be feasible due to thermal limitations, realizing a semiconductor device capable of more efficient cooling. Is strongly desired.

[0006]

As described above, conventionally,
The heat generated in the active circuit elements of the semiconductor chip is released to the cooling device via the heat transfer path by heat conduction in the semiconductor chip and the package, so that the heat transfer path has high thermal resistance, and is efficient and sufficient. It is assumed that the chip cannot be cooled, and the circuit cannot be formed when the active circuit elements and the like formed on the semiconductor chip are highly integrated. The present invention has been made in view of such a situation, and an object of the present invention is to efficiently and sufficiently cool a semiconductor chip and to form active circuit elements and the like on a semiconductor chip with a high degree of integration. It is to provide a semiconductor device which can be used.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor chip circuit elements are formed, a through hole provided to penetrate through the semiconductor chip, the semiconductor switch
Cooling means for cooling the tip using a cooling medium,
At least one of the circuit elements is an inner wall surface of the through hole.
The cooling means further comprises:
Convection cooling means for allowing a medium to flow therethrough , and further, the cooling means boils the through-hole.
Is intended characterized in that it is a boil cooling means for the Agakaku, also a semiconductor chip circuit elements are formed, this
A groove provided in the semiconductor chip, and the semiconductor chip
Cooling means for cooling using a cooling medium;
At least one of the path elements faces the inner wall surface of the groove.
Is characterized by being formed , furthermore,
The cooling unit allows the cooling medium to flow through the groove.
And characterized in that a convective cooling means, further, the cooling means, boiling cooling hand to boiling nuclear said groove
Characterized by steps, and at least
A semiconductor chip having at least one through hole;
Opening, and the opening communicates with the through-hole.
A mounting member on which the semiconductor chip is mounted,
Hand through which the cooling medium flows through the through hole and the opening
And a step .

[0008]

In the semiconductor device constructed as described above, a cooling hole is formed in a semiconductor chip, so that the heat transfer coefficient when a cooling medium flows through the cooling hole is the same as that of a conventional radiation fin. The heat transfer coefficient is several tens of times greater than the heat transfer coefficient when a cooling medium flows along the surface of a flat plate, and the cooling medium flows in direct contact with the active circuit elements of the semiconductor chip and is very efficient. Cooling is possible.

[0009] It is also possible to perform boiling cooling using cooling holes or cooling grooves formed in the semiconductor chip as boiling nuclei.

On the other hand, since the active circuit elements are provided on the inner wall surfaces of the cooling holes or the cooling grooves formed in the semiconductor chip, the heat transfer coefficient increases and the cooling medium flows directly in contact with the active circuit elements. As a result, heat can be dissipated in a state where the thermal resistance is very small, and efficient cooling can be performed.
Further, it is possible to increase the degree of integration of active circuit elements and the like without requiring miniaturization of the structure.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view, and FIG. 2 is a cross-sectional view of a main part partially shown in cross-section.

In FIG. 1 and FIG. 2, reference numeral 11 denotes a semiconductor device.
It is configured to house a semiconductor chip 15 having a rectangular plate shape of about 500 μm. Here, the mounting member is not limited to the package, but may be a short substrate. This is the same in the following embodiments. Semiconductor chip 15
Is formed, for example, by dividing a Si wafer on which a plurality of semiconductor circuits are formed, and the active circuit elements 16 and the passive circuit elements (not shown) and the wirings 17 are formed on one surface of the circuit forming surface 18 at a depth δ from the surface. Formed in a range.

The semiconductor chip 15 is mounted on the circuit forming surface 1.
8 is fixed to a corresponding pad portion 20 provided on the inner bottom surface 14 of the concave portion 13 via a bump 19 that conducts to a semiconductor circuit provided in the semiconductor device 8. The pad portion 20 is fixed to the inner bottom surface 14 of the recess 13 so as to be electrically connected to an external lead (not shown). As a result, a gap 21 corresponding to the height of the bump 19 is formed between the circuit forming surface 18 and the inner bottom surface 14 of the recess 13.

The semiconductor chip 15 has a width of, for example, several μm, which penetrates from the one side of the circuit forming surface 18 to the other side near the portion where the active circuit element 16 is formed.
A plurality of cooling holes 22 having a circular cross section having a diameter of about several tens of μm, and in some cases, several hundred μm in accordance with the amount of generated heat and the like, are formed. The cooling hole 22 communicates with the gap 21 between the recess 13 and the inner bottom surface 14.

On the other hand, one end of a cooling medium branch pipe 23 is attached to the other surface of the semiconductor chip 15 so as to include the opening of the cooling hole 22 in an airtight manner.
The other end of the cooling medium branch pipe 23 is attached so as to communicate with a side port 26 of a cooling medium pipe 25 that closes and closes the opening 24 of the recess 13 in an airtight manner with the outer surface of the pipe wall. Here, the cooling medium branch pipe 23 may be, for example, a bellows formed in a bellows shape.

Further, a cooling medium introduction port 27 is formed in the package 12 so as to communicate with the inside of the concave portion 13. It is designed to introduce air. As a result, the cooling medium introduced into the recess 13 through the cooling medium inlet 27 flows through the cooling hole 22 from the gap 21 as shown by the solid arrow, and further flows into the cooling medium pipe 25 through the cooling medium branch 23. .

In the present embodiment configured as described above, when the semiconductor device 11 is operated, the cooling medium is supplied from the cooling medium source to the cooling medium inlet 27 so that the semiconductor device 1 can be operated.
1, that is, the semiconductor chip 15 is cooled.

This cooling is performed by introducing the cooling medium into the recess 13 through the cooling medium inlet 27 and flowing the cooling medium toward the cooling medium pipe 25 which has a lower pressure than the inside of the recess 13. The cooling medium introduced and diffused into the recess 13 flows through the gap 21 along the circuit forming surface 18 of the semiconductor chip 15, and flows from the circuit forming surface 18 through the cooling hole 22 to the other surface of the semiconductor chip 15. The cooling medium reaching the other surface of the semiconductor chip 15 is cooled by the cooling medium branch pipe 23.
And flows from the side port 26 to the cooling medium pipe 25.

Although not shown, the inside of the recess 13 may be set at a lower pressure than the cooling medium pipe 25, and the cooling medium may be supplied from the cooling medium pipe 25 to the semiconductor chip 15 via the cooling medium branch pipe 23. . In this case, the cooling medium flows through a path opposite to the path indicated by the solid arrow in FIG.

The active circuit elements 16 and the like formed on the semiconductor chip 15 are in direct contact with the flow of the cooling medium, and the heat of the semiconductor chip 15 and the package 12 and the like having a large thermal resistance as in the prior art. Cooling is performed with very low thermal resistance without conduction. The heat transfer coefficient involved in flowing a cooling medium into the cooling holes 22 formed in the semiconductor chip 15 is determined by the conventional cooling device (see FIG. 14).
As described above, since the heat transfer coefficient is several tens times larger than the heat transfer coefficient when the cooling medium flows along the surface of the flat plate, very efficient cooling is performed.

Although the cooling holes 22 formed in the semiconductor chip 15 of the above embodiment have a circular cross section, the present invention is not limited to this. can get.

A simulation was performed using a computer in order to confirm the state of cooling in this embodiment. In this simulation, a 5 W power FET in which a transistor element as an active circuit element is formed at the center of one surface of a 5 mm square semiconductor chip was used as a model. Here, as a counterpart to this embodiment, a cooling hole having a rectangular cross section of 0.2 mm square is provided at the center of the semiconductor chip, and cooling is performed by flowing air of a cooling medium so as to pass through the cooling hole. The temperature of the transistor was calculated.

Further, as a comparative example, a radiating fin was provided on the other surface of the semiconductor chip on which no transistor was formed, and the temperature of the transistor when air was flowed through the radiating fin and cooled was calculated. Then, when the calculated temperature of the transistor in this example and the calculated temperature of the transistor in the comparative example were compared, it was found that the temperature of the present example was lower by about 50K. From this result, it was confirmed that according to this example, efficient cooling can be performed.

Next, a second embodiment will be described with reference to FIG. FIG. 3 is a perspective view of a main part partially shown in cross section.

In FIG. 3, reference numeral 27 denotes a semiconductor device.
Inner bottom surface 14 of concave portion 13 of package 28 as a mounting member
The semiconductor chip 15 is accommodated therein. The semiconductor chip 15 is formed by dividing a semiconductor wafer on which a plurality of semiconductor circuits are formed, and an active circuit element 16, a passive circuit element (not shown) and a wiring 17 are provided on one side of the circuit forming surface 18, and have a depth from the surface. It is formed in the range of δ.

The semiconductor chip 15 is mounted on the circuit forming surface 1.
8 are fixed to corresponding pad portions (not shown) provided on the inner bottom surface 14 of the concave portion 13 via bumps 19 which are connected to the semiconductor circuit provided on the semiconductor device 8. This pad portion is fixed to the inner bottom surface 14 so as to conduct to the external lead. As a result, a gap 21 corresponding to the height of the bump 19 is formed between the circuit forming surface 18 and the inner bottom surface 14 of the recess 13.

A plurality of cooling holes 22 are formed in the semiconductor chip 15 near the portion where the active circuit element 16 is formed so as to penetrate from one surface, which is the circuit forming surface 18, to the other surface.
Are formed, and the cooling holes 20 are formed in the inner bottom surface 14 of the recess 13.
Are communicated with the gap 21 between them.

Further, in the concave portion 13 of the package 28, a liquid of a cooling medium supplied from a cooling medium supply source (not shown) fills the concave portion 13 and the gap 2 as shown by a solid arrow.
1 flows through the cooling hole 22 of the semiconductor chip 15 and then flows out of the recess 13. During this time, the semiconductor chip 15 immersed in the cooling medium is cooled by boiling.

In this embodiment configured as described above, the semiconductor chip 27 is operated to operate the semiconductor chip 15.
Generates heat. However, since the active circuit elements 16 and the like formed on the semiconductor chip 15 are in direct contact with the flow of the cooling medium, they are cooled with extremely low thermal resistance, and very efficient cooling is achieved. Done. Also, when the cooling medium filled in the recess 13 flows through the cooling holes 22 of the semiconductor chip 15, the cooling holes 22 serve as boiling nuclei to perform boiling cooling, thereby promoting heat transfer. Become.

The shape of the cooling hole 22 is not limited to the illustrated circular cross section, but may be a rectangular cross section or the like. When heat transfer is promoted by using boiling nuclei, the present invention is not limited to through holes, and holes or grooves with bottoms may be used as boiling nuclei.

Further, only the boiling cooling may be performed without forcibly flowing the cooling medium as in the present embodiment.

Next, a modification of the first and second embodiments will be described. FIG. 4 is a cross-sectional view of a main part, a part of which is shown in cross-section.

In FIG. 4, a plurality of cooling holes 30 having a long hole shape are formed so as to penetrate the semiconductor chip 29.
6 is formed in the vicinity. With such a configuration, the same operation and effect as those of the first and second embodiments can be obtained.

Next, a third embodiment will be described with reference to FIG. FIG. 5 is a schematic sectional view.

In FIG. 5, reference numeral 31 denotes a semiconductor device. A cavity 33 is formed in a package 32 of the semiconductor device.
5 and a downstream space 36. And cavity 3
A cooling medium inlet 37 and a cooling medium outlet 38 are formed in side walls of the upstream space 35 and the downstream space 36 of the third unit 3, and an opening 39 is formed in the center of the partition 34.

On one surface of the partition portion 34 on the upstream space 35 side, a semiconductor chip 40 is adhered and fixed to the partition portion 34 so that its peripheral edge is airtight so as to cover the opening 39. That is, in the present embodiment, the partition 34 is a mounting member. The semiconductor chip 40 is formed substantially the same as that of the first embodiment formed by dividing a semiconductor wafer on which a plurality of semiconductor circuits are formed, and is not shown on the circuit forming surface 18 on one surface thereof. The active circuit element, the passive circuit element, and the wiring are formed in a predetermined depth range from the surface.

The semiconductor chip 40 is provided with a plurality of cooling sections having a circular cross section so as to penetrate from the one side as the circuit forming surface 18 to the other side in the vicinity of the active circuit element formed at the center and the periphery thereof. A hole 22 is formed. Thus, the upstream space 3 divided into two by the partition portion 34
5 and the downstream space 36 communicate with each other through the cooling holes 22.

Further, one end of a bonding wire 41 is fixed to the semiconductor chip 40 so as to conduct to a semiconductor circuit provided on the circuit forming surface 18. The other end of the bonding wire 41 is not shown, but is not shown. It is fixed to a corresponding pad portion provided on one side so as to conduct to an external lead.

The cooling medium is supplied to the cooling medium inlet 37 from a cooling medium supply source (not shown). As a result, the cooling medium introduced into the upstream space 35 through the cooling medium inlet 37 flows through the inside of the cooling hole 22 of the semiconductor chip 40 to reach the downstream space 36 as shown by a solid arrow, and the cooling medium outlet 38 Is discharged from

Although not shown, the flow direction of the cooling medium may be opposite to the direction indicated by the solid arrow in FIG.

In the present embodiment configured as described above, when operating the semiconductor device 31, the cooling medium is supplied from the cooling medium supply source to the cooling medium inlet 37, so that the semiconductor device 31, that is, the semiconductor chip 40. Cooling takes place.

In cooling, the cooling medium introduced through the cooling medium inlet 37 diffuses into the upstream space 35 and flows from one surface of the circuit forming surface 18 of the semiconductor chip 40 through the cooling hole 22 to the other surface. Then, the cooling medium that has reached the downstream space 36 on the other surface side of the semiconductor chip 40 is discharged outside from the cooling medium discharge port 38.

As described above, the semiconductor chip 40 and the active circuit elements formed on the semiconductor chip 40 are cooled in direct contact with the flow of the cooling medium. Therefore, also in this embodiment, the same efficient cooling as in the first embodiment is performed.

Next, a fourth embodiment will be described with reference to FIG.
FIG. 6 is a perspective view of a main part of the semiconductor chip, a part of which is shown in cross section.

In FIG. 6, reference numeral 42 denotes a semiconductor chip, in which a plurality of cooling holes 43 having a circular cross section are formed so as to penetrate between the front and back surfaces. The semiconductor device is formed, for example, by housing the semiconductor chip 42 in a package (not shown) configured in the same manner as in the first or third embodiment, and providing a cooling medium to flow through the cooling hole 43. I have.

The semiconductor chip 42 has an active circuit element 16 constituting a semiconductor circuit, a passive circuit element (not shown) and wiring 17 provided on one surface 18. Further, the semiconductor chip 42 is fixed to a pad portion (not shown) via the bump 19 that is connected to the semiconductor circuit. Further cooling holes 43
A plurality of active circuit elements 16 and wirings 17 are formed on the inner wall surface portion facing the surface. Here, the wiring 17 is not limited to the wiring in the direction in which the cooling holes 43 extend as illustrated.

The semiconductor chip 42 constructed as described above
In the present embodiment, when the semiconductor device is operated, the cooling medium is supplied from the cooling medium supply source so as to flow through the cooling holes 43 of the semiconductor chip 42 and the semiconductor chip 42
Is cooled. Therefore, the active circuit elements 16 and the like formed on the one surface 18 of the semiconductor chip 42 and the inner wall surface of the cooling hole 43 are cooled directly in contact with the flow of the cooling medium. Therefore, also in this embodiment, the same efficient cooling as in the first embodiment is performed.

On the other hand, according to the present embodiment, the cooling holes 43
Since the active circuit element 16 and the like are provided on the inner wall surface of the device, the degree of integration can be increased without the need for miniaturization of the structure.

The semiconductor chip 42 according to the present embodiment may be applied to the second embodiment to perform cooling by boiling.

Next, a fifth embodiment will be described with reference to FIGS. FIG. 7 is a perspective view of a main part of the semiconductor chip, a part of which is shown in cross section, and FIG. 8 is a partial circuit diagram.

7 and 8, reference numeral 44 denotes a semiconductor chip on which a semiconductor circuit is formed. A plurality of cooling holes 45 having a circular cross section are formed so as to penetrate between the front and back surfaces. The semiconductor chip 44 is housed in a package (not shown) configured in the same manner as in the first or third embodiment shown in FIG. 1 or FIG. 5 so that the cooling medium flows through the cooling hole 45. A semiconductor device is formed.

The semiconductor chip 44 is formed by a first layer 46 ₁ , a second layer 46 ₂ ,...
They are stacked in this order of the top layer 46 _n. Each layer 46
_1, 46 _2, ..., the 46 _n, the capacitor 48, the bit line 49 of the transistors 47 and passive circuit elements of active circuit elements constituting the semiconductor circuit as shown in FIG. 8 is formed.

That is, each layer 46 is provided around the cooling hole 45.
_1, 46 _2, ..., 46 first impurity implantation region 50 ₁ at a distance from each other in _n, 50 _2, ..., ₁ 50 _n and the second impurity-implanted region 51, 51 _2, ..., 51 _n are provided, Further, each layer 46 ₁ , 46 ₂ ,
..., and the oxide film 52 and the first wiring 53 are layered in common 46 _n. Each layer 46 ₁ , 46 ₂ ,..., 46
_{In n} , the first impurity implanted regions 50 ₁ , 50 ₂ ,.
second wiring connected to _{n 49 1, 49 2, ...} , 49 n are provided.

As a result, the transistors 47 ₁ , 47 ₂ ,
.., 47 _n are formed by using the first wiring 53 as a gate electrode, the oxide film 52 as a gate insulating film,
_{1, 50 2, ..., 50} n and the second impurity implantation region 5
1 _1, 51 _2, ..., it formed a 51 _n source, as a drain region. Further, capacitors 48 ₁ , 48 ₂ ,.
48 _n are the second impurity implanted regions 51 ₁ , 51 ₂ ,.
51 _n and the base material of each layer 46 ₁ , 46 ₂ ,..., 46 _n . The first wiring 53 becomes a word line, and the second wirings 49 ₁ , 49 ₂ ,..., 49 _n become bit lines.

One end of a bonding wire (not shown) is fixed so as to conduct to the semiconductor circuit, and the other end is fixed to a corresponding pad portion provided on the package (not shown) so as to conduct to external leads.

The semiconductor chip 44 configured as described above
In the present embodiment, when the semiconductor device is operated, a cooling medium is supplied from a cooling medium supply source so as to flow through the cooling hole 45 of the semiconductor chip 44 and the semiconductor chip 44
Is cooled. Therefore, the transistors 47 ₁ , 47 ₂ ,..., 47 of the active circuit elements formed on the surface of the uppermost layer 46 _n of the semiconductor chip 44 and the inner wall surface of the cooling hole 45.
_{n and the} like are cooled by the flow of the cooling medium.
Therefore, also in this embodiment, the same efficient cooling as in the first embodiment is performed.

The semiconductor chip 44 according to the present embodiment may be applied to the second embodiment to perform cooling by boiling.

Further, since the transistors 47 ₁ , 47 ₂ ,..., 47 _{n and the} like are provided so as to face the inner wall surface of the cooling hole 45, the structure needs to be miniaturized as in the fourth embodiment. It is possible to increase the degree of integration without the need.

Next, a sixth embodiment will be described with reference to FIG.
FIG. 9 is a perspective view of a main part of a semiconductor chip, a part of which is shown in cross section.

In FIG. 9, reference numeral 55 denotes a semiconductor chip, in which a plurality of cooling holes 56 having a circular cross section are formed so as to penetrate between the front and back surfaces. And the semiconductor chip 55
Although not shown, the semiconductor device is housed in a package configured in the same manner as the above-described first or third embodiment, and is provided so as to allow a cooling medium to flow through the cooling holes 56.

The semiconductor chip 55 is made of, for example, GaAs.
The first layer 57 ₁ , the second layer 57 ₂ ,..., the lowermost layer in FIG. 8, and the uppermost layer 57 _n are formed in this order by epitaxial growth of s. Each layer 57 ₁ , 57 ₂ ,
, 57 _n around the edge forming the inner wall surface of the cooling hole 56, the transistors 58 ₁ , 58 ₂ ,.
N-type region 59 constituting the _{58 n 1, 59 2, ...} , 59 n
And a first ^{n +} -type region _{60 1, 60 2, ...,} 60 n, the second ^{n +} -type regions _{61 1, 61 2, ...,} 61 n are formed by exposure.

Further, the n-type regions 59 ₁ , 59 ₂ ,..., 59 _n and the first n ⁺ -type region 60
_1, 60 _2, ..., 60 _n, the second ^{n +} -type regions 61 _and 62
1 _2, ..., a 61 _n, the first wiring 62 to connect the axial direction, the second wire 63, third wiring 64 is provided. Thus, the first wiring 62 becomes a gate electrode, the second wiring 63 and the third wiring 64 become a source electrode and a drain electrode, and a large number of transistors 58 ₁ , 58 ₂ ,.
The semiconductor circuit has a configuration in which _n is connected in parallel.

One end of a bonding wire (not shown) is fixed so as to conduct to the semiconductor circuit, and the other end of the bonding wire is fixed to a corresponding pad portion (not shown) provided on a package.

The semiconductor chip 55 constructed as described above
In the present embodiment, when operating the semiconductor device, the cooling medium is supplied from the cooling medium supply source so as to flow through the cooling holes 56 of the semiconductor chip 55 so that the semiconductor chip 55
Is cooled. Therefore, the transistors 58 ₁ , 58 ₂ ,..., 58 _n of the active circuit elements formed so as to be exposed on the inner wall surface of the cooling hole 56 of the semiconductor chip 55 are cooled directly in contact with the flow of the cooling medium. become. Therefore, also in this embodiment, the same efficient cooling as in the first embodiment is performed.

Since the transistors 58 ₁ , 58 ₂ ,..., 58 _n are provided on the inner wall surface of the cooling hole 56, the degree of integration can be reduced without the need for miniaturization of the structure as in the fourth embodiment. It is possible to increase.

Incidentally, the semiconductor chip 55 according to the present embodiment may be applied to the second embodiment to perform boiling cooling.

Next, a seventh embodiment will be described with reference to FIG. FIG. 10 is a perspective view of a main part of a semiconductor chip, a part of which is shown in cross section.

In FIG. 10, reference numeral 65 denotes a semiconductor chip.
A plurality of cooling holes 66 having a circular cross section are formed so as to penetrate between the front and back surfaces. The semiconductor device is formed so that the semiconductor chip 65 is housed in a package (not shown) configured in the same manner as in the third embodiment, and the cooling medium flows through the cooling holes 66.

The semiconductor chip 65 is made of, for example, GaAs.
s cooling hole 66 formed so as to penetrate through the single crystal substrate
On the inner wall surface, a transistor 6 is formed in an axial direction by ion implantation.
7, an n-type region 68 and a first n ⁺ -type region 69,
The second n ⁺ -type region 70 is formed to be exposed. Further, a first wiring 71, a second wiring 72, and a third wiring 73 extending in the axial direction are provided in these regions 68, 69, and 70, and the first wiring 71 is a gate electrode and a second wiring. Wiring 7
The second and third wirings 73 serve as a source electrode and a drain electrode, and a large-area transistor 67 is formed on the inner wall surface of the cooling hole 66.

Then, one end of a bonding wire (not shown) is fixed so as to be electrically connected to the semiconductor circuit including the transistor 67, and the other end of the bonding wire is fixed to a corresponding pad portion provided on a package (not shown).

The semiconductor chip 65 configured as described above
In the present embodiment, when operating the semiconductor device, the cooling medium is supplied from the cooling medium supply source so as to flow through the cooling holes 66 of the semiconductor chip 65 so that the semiconductor chip 65
Is cooled. For this reason, a transistor 67 of an active circuit element which is formed so as to be exposed on the inner wall surface of the cooling hole 66 of the semiconductor chip 65 and can flow a large current with a large area.
Is cooled in direct contact with the flow of the cooling medium. Therefore, also in this embodiment, the same efficient cooling as in the first embodiment is performed.

Further, since the transistor 67 is provided on the inner wall surface of the cooling hole 66, it is possible to increase the degree of integration without requiring a fine structure as in the fourth embodiment.

The semiconductor chip 65 according to the present embodiment may be applied to the second embodiment to perform cooling by boiling.

Next, an eighth embodiment will be described with reference to FIGS. FIG. 11 is a schematic cross-sectional view, and FIG. 12 is a cross-sectional view of a main part partially shown in cross-section.

In FIGS. 11 and 12, reference numeral 81 denotes a semiconductor device, which is, for example, several mm to several tens of mm square and has a thickness of 100 μm to 500 μm.
It is configured to house a semiconductor chip 82 of a square plate shape of about m. The semiconductor chip 82 is formed, for example, by dividing an Si wafer on which a plurality of semiconductor circuits are formed.

The semiconductor chip 82 is fixed to a corresponding pad portion (not shown) provided on the inner bottom surface 14 of the concave portion 13 via a bump 19 which is connected to the semiconductor circuit on one side. This pad portion is fixed to the inner bottom surface 14 of the concave portion 13 so as to be electrically connected to an external lead (not shown). Thereby, one surface of the semiconductor chip 82 and the inner bottom surface 1 of the recess 13 are formed.
4, a gap corresponding to the height of the bump 19 is formed.

On the other hand, a plurality of cooling grooves 83 having a rectangular cross section are formed on the other surface of the semiconductor chip 82.
An active circuit element 84 constituting a semiconductor circuit is formed facing the side wall surface of the third semiconductor device. On the other surface of the semiconductor chip 82 housed in the concave portion 13, for example, a cooling medium branch pipe 23 formed in a bellows shape is air-tight at one end so as to include at least a part of the entire opening of the cooling groove 83. It is attached so as to be in close contact with.

Then, for example, cooling air as a cooling medium is introduced into the concave portion 13 of the package 12 through the cooling medium introduction port 27, and the introduced cooling medium flows in the cooling groove 83 in the groove direction as indicated by the solid arrow. Then, it is collected in the cooling medium branch pipe 23 and flows from the side port 26 to the cooling medium pipe 25.

In the present embodiment configured as described above, when operating the semiconductor device 81, the cooling medium is supplied from the cooling medium source to the cooling medium inlet 27 so that the semiconductor device 8 is operated.
1, that is, the cooling of the semiconductor chip 82 is performed. When the cooling medium flows from the cooling medium inlet 27 toward the cooling medium pipe 25 having a negative pressure, the cooling is performed by the active circuit element 84 provided in the cooling groove 83 of the semiconductor chip 82. This is performed by dissipating the heat generated in the active circuit element 84 by flowing the medium so as to be in direct contact therewith.

As described above, the active circuit element 84 comes into direct contact with the flow of the cooling medium and is cooled with extremely low thermal resistance, so that very efficient cooling is performed.

In the above embodiment, the cross-sectional shape of the cooling groove 83 is rectangular, but is not limited to this, and may be V-shaped or the like. Further, even when the semiconductor chip 82 has a laminated structure as in the fifth and sixth embodiments, the same operation and effect as those of the eighth embodiment can be obtained.

Next, a ninth embodiment will be described with reference to FIG. FIG. 13 is a schematic sectional view.

In FIG. 13, reference numeral 85 denotes a semiconductor device, which is configured to house a semiconductor chip 88 having a rectangular plate shape on the inner bottom surface 14 of the concave portion 87 of the package 86. The semiconductor chip 88 is formed, for example, by dividing an Si wafer on which a plurality of semiconductor circuits are formed, and active circuit elements, passive circuit elements, and wiring (not shown) are formed on the circuit forming surface 18 on one surface thereof.

The semiconductor chip 88 is fixed to a corresponding pad portion (not shown) provided on the inner bottom surface 14 of the concave portion 87 via a bump 19 which is connected to the semiconductor circuit on one side. This pad portion is fixed to the inner bottom surface 14 of the concave portion 87 so as to be electrically connected to an external lead (not shown). Thereby, one surface of the semiconductor chip 88 and the inner bottom surface 1 of the concave portion 87 are formed.
4, a gap corresponding to the height of the bump 19 is formed.

On the other hand, a cooling plate 89 is provided on the other surface of the semiconductor chip 88 so that one surface thereof is in close contact with this surface. The cooling plate 89 has a plurality of cooling holes 90 formed in a direction parallel to the main surface, and an opening 91 communicating with the cooling holes 90 is formed at the center of the other surface. Also, the cooling plate 89
On the other surface, for example, a cooling medium branch pipe 2 formed in a bellows shape
3 is attached so as to include the opening 91 inside so that one end is airtightly adhered.

The cooling medium, for example, cooling air is introduced into the concave portion 87 of the package 86 through the cooling medium introduction port 27, and the introduced cooling medium flows through the cooling hole 90 of the cooling plate 89 as shown by a solid arrow. The flow is collected in the cooling medium branch pipe 23 from the opening 91, and the cooling medium pipe 25 is
It is flowing to.

In the present embodiment configured as described above, when operating the semiconductor device 85, the cooling medium is supplied from the cooling medium source to the cooling medium inlet 27 so that the semiconductor device 8 is operated.
5, ie, cooling of the semiconductor chip 88 is performed. This cooling is performed by a cooling plate 89 provided so as to be in close contact with the other surface of the semiconductor chip 88 when the cooling medium flows from the cooling medium introduction port 27 toward the cooling medium pipe 25 having a negative pressure. When the cooling medium flows through the cooling holes 90, the heat generated in the active circuit elements of the semiconductor chip 88 is transmitted to the cooling medium via the cooling plate 89 and dissipated.

As described above, the semiconductor chip 88 having the active circuit element is cooled in contact with the flow of the cooling medium only through the cooling plate 89, so that the semiconductor chip 88 without the package 86 or the like has a very small thermal resistance. Efficient cooling is achieved.

[0089]

As is apparent from the above description, according to the present invention, a semiconductor chip can be efficiently and sufficiently cooled, and active circuit elements and the like can be formed on a semiconductor chip with a high degree of integration. And the like.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of the present invention.

FIG. 2 is a perspective view of a main part showing a part in cross section according to the first embodiment of the present invention.

FIG. 3 is a perspective view of a main part showing a part of a second embodiment of the present invention in cross section.

FIG. 4 is a perspective view of a main part showing a part of the first and second embodiments of the present invention in cross section.

FIG. 5 is a schematic sectional view showing a third embodiment of the present invention.

FIG. 6 is a perspective view of a main part of a semiconductor chip showing a part of a cross section according to a fourth embodiment of the present invention.

FIG. 7 is a perspective view of a main part of a semiconductor chip, a part of which is shown in cross section according to a fifth embodiment of the present invention.

FIG. 8 is a partial circuit diagram according to a fifth embodiment of the present invention.

FIG. 9 is a perspective view of a main part of a semiconductor chip, a part of which is shown in cross section according to a sixth embodiment of the present invention.

FIG. 10 is a perspective view of a main part of a semiconductor chip, a part of which is shown in cross section according to a seventh embodiment of the present invention.

FIG. 11 is a schematic sectional view showing an eighth embodiment of the present invention.

FIG. 12 is a perspective view of a main part of a semiconductor chip, a part of which is shown in cross section according to an eighth embodiment of the present invention.

FIG. 13 is a schematic sectional view showing a ninth embodiment of the present invention.

FIG. 14 is a schematic sectional view showing a conventional example.

[Explanation of symbols]

 15 ... Semiconductor chip 16 ... Active circuit element 22 ... Cooling hole

──────────────────────────────────────────────────続 き Continuing on the front page (72) Yasushi Godai, 2-4, Suehirocho, Tsurumi-ku, Yokohama-shi, Kanagawa Prefecture Inside Keihin Works, Toshiba Corporation (72) Kazuya Nishibori, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa No. 1 Toshiba R & D Center (72) Inventor Shimichi Matsuoka 1 Tokoba Toshiba-cho, Komukai, Kawasaki City, Kanagawa Prefecture (56) References JP-A-6-268110 (JP, A) JP-A-57-54352 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 23/34-23/473

Claims (7)

(57) [Claims] A semiconductor chip on which a circuit element is formed;
A through hole provided to penetrate the semiconductor chip; and a cooling device for cooling the semiconductor chip using a cooling medium.
Means, wherein at least one of said circuit elements is
A semiconductor device formed so as to face an inner wall surface of the through hole . 2. The semiconductor device according to claim 1, wherein said cooling means is a convection cooling means for flowing said cooling medium into said through hole. 3. The semiconductor device according to claim 1, wherein said cooling means is a boiling cooling means using said through hole as a boiling nucleus. 4. A semiconductor chip having a circuit element formed thereon,
A groove provided in the semiconductor chip;
Cooling means for cooling using a cooling medium,
At least one of the circuit elements faces the inner wall surface of the groove.
A semiconductor device characterized by being formed. 5. The cooling means includes a cooling medium in the groove.
Convection cooling means for flowing through the body
The semiconductor device according to claim 4. 6. The cooling means uses the groove as a boiling nucleus.
5. The half as claimed in claim 4, wherein said cooling means is a boiling cooling means.
Conductor device. 7. A semiconductor having at least one through hole.
A chip, having at least one opening,
The semiconductor chip is mounted so that the through hole communicates with the semiconductor chip.
Mounting member, through the through-hole and the opening
Means for allowing a cooling medium to flow therethrough.
Semiconductor device.