JP3348428B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor (FET) manufactured using a semiconductor substrate such as GaAs or InP, and more particularly, to a high-power amplifier or a high-power amplifier operating in a microwave frequency band. The present invention relates to a field-effect transistor effectively applied to a switch circuit and the like.

[0002]

2. Description of the Related Art With the development of mobile communication systems in recent years, the demand for small and high-performance components operating at high frequencies has been increasing. In response to this trend, FETs, especially Ga
MESFET made of a compound semiconductor such as As, H
EMT and the like have been put into practical use as transistors that can overcome the characteristic limits of Si bipolar transistors conventionally used in the high frequency band.

FIG. 7A is a top view showing the structure of a conventional FET, and FIG.
It is sectional drawing which shows the structure along the -B line. This is Ga
As Schottky gate field effect transistor (GaAs
s-MESFET).

An n-type active layer 2 is formed on a semiconductor substrate 1, and n ⁺ -type high-concentration impurity layers 3 and 4 are formed at both ends thereof. A gate electrode 5 is formed on the active layer 2 by Schottky contact, and a source electrode 6 and a drain electrode 7 are formed on the high-concentration impurity layers 3 and 4 by ohmic contact.

In the manufacturing process of such an FET, for example, when a pattern is formed on the semiconductor substrate 1 by an optical exposure technique, in order to maintain an alignment margin with respect to a previously formed pattern, The pattern formed subsequently may be formed larger by a dimension having a margin corresponding to the maximum misalignment of the exposure apparatus. Therefore, taking into account the minimum alignment margin required for the pattern formation, the high-concentration impurity layers 3 and 4 are formed partially larger than the active layer 2, and the gate electrode 5 is similarly formed with the active layer. 2, the source electrode 6 and the drain electrode 7 are partially larger than the high-concentration impurity layers 3 and 4, respectively. However, since this deviation is at most about 0.1 to 1 μm, it is a minute size that can be ignored sufficiently when compared with a commonly used gate width.

Hereinafter, the ohmic electrode means a source electrode or a drain electrode formed in ohmic contact with a high-concentration impurity layer. Similarly, the gate width W _G, to represent the length of the source electrode side edge portion or the drain electrode side edge portion and the active layer and the overlap portion of the gate electrode. Similarly, the contact width W
_C represents the length of the portion where the edge of the ohmic electrode on the gate electrode side overlaps the high-concentration impurity layer.

Accordingly, in the conventional FET, the gate width W _G and the contact width W _C is the degree to which a difference in the range of about the dimensions of the minimum required alignment margin in the pattern formation of the active layer and the high concentration impurity layer And are formed so as to substantially coincide with each other.

[0008]

In a mobile communication terminal and various devices constituting a mobile communication system, an FET applied to a power amplifier circuit, a high-frequency switch circuit for switching antenna transmission / reception, and the like is desired. ing. Since this power amplifier circuit occupies most of the power consumption in terminals and devices, reduction in power consumption, that is, higher efficiency is required. Further, the high-frequency switch circuit is required to have a small insertion loss. Therefore, it is necessary for the FETs applied to them to have a small resistance between the drain and the source in the ON state.

Here, the on-resistance R _ON is hereinafter referred to as an FET.
The series resistance _RD and the contact resistance R
The resistance between the drain and the source composed of _C is represented. This series resistance _RD is a resistance measured between the gate electrode and the ohmic electrode. The contact resistance _RC is a resistance measured at a junction between the ohmic electrode and the high-concentration impurity layer in contact with the ohmic electrode.

In the above-mentioned conventional FET, when the distance between the gate electrode and the ohmic electrode is reduced in order to reduce the series resistance _RD , the drain breakdown voltage is reduced. However, in the FET in the power amplifier circuit, in order to increase the output power, it is necessary to increase the drain withstand voltage by relaxing the electric field concentration at the edge of the drain electrode on the gate electrode side. Further, even in the FET in the high-frequency switch circuit, a high-power signal passes when connected to the transmission circuit side, so that it is necessary to similarly increase the drain breakdown voltage. Therefore, FE
In order to increase the breakdown voltage of T, the drain electrode cannot be arranged very close to the gate electrode.

Further, in the conventional FET, for most of the drain current flows to concentrate the gate electrode side edge portion of the ohmic electrode, the contact width W _C is determined by the contact width W _C. However, the contact width W _C is almost identical to the gate width W _G, the gate width W _G is predetermined by the requirements of the circuit design. Therefore, there is a problem that the contact width W _C cannot be increased more than necessary in order to reduce the contact resistance R _C.

For insights on the electric field concentration at the edge of the ohmic electrode on the gate electrode side, see "Williams. Ralph, Modern GaAs Processing Methods, c.
hap.11, Boston.London, Artech House Inc. ", etc.

The present invention has been made in view of the above problems, and it is an object of the present invention to reduce the contact resistance of an ohmic electrode without unnecessarily increasing the gate width determined according to a circuit design requirement. Accordingly, an object of the present invention is to provide a field-effect transistor that can reduce the resistance between the drain and the source in an on state and can be applied to a circuit that requires a high breakdown voltage as required.

[0014]

In order to achieve the above object, a field effect transistor according to the present invention has a semiconductor substrate, an active layer formed by doping impurities in a surface region of the semiconductor substrate, and an active layer. Two high-concentration impurity layers formed by doping impurities at both ends of the active layer, a gate electrode formed by Schottky contact on the active layer, and ohmic contacts on the two high-concentration impurity layers in the field effect transistor and a formed source and drain electrodes and the length W _C of the portion where the gate electrode side edge portion of the source electrode and the drain electrode and the high concentration impurity layers overlap, the gate electrode the source electrode side edge portion or the drain electrode side edge portion and the active layer and the overlap portion further than the length W _G, minimum patterning of the active layer and the high concentration impurity layer It is characterized in that it is larger than the size of the necessary alignment margin.

Here, the length W _C of the portion where the gate electrode side edge of the source or drain electrode overlaps with the high concentration impurity layer depends on the concentration of the current flowing in the gate electrode side edge of the source or drain electrode. It may be characterized in that it is sufficiently relaxed.

The length W _{A of the} portion where the edge of the source electrode or the drain electrode on the gate electrode side overlaps the active layer.
The source electrode side edge portion or the drain electrode side edge portion and the active layer and the overlap portions of the gate electrode further than the length W _G, the minimum required alignment margin in the pattern formation of the active layer and the high concentration impurity layer It may be characterized by being larger than the size.

In order to achieve the above object, a field effect transistor according to the present invention comprises: a semiconductor substrate; and an active layer formed by doping impurities in a surface region of the semiconductor substrate.
Two high-concentration impurity layers formed by doping impurities at both ends of the active layer, a gate electrode formed by Schottky contact on the active layer, and an ohmic contact formed on one of the two high-concentration impurity layers. A source electrode formed in contact therewith, and a drain electrode formed in ohmic contact with the other of the two high-concentration impurity layers, and the edge of the source electrode or the drain electrode on the gate electrode side and the high-concentration impurity layer are formed. the length W _C of the overlap is the source electrode side edge portion or the drain electrode side edge portion and the active layer and the overlap portions of the gate electrode relative to the length _{W G, 1 [μm] +} W G <W C <
Characterized in that it is set to satisfy the 5W _G.

Here, the length W of the portion where the edge of the source electrode or the drain electrode on the gate electrode side overlaps the active layer.
_A is the source electrode side edge portion or the drain electrode side edge portion and the active layer and the overlap portions of the gate electrode relative to the length _{W G, 1 [μm] +} W G < set to satisfy W _A <5W _G It may be characterized by being performed.

The active layer is divided into a plurality of parts at predetermined intervals along a direction in which the source electrode side edge or the drain electrode side edge of the gate electrode overlaps the active layer. It may be a feature.

The gate electrode may be arranged closer to the high-concentration impurity layer overlapping the source electrode than to the high-concentration impurity layer overlapping the drain electrode.

The active layer is formed by selectively implanting impurities into the semiconductor substrate, and the high-concentration impurity layer is formed by further selectively implanting impurities at both ends of the active layer. May be a feature.

The high-concentration impurity layer is formed by selectively injecting impurities into the semiconductor substrate, and the active layer is doped with the impurity on the high-concentration impurity layer, crystal-grown, and shaped into a mesa. It may be characterized in that element isolation is provided.

Further, the active layer and the high-concentration impurity layer may be characterized in that an impurity is added to the semiconductor substrate, the crystal is grown sequentially, and both are formed into a mesa shape, and element isolation is performed.

[0024]

In the field effect transistor of the present invention, the length W _C of the portion where the gate electrode side edge portion of the source electrode and the drain electrode and the high concentration impurity layers overlap is the source electrode side edge portion or the drain electrode of the gate electrode to length W _G determined by the requirements of the circuit design as a portion overlapping a side edge portion and the active layer, beyond the dimension of the minimum required alignment margin in the pattern formation of the active layer and the high concentration impurity layer, It is increasing at a predetermined rate. As a result, the drain current flowing through the gate electrode side edge of the source electrode or the drain electrode flows more dispersedly than before. That is, the concentration of the current flowing through the edge portion of the source electrode or the drain electrode on the gate electrode side is sufficiently relaxed. Therefore, the contact resistance of the source electrode or the drain electrode is reduced.

As a result, the resistance between the source and the drain in the on state is reduced to a desired value while having a high breakdown voltage structure in which the distance between the gate electrode and the source or drain electrode is maintained at a predetermined value. Therefore, by applying the field-effect transistor of the present invention, power consumption can be reduced in the power amplifier circuit, that is, power efficiency can be improved, and insertion loss can be reduced in the high-frequency switch circuit.

[0026] Here, the gate electrode side edge portion and the active layer and the overlap portion of the drain electrode length W _A is the source electrode side edge portion or the drain electrode side edge portion and the active layer and the overlap portion of the gate electrode to length W _G, beyond the dimension of the minimum required alignment margin, it is preferable that the larger a predetermined ratio. As a result, the drain current flowing through the gate electrode side edge of the source electrode or the drain electrode flows more dispersedly,
The contact resistance of the source or drain electrode is further reduced.

The active layer may be formed by dividing the gate electrode into a plurality of parts at a predetermined interval along a direction in which the source electrode side edge or the drain electrode side edge of the gate electrode overlaps the active layer. It is suitable. As a result, the drain current flowing through the gate electrode side edge of the source electrode or the drain electrode flows more uniformly in the direction of the gate width, so that the contact resistance of the source electrode or the drain electrode is further reduced.

Further, it is preferable that the gate electrode is arranged closer to the high concentration impurity layer overlapping the source electrode than to the high concentration impurity layer overlapping the drain electrode.
As a result, the series resistance between the gate electrode and the drain electrode increases, so that the drain withstand voltage improves.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction and operation of an embodiment according to the present invention will be described below with reference to FIGS. In addition,
In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. Also, the dimensional ratios in the drawings do not always match those described.

FIG. 1A is a top view showing the structure of a first embodiment according to the field effect transistor of the present invention. FIG.
FIG. 2B is a cross-sectional view illustrating a structure taken along line BB in FIG. In this embodiment, the GaAs-MESFE
The present invention is applied to T.

In a semiconductor substrate 1 made of GaAs, an n-type active layer 2 is formed by selectively ion-implanting donor impurities such as Si ions in a predetermined surface region. At both ends of the active layer 2, donor impurities such as Si ions are selectively ion-implanted to form n ⁺ -type high-concentration impurity layers 3 and 4.

On the active layer 2, Ti / P ₊ / Au
Is formed in Schottky contact. Further, on the high concentration impurity layers 3 and 4, AuG
A source electrode 6 and a drain electrode 7 made of e / Ni are formed in ohmic contact with each other.

The active layer 2 has a dopant concentration of about 2
× 10 ¹⁸ cm ^-3 and a layer thickness of about 0.01 μm.
The high concentration impurity layers 3 and 4 each have a dopant concentration of about 2
× 10 ¹⁷ cm ^-3 and a layer thickness of about 0.07 μm.
The gate electrode 5 has a gate length of about 0.7 μm and a gate width of about 2 μm.
It has a thickness of 00 μm and a layer thickness of about 1 μm. Source electrode 6
The drain electrode 7 has a layer thickness of about 0.1 μm. Note that the distance between the gate electrode 5 and the source electrode 6 is about 0.5 μm. The distance between the gate electrode 5 and the drain electrode 7 is about 2 μm.

[0034] In the FET, in response to the gate width W _G determined by requirements of the circuit design, the active layer 2 is formed. The active layer 2 consideration of the position alignment margin of the pattern formation with respect to the gate electrode 5 is formed larger than the partially active layer 2 along the direction of the gate width W _G.
Further, the above taking into account the alignment margin for the active layer 2, the high concentration impurity layers 3 and 4 are formed so as to protrude largely along the direction of the gate width W _G. Considering alignment margin for these high concentration impurity layers 3 and 4, larger than the respective source electrode 6 and drain electrode 7 along the direction of the gate width W _G partially high concentration impurity layers 3,4 Is formed.

[0035] In this way, the contact width W _C of the source electrode and the drain electrode is set so as to satisfy the _{1 [μm] + W G <} W C <5W G to the gate width W _G. Therefore, this F
In ET, the contact W between the source electrode and the drain electrode
_C is designed to be larger by a predetermined ratio with respect to the gate width W _G. This ratio, according to the device structure and manufacturing techniques for applying the present invention, taking into account the value of the contact resistance R _C per unit length in the direction of the gate width W _G of the ohmic electrode, a desired value of the on-resistance R _ON Determined accordingly. However, if the contact width W _C is not greater only about the size of the alignment margin needed for normal patterning than the gate width W _G, it will not be included in this embodiment.

Next, the operation of the first embodiment will be described.

[0037] In the FET, such that the contact width W _C is increased at a predetermined ratio with respect to the gate width W _G determined by requirements of the circuit design, the direction of the high concentration impurity layers 3 and 4 the gate width W _G The pattern is formed largely along the line. As a result, the drain current flowing through the edge portions of the source electrode 6 and the gate electrode 7 on the gate electrode side is dispersed and flows as compared with the related art, so that the contact resistance _RC of the ohmic electrode is reduced.

Therefore, the ON resistance R _ON is reduced to a desired value while having a high breakdown voltage structure in which the distance between the gate electrode 5 and the ohmic electrode is maintained at a predetermined value. Therefore, power consumption is reduced in the power amplifier circuit, that is, power efficiency is improved, and insertion loss is reduced in the high-frequency switch circuit.

In this FET, the layout design of the high-concentration impurity layers 3 and 4 and the ohmic electrodes corresponding to these layers is performed by changing the pattern of the etching mask while keeping the structure in the direction perpendicular to the surface of the semiconductor substrate as in the conventional case. To be realized. Therefore, according to the present invention, there is provided an FET which is applied as a high-performance FET operating in a microwave frequency band while maintaining the conventional manufacturing process technology.

FIG. 2A is a top view showing the structure of a second embodiment according to the field effect transistor of the present invention. FIG.
FIG. 2B is a cross-sectional view illustrating a structure taken along line BB in FIG. In this embodiment, the GaAs-MESFE
The present invention is applied to T.

Into the semiconductor substrate 1 made of GaAs, donor impurities such as Si ions are selectively ion-implanted into two predetermined surface regions, and an n ⁺ -type high-concentration impurity layer 3 is formed.
4 are formed. On this semiconductor substrate 1, an n-type active layer 2 to which donor impurities such as Si ions are added is formed by crystal growth. Further, the active layer 2 covers the high-concentration impurity layers 3 and 4 by etching and is formed into a mesa shape, and device isolation is performed.

On the active layer 2, Ti / P ₊ / Au
Is formed in Schottky contact. Further, on the high concentration impurity layers 3 and 4, AuG
A source electrode 6 and a drain electrode 7 made of e / Ni are formed in ohmic contact with each other.

The active layer 2 has a dopant concentration of about 2
× 10 ¹⁸ cm ^-3 and a layer thickness of about 0.01 μm.
The high concentration impurity layers 3 and 4 each have a dopant concentration of about 2
× 10 ¹⁷ cm ^-3 and a layer thickness of about 0.07 μm.
The gate electrode 5 has a gate length of about 0.7 μm and a gate width of about 2 μm.
It has a thickness of 00 μm and a layer thickness of about 1 μm. Source electrode 6
The drain electrode 7 has a layer thickness of about 0.1 μm. Note that the distance between the gate electrode 5 and the source electrode 6 is about 0.5 μm. The distance between the gate electrode 5 and the drain electrode 7 is about 2 μm.

[0044] In the FET, in response to the gate width W _G determined by requirements of the circuit design, the active layer 2 is formed. The active layer 2 consideration of the position alignment margin of the pattern formation with respect to the gate electrode 5 is formed larger than the partially active layer 2 along the direction of the gate width W _G.
Further, the above taking into account the alignment margin for the active layer 2, the high concentration impurity layers 3 and 4 are formed so as to protrude largely along the direction of the gate width W _G. Considering alignment margin for these high concentration impurity layers 3 and 4, larger than the respective source electrode 6 and drain electrode 7 along the direction of the gate width W _G partially high concentration impurity layers 3,4 Is formed.

[0045] In this way, the contact width W _C of the source electrode and the drain electrode is set so as to satisfy the _{1 [μm] + W G <} W C <5W G to the gate width W _G. Therefore, this F
In ET, the contact width W _C of the source electrode and the drain electrode is designed to be larger at a predetermined ratio with respect to the first embodiment and the same way the gate width W _G.

According to the above configuration, the present embodiment provides the first
It works almost the same as the embodiment.

FIG. 3A is a top view showing the structure of a third embodiment according to the field effect transistor of the present invention. FIG.
FIG. 3B is a cross-sectional view illustrating a structure taken along line BB in FIG. In this embodiment, GaAs having a structure often used for a high-output FET particularly required to have a high breakdown voltage is used.
-The present invention is applied to a MESFET.

In a semiconductor substrate 1 made of GaAs, an n-type active layer 2 is formed by selectively ion-implanting donor impurities such as Si ions in a predetermined surface region. At both ends of the active layer 2, donor impurities such as Si ions are selectively ion-implanted to form n ⁺ -type high-concentration impurity layers 3 and 4.

On the active layer 2, Ti / P ₊ / Au
Is formed in Schottky contact. Further, on the high concentration impurity layers 3 and 4, AuG
A source electrode 6 and a drain electrode 7 made of e / Ni are formed in ohmic contact with each other.

The active layer 2 has a dopant concentration of about 2
× 10 ¹⁸ cm ^-3 and a layer thickness of about 0.01 μm.
The high concentration impurity layers 3 and 4 each have a dopant concentration of about 2
× 10 ¹⁷ cm ^-3 and a layer thickness of about 0.07 μm.
The gate electrode 5 has a gate length of about 0.5 μm and a gate width of about 2 μm.
It has a thickness of 00 μm and a layer thickness of about 1 μm. Source electrode 6
The drain electrode 7 has a layer thickness of about 0.1 μm. Note that the distance between the gate electrode 5 and the source electrode 6 is about 0.5 μm. The distance between the gate electrode 5 and the drain electrode 7 is about 2 μm.

[0051] In the FET, in response to the gate width W _G determined by requirements of the circuit design, the active layer 2 is formed. However, the active layer 2 is formed so as to overlap larger than the gate width W _G to the gate electrode side edge portion of the drain electrode 7. The gate electrode 5 has a gate width W in consideration of a margin for pattern formation with respect to the active layer 2.
_G is partially formed larger than the active layer 2 along the direction of _G , and is higher than the high-concentration impurity layer 4 overlapping the drain electrode 7.
It is arranged close to the high-concentration impurity layer 3 overlapping the source electrode 6. Further, the above taking into account the alignment margin for the active layer 2, the high concentration impurity layer 3 is formed so as to protrude largely along the direction of the gate width W _G. On the other hand, considering the alignment margin for the active layer 2, the high concentration impurity layer 4 are partially larger along the direction of the gate width W _G. Considering alignment margin for these high concentration impurity layers 3 and 4, larger than the respective source electrode 6 and drain electrode 7 along the direction of the gate width W _G partially high concentration impurity layers 3,4 Is formed.

[0052] In this way, the contact width W _C of the source electrode and the drain electrode is set so as to satisfy the _{1 [μm] + W G <} W C <5W G to the gate width W _G. The length W _A of the portion where the gate electrode side edge portion of the drain electrode and the active layer are overlapped, are set so as to satisfy the _{1 [μm] + W G <} W A <5W G to the gate width W _G ing.

[0053] Therefore, in the FET, and the contact width W _C of the source and drain electrodes, the length W _A of the gate electrode side edge portion and the active layer and the overlap portion of the drain electrode, and the first embodiment is designed to be larger at a predetermined ratio relative to a similar manner the gate width W _G.

According to the above configuration, the present embodiment is different from the first embodiment.
It works almost the same as the embodiment. Further, in the FET, to the gate width W _G determined by requirements of the circuit design, the gate electrode side edge portion of the drain electrode 7 and the active layer 2
DOO length W _A of the portion overlapping so increases at a predetermined ratio, are partially large patterned active layer 2 along the direction of the gate width W _G. As a result, the drain current flowing through the gate electrode side edge of the drain electrode 7 flows more dispersedly than in the first embodiment, and the contact resistance _RC of the ohmic electrode is further reduced.

Further, the gate electrode 5 is disposed closer to the high-concentration impurity layer 3 overlapping the source electrode 6 than the high-concentration impurity layer 4 overlapping the drain electrode 7.
Since the series resistance _RD between the gate electrode 5 and the drain electrode 7 increases, the drain withstand voltage is improved.

In this embodiment, the active layer 2 is formed in the semiconductor substrate 1 by selective implantation of donor impurities. However, as in the case of the second embodiment, the active layer 2 may be formed into a mesa by crystal growth. The same operation and effect can be obtained.

In a normal FET, in order to maximize the mutual conductance gm, the high-concentration impurity layer 3 overlapping with the source electrode 6 is formed so as to extend to the alignment margin limit required for pattern formation. However,
If this alignment margin is secured to some extent, by forming the active layer 2 so as to overlap larger m than the gate width W _G to the gate electrode side edge portion of the source electrode 6, the ohmic electrode contact resistance R _C is It is even further reduced.

FIG. 4A is a top view showing the structure of a fourth embodiment according to the field effect transistor of the present invention. FIG.
FIG. 4B is a cross-sectional view illustrating a structure taken along line BB in FIG. In this embodiment, the GaAs-MESFE
The present invention is applied to T.

On a semiconductor substrate 1 made of GaAs, S
n-type active layer 2 doped with donor impurities such as i-ions
And n further doped with donor impurities such as Si ions.
⁺ -Type high-concentration impurity layers 3 and 4 are sequentially formed by crystal growth. The active layer 2 and the high-concentration impurity layers 3 and 4 are formed in a mesa shape by etching, and are subjected to device isolation. Furthermore, the high-concentration impurity layers 3 and 4 are separated by forming a groove exposing the active layer 2 by etching.

Active layer 2 exposed by this recess structure
On top, a gate electrode 5 made of Ti / P ₊ / Au is formed in Schottky contact. A source electrode 6 made of AuGe / Ni is formed on the high concentration impurity layers 3 and 4.
And the drain electrode 7 are formed in ohmic contact with each other.

The active layer 2 has a dopant concentration of about 2
× 10 ¹⁸ cm ^-3 and a layer thickness of about 0.01 μm.
The high concentration impurity layers 3 and 4 each have a dopant concentration of about 2
× 10 ¹⁷ cm ^-3 and a layer thickness of about 0.07 μm.
The gate electrode 5 has a gate length of about 0.7 μm and a gate width of about 2 μm.
It has a thickness of 00 μm and a layer thickness of about 1 μm. Source electrode 6
The drain electrode 7 has a layer thickness of about 0.1 μm. Note that the distance between the gate electrode 5 and the source electrode 6 is about 0.5 μm. The distance between the gate electrode 5 and the drain electrode 7 is about 1 μm.

[0062] In the FET, in response to the gate width W _G determined by requirements of the circuit design, the active layer 2 is formed. However, the active layer 2 is formed so as to overlap larger than the gate width L _GT to the gate electrode side edge portion of the source electrode 6 and drain electrode 7. The active layer 2 consideration of the position alignment margin of the pattern formation with respect to the gate electrode 5 is formed larger than the partially active layer 2 along the direction of the gate width W _G. In consideration of the alignment margin for the active layer 2, the high concentration impurity layers 3 and 4 are partially larger along the direction of the gate width W _G respectively. Considering alignment margin for these high concentration impurity layers 3 and 4, larger than the respective source electrode 6 and drain electrode 7 along the direction of the gate width W _G partially high concentration impurity layers 3,4 Is formed.

[0063] In this way, the contact width W _C of the source electrode and the drain electrode is set so as to satisfy the _{1 [μm] + W G <} W C <5W G to the gate width W _G. The length W _A of the portion where the gate electrode side edge portions of the source and drain electrodes and the active layer overlap, one for the gate width _{W G [μm] + W G} < to satisfy W _A <5W _G Is set to

Therefore, in this FET, the contact width W _C of the source electrode and the drain electrode and the length W _{A of the} portion where the edge of the source electrode and the drain electrode on the gate electrode side overlaps with the active layer are equal to the first width. is designed to be larger by a predetermined ratio with respect to embodiments and the same way the gate width W _G.

According to the above configuration, the present embodiment is different from the first embodiment.
It works almost the same as the embodiment. Further, in the FET, to the gate width W _G determined by requirements of the circuit design, the length W _A of the portion where the gate electrode side edge portion of the source electrode 6 and drain electrode 7 and the active layer 2 overlap is given so as to increase in proportion, it is partially large patterned active layer 2 along the direction of the gate width W _G. As a result, the drain current flowing through the gate electrode side edge of the ohmic electrode flows more dispersedly than in the first embodiment.
_C is further reduced.

In this embodiment, the active layer 2 and the high-concentration impurity layers 3 and 4 are crystal-grown on the semiconductor substrate 1 and are formed in a mesa shape. Can be obtained in the semiconductor substrate 1 by selective implantation.

FIG. 5A is a top view showing the structure of a fifth embodiment according to the field effect transistor of the present invention. FIG.
FIG. 5B is a cross-sectional view illustrating a structure taken along line BB in FIG. In this embodiment, the GaAs-MESFE
The present invention is applied to T, and can be applied to any of the structures of the above embodiments.

[0068] a semiconductor substrate 1 made of GaAs is selectively ion-implanted donor impurity such as Si ions in a predetermined surface area of the plurality of positions, n-type active layer 2 ₁ to 2 ₄ is formed. A plurality of active layers ₂₁ to ₂₄ along the direction of the gate width W _G being arranged by dividing at predetermined intervals. At both ends of these active layers ₂₁ to _24, further selective ion implantation of donor impurities such as Si ions, n
⁺ Type high concentration impurity layers 3 and 4 are formed.

[0069] Further, on the active layer 2 ₁ to 2 _4, Ti / P
₊ / Au gate electrode 5 is formed in Schottky contact. Further, a source electrode 6 and a drain electrode 7 made of AuGe / Ni are formed on the high-concentration impurity layers 3 and 4 in ohmic contact, respectively.

[0070] Here, the active layer ₂₁ to ₂₄ has a dopant concentration of about 2 × 10 ¹⁸ cm ^-3 and a layer thickness of about 1 [mu] m. Each of the high-concentration impurity layers 3 and 4 has a dopant concentration of about 2 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.07 μm. The gate electrode 5 has a gate length of about 0.5 μm, a gate width of about 200 μm, and a layer thickness of about 1 μm. Each of the source electrode 6 and the drain electrode 7 has a layer thickness of about 0.1 μm.
have. The distance between the active layers ₂₁ to ₂₄ is about 20 [mu] m. The distance between the gate electrode 5 and the source electrode 6 is about 0.5 μm. The distance between the gate electrode 5 and the drain electrode 7 is about 2 μm.

[0071] In the FET, in response to the gate width W _G determined by requirements of the circuit design, the active layer ₂₁ to ₂₄ are formed. However, the gate width W _G determined by requirements of the circuit design is consistent with the sum of the gate width W _G1 to _W-G4 corresponding to the active layer _{2 1 ~2 4 (W G1 +} W G2 + W G3 + W G4). Considering the alignment margin of the pattern formation for these active layers ₂₁ to _24, the gate electrode 5 is formed larger than partially the active layers ₂₁ to ₂₄ along the direction of the gate width W _G Have been. These active layers 2 ₁ to 2
Than considering the alignment margin for _4, high concentration impurity layers 3 and 4 each active layer along the direction of the gate width W _G 2
It is formed so as to protrude greater than ₂₁ to _24.
Considering alignment margin for these high concentration impurity layers 3 and 4, larger than the respective source electrode 6 and drain electrode 7 along the direction of the gate width W _G partially high concentration impurity layers 3,4 Is formed.

[0072] In this way, the contact width W _C of the source electrode and the drain electrode is set so as to satisfy the _{1 [μm] + W G <} W C <5W G to the gate width W _G. Therefore, this F
In ET, the contact width W _C of the source electrode and the drain electrode is designed to be larger at a predetermined ratio with respect to the first embodiment and the same way the gate width W _G.

According to the above configuration, the present embodiment provides the first
It works almost the same as the embodiment. Further, a plurality of active layers ₂₁ to ₂₄ are arranged being divided along the direction of the gate width W _G. Accordingly, the drain current flowing through the gate electrode side edge portion of the ohmic electrode, so will flow more evenly to face the direction of the gate width W _G than the first embodiment, the contact resistance of the ohmic electrodes R
_C is further reduced.

In this embodiment, the active layer 2 _N is formed in the semiconductor substrate 1 by selective implantation of donor impurities. However, as in the second embodiment, the active layer 2 _N is crystal-grown and shaped into a mesa. The same operation and effect can be obtained. Here, N is an arbitrary natural number.

Further, in this embodiment, when the present invention is applied to an integrated circuit, the dimensions of the plurality of active layers 2 _N are different due to restrictions on layout design, or the source electrode 6 or the drain electrode 7 is different from the active layer 2 _N. Even if the shapes of the overlapping active layers 2 _N are different, the same function and effect can be obtained.

FIG. 6 is a graph showing the relationship between the ratio of the contact width to the gate width and the contact resistance in the above embodiments of the field effect transistor of the present invention. In general, in the above embodiments, the contact resistance R _C of the ohmic electrode is represented by the following equation with respect to the contact width W _C.

R _C = (r _C · R _SC / W _C ) ^1/2 where r _C is the specific resistance [Ω · cm] of the junction between the ohmic electrode and the high concentration impurity layer, and R _SC is the ohmic The sheet resistance [Ω] of the high-concentration impurity layer to be bonded to the electrode is given, and W _C is the contact width [cm].

Normally, the specific resistance r _C and the sheet resistance R _SC can take the following values.

[0079] ^{_{r C = 0.8 × 10 -6 ~4}} × 10 -6 Ω · cm, where R _SC = 100 to 200, when the gate width W _G is a constant, the contact resistance R _C is the gate width W _G the ratio of the contact width W _C for the W _C
It is expressed as shown in the following expression for / W _G.

R _C = C ₀ · (W _C / W _G ) ^-1/2 where C ₀ is a proportional constant [Ω].

When the value of the contact resistance R _C corresponding to the range of 1 ≦ W _C / W _G ≦ 10 is plotted based on this equation, a graph shown in FIG. 6 is obtained. Note that W _C / W _G =
The contact resistance R _C is normalized by setting C ₀ = 1 so that R _C = 1 with respect to 1.

According to this graph, when W _C / W _G ≧ 5, the contact resistance R _C is 以下 or less as compared with the case where W _C / W _G = 1, but W _C / W _G. Shows a tendency to saturate with an increase in the value of. At this time, since the size of the semiconductor chip FET is formed becomes excessive, it can not be obtained practical gate width W _G and the contact width W _C. Therefore, the contact width W _C is it is preferred that less than 5 times the gate width W _G. However, it is desirable that the value of W _C / W _G be as large as possible within the allowable range of the chip size.

[0083] On the other hand, when the value of W _C / W _G is approximate to 1, the contact resistance R _C is a tendency to rapidly reduced with increasing values of W _C / W _G. However,
The difference between the contact width W _C and the gate width W _G (W _C -W _G)
Is less than the normal alignment margin at the time of exposure, that is, the range of 0.1 to 1 μm or less, the contact resistance _RC becomes W
_C = W only been slightly reduced in comparison with the case of _G.
Therefore, 1 [mu] Contacts width W _C is than the gate width W _G
Preferably, it is larger than m.

[0084] Thus, in the above various embodiments, the contact width W _C is found that it is preferable to satisfy the _{1 [μm] + W G <} W C <5W G to the gate width W _G. Note that, regarding the above-described equation representing the contact resistance _RC , refer to the document "Ralph E. williams, Gallium Arsenide Processing Tec".
hniques, chap. 11, Artech house Inc., 1984 "and the like.

The present invention is not limited to the above embodiments, and various modifications are possible.

[0086] For example, in the above various embodiments, although larger than the gate contact width W _C of the two ohmic electrode width W _G, constraints on layout design in a case of applying the present invention for the integrated circuit , even larger than the gate width W _G of the contact width W _C only one of a source electrode and a drain electrode, the same effects can be obtained.

[0087]

As described in detail above, in the field-effect transistor of the present invention, the length of the portion where the edge of the source or drain electrode on the gate electrode side overlaps with the high concentration impurity layer is equal to the length of the gate electrode. The minimum margin required for pattern formation of the active layer and high-concentration impurity layer with respect to the length determined by the circuit design requirement at the portion where the active layer overlaps the source electrode side edge or drain electrode side edge Exceeds the size of the above, and increases at a predetermined rate. Therefore, the drain current flowing through the gate electrode side edge of the source electrode or the drain electrode flows more dispersedly than in the conventional case, and the contact resistance of the source electrode or the drain electrode is reduced.

As a result, the resistance between the source and the drain in the ON state is reduced to a desired value while having a high breakdown voltage structure in which the distance between the gate electrode and the source or drain electrode is maintained at a predetermined value. Therefore, by applying the field-effect transistor of the present invention, power consumption can be reduced in the power amplifier circuit, that is, power efficiency can be improved, and insertion loss can be reduced in the high-frequency switch circuit.

As a result, the present invention provides a high-concentration impurity layer and a corresponding ohmic electrode or an active layer and a high-concentration impurity layer by changing the pattern of the etching mask while maintaining the structure in the direction perpendicular to the surface of the semiconductor substrate as in the prior art. This can be realized by changing the layout design of the gate electrode corresponding to. Therefore, according to the present invention, there is obtained an effect that a high-performance field-effect transistor that operates in a microwave frequency band is provided while maintaining the conventional manufacturing process technology.

[Brief description of the drawings]

FIG. 1A is a top view showing a structure of a first embodiment according to a field effect transistor of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a structure taken along line BB in FIG.

FIG. 2A is a top view showing a structure of a second embodiment according to the field effect transistor of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a structure taken along line BB in FIG.

FIG. 3A is a top view showing a structure of a third embodiment according to the field effect transistor of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a structure taken along line BB in FIG.

FIG. 4A is a top view showing the structure of a fourth embodiment according to the field effect transistor of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a structure taken along line BB in FIG.

FIG. 5A is a top view showing the structure of a fifth embodiment according to the field effect transistor of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a structure taken along line BB in FIG.

FIG. 6 is a graph showing the relationship between the ratio of the contact width to the gate width and the contact resistance in the above-mentioned embodiments of the field-effect transistor of the present invention.

FIG. 7A is a top view showing a structure of a conventional field-effect transistor, and FIG.
It is sectional drawing which shows the structure along the B line.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Active layer, 3,4 ... High concentration impurity layer, 5 ... Gate electrode, 6 ... Source electrode, 7 ... Drain electrode.

Claims (7)

(57) [Claims] A semiconductor substrate formed by doping impurities in a surface region of the semiconductor substrate;
The active layer, and each doped with the impurity to both ends of the active layer
Two high-concentration impurity layers formed and a gate formed in Schottky contact on the active layer
Ohmic contact with the electrode and one of the two high-concentration impurity layers
The formed source electrode is in ohmic contact with the other of the two high-concentration impurity layers.
A drain electrode formed, and the gate electrode of the source electrode or the drain electrode.
Length of the portion where the pole side edge portion and the high concentration impurity layer overlap
W _C is the source electrode side edge of the gate electrode or
Indicates a portion where the edge portion on the drain electrode side overlaps with the active layer
The relative length _{W G, 1 [μm] +} W G <W C < field, characterized in that it is set to satisfy the 5W _G
Effect transistor. 2. The source electrode or the drain electrode
Of the portion where the gate electrode side edge portion and the active layer overlap
The length W _A, the relative length _{W G, 1 [μm] +} W G <W A < claims, characterized in that it is set to satisfy the 5W _G
Item 2. The field effect transistor according to Item 1. 3. The method according to claim 1, wherein the active layer is a source of the gate electrode.
The edge on the electrode side or the edge on the drain electrode side
At predetermined intervals along the direction of the area where the conductive layer overlaps
2. The device according to claim 1, wherein the components are divided and arranged.
Field effect transistor. 4. The gate electrode is connected to the drain electrode.
The source electrode is heavier than the high concentration impurity layer that overlaps.
That is disposed close to the high-concentration impurity layer.
The field effect transistor according to claim 1, wherein: 5. The semiconductor device according to claim 5, wherein said active layer is provided on said semiconductor substrate.
The high-concentration impurities
The material layer further selectively covers the impurities at both ends of the active layer.
2. The method according to claim 1, wherein
A field-effect transistor according to claim 1. 6. The semiconductor device according to claim 1, wherein said high-concentration impurity layer is formed on said semiconductor substrate.
The impurity is formed by selectively implanting the impurity,
The conductive layer is formed by adding the impurity on the high-concentration impurity layer.
The crystal is grown and shaped into a mesa, and the elements are separated.
The field effect transformer according to claim 1, wherein
Jista. 7. The active layer and the high concentration impurity layer,
Crystal growth by adding the impurities on the semiconductor substrate sequentially
And molded together in a mesa shape,
2. The field effect transistor according to claim 1, wherein
Star.