JP3407264B2 - Single electron transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-electron transistor. Conventionally, a single-electron transistor described below with reference to FIG. 2 has been proposed. That is, there is provided a compound semiconductor laminate 1 in which a two-dimensional electron gas layer 6 extending along a plane perpendicular to the laminating direction is formed. In this case, the compound semiconductor laminate 1 is
(A) a compound semiconductor substrate or layer 2 into which neither an impurity imparting n-type or an impurity imparting p-type is intentionally introduced, and (b) a lower end of a conduction band higher than the compound semiconductor substrate or layer 2 Or n-type impurity or p
A compound semiconductor layer 3 which does not intentionally introduce any of the type-imparting impurities and has a relatively thin thickness, and (c) a lower end of a conduction band higher than that of the compound semiconductor substrate or layer 2 and which is n-type. And the compound semiconductor layer 4 having a relatively small thickness forms a heterojunction 5 between the compound semiconductor substrate or the layer 2 and the compound semiconductor layer 3 and has a relatively small thickness. 2 on the heterojunction 5 side of
It may have a configuration in which the three-dimensional electron gas layer 6 is stacked in that order so as to form the three-dimensional electron gas layer 6. Further, a source electrode 7S and a drain electrode 7D (not shown in FIG. 2B) are provided on the compound semiconductor laminate 1 so as to be in contact with the two-dimensional electron gas layer 6. In this case, the source electrode 7S and the drain electrode 7D extend on the compound semiconductor laminate 1 to a depth where the material of the source electrode 7S and the drain electrode 7D terminates in the compound semiconductor substrate or the layer 2. May be attached as follows. Further, the source-side two-dimensional electron gas region 10S on the source electrode 7D side and the drain side 2 on the drain electrode 7D side are formed on the compound semiconductor laminate 1 from the two-dimensional electron gas layer 6.
The two-dimensional electron gas region 10D and the dot-shaped two-dimensional electron gas region 10T between the source-side two-dimensional electron gas region 10S and the drain-side two-dimensional electron gas region 10D are formed or formed so as to be formed by the depletion layer 11. 2
Two-dimensional electron gas region forming means 12. In this case, the two-dimensional electron gas region forming means 1
Reference numeral 2 denotes a Schottky electrode 1 formed on the compound semiconductor laminate 1 so as to form a Schottky junction between the compound semiconductor laminate 1 and a depletion layer extending into the compound semiconductor laminate 1.
3 and the free end of the Schottky electrode 13 on the source electrode 7S side so as to form a Schottky junction between the compound semiconductor stack 1 and the depletion layer extending into the compound semiconductor stack 1 between the compound semiconductor stack 1 and the compound semiconductor stack 1. The free ends of the Schottky electrode 14 are extended so as to face each other, and a Schottky junction is formed between the Schottky electrode 14 and the compound semiconductor laminate 1 to form a depletion layer extending into the compound semiconductor laminate 1. A Schottky electrode 15 extending so as to face an end of the electrode 13 on the drain electrode 7D side, and a Schottky junction between the compound semiconductor laminate 1 and a depletion layer extending in the compound semiconductor laminate 1 between the Schottky electrode 15 and the Schottky electrode 15. And a Schottky electrode 16 extending so that the free end is opposed to the end of the Schottky electrode 13 on the side of the source electrode 7S. In the compound semiconductor laminate 1, the number of electrons in the dot-like two-dimensional electron gas region 10T is controlled by a depletion layer, so that a single electron is generated between the source electrode 7S and the drain electrode 7D on the source side in two dimensions. Electron gas region 10S, depletion layer 11 of two-dimensional electron gas region forming means 12
Source-side tunnel barrier 1 formed between the source-side two-dimensional electron gas region 10S and the dot-shaped two-dimensional electron gas region 10T of FIG.
8S, a dot-shaped two-dimensional electron gas region 10T, a drain-side tunnel barrier 18D composed of a dot-shaped two-dimensional electron gas region 10T of the depletion layer 11 of the depletion layer 11 of the two-dimensional electron gas region forming means 12 and a drain-side two-dimensional electron gas region 10D. And a single electron transfer control means 17 provided to control movement through the two-dimensional drain-side electron gas region 10D. In this case, the single electron transfer control means 17 has the Schottky electrode 16 which constitutes the two-dimensional electron gas region forming means 12 described above. The above is the configuration of the conventionally proposed single-electron transistor. According to the conventional single-electron transistor having such a structure, between the Schottky electrode 13 and the source electrode 7S of the two-dimensional electron gas region forming means 12, the Schottky electrode 1 of the two-dimensional electron gas region forming means 12 is provided.
4 and the source electrode 7S, the Schottky electrode 15 and the source electrode 7S of the two-dimensional electron gas region forming means 12
The above-described source-side two-dimensional electron gas can be applied between the Schottky electrode 16 and the source electrode 7S of the two-dimensional electron gas region forming means 12 with or without applying a required bias voltage. Area 10S,
The two-dimensional electron gas region 10D on the drain side and the two-dimensional electron gas region 10S between the source side two-dimensional electron gas region 10S and the two-dimensional electron gas region on the drain side 10D
T is formed or formed. From such a state, if a control voltage is applied between the Schottky electrode 16 and the source electrode 7S of the single electron mobility control means 17 (when applied to the above-mentioned bias voltage, it is superimposed on it). Then, by controlling the spread of the depletion layer from the Schottky junction of the Schottky electrode 16 according to the control voltage, the size of the dot-shaped two-dimensional electron gas region 10T is controlled. The number of electrons in the two-dimensional electron gas region 10T is controlled. As described above, the conventional single-electron transistor shown in FIG. 2 has a function as a single-electron transistor. [0015] In the case of the conventional single-electron transistor shown in FIG.
0S, the two-dimensional electron gas region forming means 12 which forms or forms the drain-side two-dimensional electron gas region 10D and the dot-shaped two-dimensional electron gas region 10T is composed of four Schottky electrodes 13, 14, 15, and 16 in many cases. , The source-side two-dimensional electron gas region 10S and the drain-side two-dimensional electron gas region 1S.
The formation or formation of the two-dimensional electron gas region 10T is difficult. This is even more so if the dot-shaped two-dimensional electron gas region 10T is to be formed finely or formed in order to obtain the function as a single-electron transistor with high efficiency. Further, the Schottky electrode 13 and the Schottky electrode 1 constituting the two-dimensional electron gas region forming means 12 are formed.
4, a source-side two-dimensional electron gas region 10S of the depletion layer 11 and a dot-shaped two-dimensional electron gas are adjusted by applying a bias voltage between one or both of them and the source electrode 7S. The length of the source-side tunnel barrier 18S between the regions 10T, that is, the transmittance of electrons passing through the source-side tunnel barrier 18S, can be controlled.
A bias voltage is applied between one or both of the Schottky electrode 13 and the Schottky electrode 15 and the source electrode 7S, and if the bias voltage is adjusted, the two-dimensional drain side of the depletion layer 11 can be adjusted. The length of the drain-side tunnel barrier 18D formed between the electron gas region 10D and the dot-shaped two-dimensional electron gas region 10T, that is, the transmittance of electrons passing through the drain-side tunnel barrier 18D can be controlled. Then, the size of the dot-shaped two-dimensional electron gas region 10T, that is, the number of electrons in the dot-shaped two-dimensional electron gas region 10T is changed relatively large, and the Schottky electrode constituting the single electron transfer control means 17 is changed. The size of the dot-shaped two-dimensional electron gas region 10T, and therefore the dot-shaped secondary If the number of electrons in the electron gas region 10T is controlled, the lengths of both the source-side tunnel barrier 10S and the drain-side tunnel barrier 10D described above are changed relatively large, so that the function as a single-electron transistor is expected. However, there is a drawback that the function cannot be easily obtained. Thus, the present invention is free of the above-mentioned disadvantages,
It proposes a new single-electron transistor. The single-electron transistor according to the present invention has the same structure as that of the conventional single-electron transistor shown in FIG. 2, (i) extending inside along a plane orthogonal to the laminating direction. A compound semiconductor laminate forming a two-dimensional electron gas layer, and (ii) the compound semiconductor laminate,
A source electrode and a drain electrode provided to be in contact with the two-dimensional electron gas layer; and (iii) a source-side two-dimensional electron gas on the source electrode side from the two-dimensional electron gas layer on the compound semiconductor laminate. Region, the drain-side two-dimensional electron gas region on the drain electrode side, and the source side 2
A two-dimensional electron gas region forming means which forms or is provided so as to form a two-dimensional electron gas region and a dot-like two-dimensional electron gas region between the drain-side two-dimensional electron gas region by a depletion layer; In the compound semiconductor laminate, the number of electrons in the dot-shaped two-dimensional electron gas region is controlled by a depletion layer, whereby a single electron is generated between the source electrode and the drain electrode in the source-side two-dimensional electron gas region. A source-side tunnel barrier between the source-side two-dimensional electron gas region and the dot-shaped two-dimensional electron gas region of the depletion layer of the two-dimensional electron gas region forming means; the dot-shaped two-dimensional electron gas region; A drain-side tunnel formed between the dot-shaped two-dimensional electron gas region and the drain-side two-dimensional electron gas region of the depletion layer of the electron gas region forming means; Walls, and having a single electron transfer control means provided to control the movement via the drain-side two-dimensional electron gas region. However, the single-electron transistor according to the present invention is the same as the single-electron transistor having the above-mentioned structure, except that (v) the two-dimensional electron gas region forming means is:
In the compound semiconductor laminate, first to linear and band-like extending extending so as to sandwich a contact region of the two-dimensional electron gas layer with the source electrode and the drain electrode when viewed from above in the compound semiconductor laminate. The first and second lines or bands formed by the first and second ion-implanted regions, respectively, so that the second depletion layer is formed respectively.
A depletion layer forming region, and the compound semiconductor laminate, extending from above, both across the first and second depletion layer forming regions as viewed from above and between the compound semiconductor laminate. A plurality of Schottky electrodes formed so as to form a plurality of Schottky junctions respectively forming a plurality of depletion layers extending in the body,
In addition, the single electron transfer control means may be provided on the compound semiconductor laminate between the two-dimensional electron gas layer and the first depletion layer formation region when viewed from above, when viewed from above. A first control electrode provided so as to be in contact with a region opposite to the region side, and the two-dimensional electron gas layer and the second depletion layer forming region, as viewed from above, on the compound semiconductor laminate. It has one or both of a second control electrode provided so as to be in contact with the region opposite to the region between the first and second depletion layer formation regions. According to the single electron transistor of the present invention, the source-side two-dimensional electron gas region is formed by the two-dimensional electron gas region forming means in the same manner as in the case of the conventional single electron transistor described above with reference to FIG. , A drain-side two-dimensional electron gas region, and a dot-like two-dimensional electron gas region between the source-side two-dimensional electron gas region and the drain-side two-dimensional electron gas region. From such a state, the size of the dot-shaped two-dimensional electron gas region is controlled by the single electron mobility control means, as in the case of the conventional single electron transistor described above with reference to FIG. The number of electrons in the dot-shaped two-dimensional electron gas region is controlled. As described above, according to the single-electron transistor of the present invention, it functions as a single-electron transistor as in the case of the conventional single-electron transistor described above with reference to FIG. However, in the case of the single-electron transistor according to the present invention, the two-dimensional electron gas region forming or forming the source-side two-dimensional electron gas region, the drain-side two-dimensional electron gas region, and the dot-shaped two-dimensional electron gas region. Since the forming means includes the first and second depletion layer forming regions and the plurality of Schottky electrodes, the source-side two-dimensional electron gas region, the drain-side two-dimensional electron gas region, and the dot-shaped two-dimensional electron gas region Is easier to form than in the conventional single-electron transistor shown in FIG. Therefore, in order to obtain the function as a single-electron transistor with high efficiency, the dot-shaped two-dimensional electron gas region can be formed more minutely. If a bias voltage is applied between the one Schottky electrode and the source electrode constituting the two-dimensional electron gas region forming means 12, and the bias voltage is adjusted, the one Schottky electrode Controls the length of the source-side tunnel barrier between the source-side two-dimensional electron gas region and the dot-shaped two-dimensional electron gas region, which is the depletion layer extending from the Schottky junction, and thus the transmittance of electrons passing through the source-side tunnel barrier. If a bias voltage is applied between the other Schottky electrode and the source electrode and the bias voltage is adjusted, the drain side 2 of the depletion layer extending from the Schottky junction of the other Schottky electrode can be adjusted. The length of the drain-side tunnel barrier between the two-dimensional electron gas region and the dot-shaped two-dimensional electron gas region,
Accordingly, the transmittance of electrons passing through the drain-side tunnel barrier can be controlled, and in this case, the size of the dot-shaped two-dimensional electron gas region, and thus the number of electrons in the dot-shaped two-dimensional electron gas region, is changed. Even so, the change is much smaller than in the case of the conventional single-electron transistor described above with reference to FIG. 2, and the change between the control electrode and the source electrode constituting the single-electron transfer control means. Even if the control voltage controls the size of the dot-shaped two-dimensional electron gas region, that is, the number of electrons in the dot-shaped two-dimensional electron gas region, the length of both the source-side tunnel barrier and the drain-side tunnel barrier described above is increased. There is no substantial change, so that the function as the single-electron transistor can be easily obtained with the intended function as compared with the conventional single-electron transistor described above with reference to FIG. It can be. Next, an embodiment of a single-electron transistor according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are denoted by the same reference numerals. That is, as in the case of the conventional single-electron transistor described above with reference to FIG. 2, the compound semiconductor stacked structure in which the two-dimensional electron gas layer 6 extending along the plane orthogonal to the stacking direction is formed. It has a body 1. In this case, the compound semiconductor laminate 1 is formed as shown in FIG.
As in the case of the conventional single-electron transistor described above,
(A) a compound semiconductor substrate or layer 2 into which neither an impurity imparting n-type or an impurity imparting p-type is intentionally introduced, and (b) a lower end of a conduction band higher than the compound semiconductor substrate or layer 2 Or n-type impurity or p
A compound semiconductor layer 3 which does not intentionally introduce any of the type-imparting impurities and has a relatively thin thickness, and (c) a lower end of a conduction band higher than that of the compound semiconductor substrate or layer 2 and which is n-type. And the compound semiconductor layer 4 having a relatively small thickness forms a heterojunction 5 between the compound semiconductor substrate or the layer 2 and the compound semiconductor layer 3 and has a relatively small thickness. 2 on the heterojunction 5 side of
It may have a configuration in which the three-dimensional electron gas layer 6 is stacked in that order so as to form the three-dimensional electron gas layer 6. Further, as in the case of the conventional single-electron transistor described above with reference to FIG.
It has a source electrode 7S and a drain electrode 7D (not shown in FIG. 1B) provided to be in contact with the two-dimensional electron gas layer 6. In this case, the material of the source electrode 7S and the material of the drain electrode 7D are formed on the compound semiconductor laminate 1 in the same manner as in the case of the conventional single-electron transistor described above with reference to FIG. It may be provided to extend to a depth ending in the compound semiconductor substrate or layer 2. Further, according to the conventional single-electron transistor described above with reference to FIG.
From the three-dimensional electron gas layer 6, a source-side two-dimensional electron gas region 10S on the source electrode 7D side, a drain-side two-dimensional electron gas region 10D on the drain electrode 7D side, a source-side two-dimensional electron gas region 10S, and a drain-side two-dimensional electron gas region And a two-dimensional electron gas region forming means 12 formed or provided so as to form a dot-shaped two-dimensional electron gas region 10T between 10D by the depletion layer 11. In this case, the two-dimensional electron gas region forming means 1
2 denotes a source electrode 7 of the two-dimensional electron gas layer 6 in the compound semiconductor laminate 1 as viewed from above in the compound semiconductor laminate 1.
The first and second ion-implanted regions 20 are formed such that linear or band-shaped first and second depletion layers 21 and 24 extending so as to sandwich the contact region with the S and the drain electrode 7D are respectively formed. And 23 are formed by the first and second depletion layer forming regions 22 and 2 in the form of a line or a band.
5 and the first and second depletion layer formation regions 22 and 25 both extending from above and above the compound semiconductor laminate 1 and between the compound semiconductor laminate 1 and the compound semiconductor laminate 1. A plurality of, for example, two Schottky electrodes 26 and 2 formed to form a plurality of Schottky junctions respectively forming a plurality of depletion layers extending to
And 7. In addition, the single electron transfer control means 17 forms the first and second depletion layer forming regions 22 and 22 on the compound semiconductor laminate 1 as viewed from above, from the two-dimensional electron gas layer 6 and the first depletion layer forming region 21. The first control electrode 29A provided so as to be in contact with a region 28A opposite to the region between the first and second regions 25, and the compound semiconductor laminate 1, the two-dimensional electron gas layer 6 and the second Depletion layer forming region 2
5, the first and second depletion layer forming regions 22 and 25
One or both (in the figure, both) of the second control electrode 29B provided so as to be in contact with the region 28B opposite to the region between the two. The above is the configuration of the embodiment of the single-electron transistor according to the present invention. According to the single electron transistor of the present invention having such a configuration, the Schottky electrode 26 and the source electrode 7S of the two-dimensional electron gas region forming means 12 are provided.
The above-described source-side two-dimensional electron gas region can be applied if a predetermined bias voltage is applied between the Schottky electrode 27 and the source electrode 7S included in the two-dimensional electron gas region forming means 12 or if there is no bias voltage. 10S, a drain-side two-dimensional electron gas region 10D, and a dot-shaped two-dimensional electron gas region 10T between the source-side two-dimensional electron gas region 10S and the drain side 10D are formed or formed. From such a state, any one of the position between the first control electrode 29A and the source electrode 7S and the position between the second control electrode 29B and the source electrode 7S of the single electron mobility control means 17 is determined. When a control voltage is applied to one or both of them, the expansion of the depletion layer 20 in the depletion layer formation region 22 and the expansion of the depletion layer 24 in the depletion layer formation region 25 are controlled in accordance with the control voltage. ,
The size of the dot-shaped two-dimensional electron gas region 10T is controlled, and therefore, the number of electrons in the dot-shaped two-dimensional electron gas region 10T is controlled. As described above, the single electron transistor according to the present invention shown in FIG. 1 also functions as a single electron transistor like the conventional single electron transistor shown in FIG. However, in the case of the single-electron transistor according to the present invention shown in FIG. 1, the source-side two-dimensional electron gas region 10S, the drain-side two-dimensional electron gas region 10D, and the dot-shaped two-dimensional electron gas region 10T are formed. Since the two-dimensional electron gas region forming means 12 includes the first and second depletion layer forming regions 22 and 25 and the Schottky electrodes 26 and 27, the source-side two-dimensional electron gas region 10S and the drain side Forming or forming the two-dimensional electron gas region 10D and the dot-shaped two-dimensional electron gas region 10T is easier than in the case of the conventional single-electron transistor shown in FIG. Therefore, in order to obtain the function as a single-electron transistor with high efficiency, the dot-shaped two-dimensional electron gas region 10T can be formed more minutely. If a bias voltage is applied between the Schottky electrode 26 constituting the two-dimensional electron gas region forming means 12 and the source electrode 7S and the bias voltage is adjusted, the Schottky junction of the Schottky electrode 26 can be obtained. Of the source-side tunnel barrier 18S between the source-side two-dimensional electron gas region 10S and the dot-shaped two-dimensional electron gas region 10T formed of a depletion layer extending from the substrate, and thus the transmittance of electrons passing through the source-side tunnel barrier 18S. Can be controlled, and the Schottky electrode 27 and the source electrode 7 can be controlled.
Assuming that a bias voltage is applied between S and S, if the bias voltage is adjusted, the drain-side two-dimensional electron gas region 10D and the dot-shaped two-dimensional electron gas region formed of a depletion layer extending from the Schottky junction of the Schottky electrode 27 are formed. 10
The length of the drain-side tunnel barrier 18D between T, and thus the transmittance of electrons passing through the drain-side tunnel barrier 18D, can be controlled, and in this case, the size of the dot-shaped two-dimensional electron gas region 10T, Therefore, dot 2
Even if the number of electrons changes in the one-dimensional electron gas region 10T, the change is much smaller than in the case of the conventional single-electron transistor described above with reference to FIG. Control electrodes 29A and 29B
The control voltage between one or both of them and the source electrode 7S causes the two-dimensional electron gas region 10T
, That is, the number of electrons in the dot-shaped two-dimensional electron gas region 10T, the lengths of both the source-side tunnel barrier 10S and the drain-side tunnel barrier 10D do not substantially change. Therefore, the function as a single-electron transistor can be easily obtained with a desired function as compared with the case of the conventional single-electron transistor described above with reference to FIG. In the above, only one embodiment of the single-electron transistor according to the present invention has been described, and various modifications and changes may be made without departing from the spirit of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a source-side two-dimensional electron gas region, a drain-side two-dimensional electron gas region, and a dot-shaped two-dimensional electron gas region showing an embodiment of a single-electron transistor according to the present invention. -Line plan view (FIG. 1A) and the b-
FIG. 1B is a cross-sectional view (FIG. 1B) on line b. FIG. 2 shows a source side 2 showing a conventional single-electron transistor.
FIG. 2A is a schematic plan view showing a state in which a two-dimensional electron gas region, a two-dimensional electron gas region on the drain side, and a two-dimensional dot-like electron gas region are formed, and a cross-sectional view thereof along the line bb (FIG. 2B). ). DESCRIPTION OF SYMBOLS 1 Compound semiconductor laminate 2 Compound semiconductor substrate or layer 3 Compound semiconductor layer 4 Compound semiconductor layer 5 Heterojunction 6 2D electron gas layer 7D Drain electrode 7S Source electrode 10D Drain side 2D electron gas region 10S Source side Two-dimensional electron gas region 10T Dot-shaped two-dimensional electron gas region 11 Depletion layer 12 Two-dimensional electron gas region forming means 13, 14, 15, 16 Schottky electrode 17 Single electron transfer control means 18D Drain-side tunnel barrier 18S Source-side tunnel barrier 26 , 27 Schottky electrodes 29A, 29B Control electrodes

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-196720 (JP, A) JP-A-5-152582 (JP, A) FUJISAWA et. al, AlGaAs / InGaAs / GaAs single electron transformers fabricated by Ga focused ion implantation, Applied Physics Letters, Applied Physics Letters, April 25, 1994, United States. 64, no. 17, p. 2250-2252 (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/778 H01L 29/80 H01L 29/812

Claims (1)

(57) [Claim 1] A compound semiconductor laminate in which a two-dimensional electron gas layer extending along a plane perpendicular to the laminating direction is formed, and the compound semiconductor laminate A source electrode and a drain electrode provided to be in contact with the two-dimensional electron gas layer; and a source-side two-dimensional electron gas region on the source electrode side from the two-dimensional electron gas layer in the compound semiconductor laminate. And a drain-side two-dimensional electron gas region on the drain electrode side and a dot-shaped two-dimensional electron gas region between the source-side two-dimensional electron gas region and the drain-side two-dimensional electron gas region are formed or formed by a depletion layer. A two-dimensional electron gas region forming means provided to control the number of electrons in the dot-shaped two-dimensional electron gas region by a depletion layer in the compound semiconductor laminate; Thereby, a single electron is generated between the source electrode and the drain electrode by the source-side two-dimensional electron gas region, the source-side two-dimensional electron gas region of the depletion layer of the two-dimensional electron gas region forming means, and the dot-shaped two-dimensional electron gas region. A source-side tunnel barrier between two-dimensional electron gas regions, the dot-shaped two-dimensional electron gas region, the dot-shaped two-dimensional electron gas region and the drain-side two-dimensional electron gas region of the depletion layer of the two-dimensional electron gas region forming means. A single-electron transistor having a drain-side tunnel barrier formed between the two-dimensional electron gas and a single-electron transfer control means provided to control movement through the drain-side two-dimensional electron gas region; A region forming means is provided in the compound semiconductor laminate, wherein the source of the two-dimensional electron gas layer is viewed from above in the compound semiconductor laminate. The first and second ion implantation regions are formed to form linear or band-shaped first and second depletion layers extending so as to sandwich the contact region between the drain electrode and the drain electrode, respectively. The line or band-shaped first and second depletion layer forming regions, and the compound semiconductor laminate, both extending across the first and second depletion layer forming regions as viewed from above, and A plurality of Schottky electrodes formed so as to form a plurality of Schottky junctions respectively forming a plurality of depletion layers extending into the compound semiconductor laminate with the compound semiconductor laminate; The control means includes a region in the compound semiconductor laminate between the two-dimensional electron gas layer and the first and second depletion layer formation regions as viewed from above, as viewed from the two-dimensional electron gas layer and the first depletion layer formation region. A first control electrode provided in contact on the opposite side of the, in the compound semiconductor lamination, as viewed from above, the two-dimensional electron gas layer and the second
And / or a second control electrode provided so as to be in contact with the depletion layer forming region on the side opposite to the region between the first and second depletion layer forming regions. A single-electron transistor comprising: