JP3434624B2 - Field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a high electron mobility transistor (High E mobility transistor) that operates in a very high frequency band of microwaves and millimeter waves.
lectron Mobility Transistor: hereinafter referred to as HEMT).

[0002]

2. Description of the Related Art A transistor having a high operating speed has been attracting attention in order to realize the utilization of radio waves in a high frequency band and the high speed calculation of a computer. The HEMT is one of ultra-high speed devices, and has a laminated structure in which a layer that supplies electrons (a doped layer) that is a carrier of a signal and a layer (channel layer) through which the supplied electrons travel is combined. There is. HEM
One of the factors that determines the performance of T is the material of the channel layer. In the past, GaAs was the mainstream for the channel layer,
Recently, InGaAs, which can transfer electrons faster than GaAs, has been attracting attention. In particular, InGaAs has a higher electron mobility and a higher electron transfer rate as x increases when expressed as Inx Ga1-x As, that is, as the In composition increases. using the set in _0.53 Ga _0.47 as, HEMT employing an InP substrate having a lattice constant equal the in _0.53 Ga _0.47 as has been fabricated. Further, it has been attempted to manufacture a HEMT having a higher In composition. I
InAlAs is generally used for the doped layer combined with the channel layer made of nGaAs. However, when the gate electrode is formed on InAlAs,
In particular, there is a problem that the withstand voltage is low when a voltage is applied in the opposite direction, and in order to solve this problem, for example, there is known a structure in which non-doped InGaAs is arranged immediately below the gate electrode (Japanese Patent Laid-Open No. Hei 4). No. 159730).

FIG. 4 shows a sectional structural view of the technique disclosed in Japanese Patent Laid-Open No. 4-159730. A buffer layer 30 made of InAlAs is formed on a substrate 311 made of InP.
2 (thickness 500 nm), channel layer 303 (thickness 20 nm) made of InGaAs, spacer layer 304 (thickness 2 nm) made of InAlAs, doped layer 305 (thickness 10 nm) made of n-type InAlAs, barrier made of InAlAs. 306 (film thickness 15 nm), InGaAs Schottky layer 307 (film thickness 10 nm), n-type InGaAs contact layer 308 (film thickness 10 n)
m) are sequentially stacked and a source electrode 309 and a drain electrode 310 are formed on the tact layer 308. Then, in the portion between the source electrode 309 and the drain electrode 310, the gate electrode 311 is formed on the Schottky layer 307 exposed by recess etching, and constitutes the HEMT 300. In the above description, layers not specifically described as n-type are non-doped semiconductor layers. With such a configuration, the gate electrode 311 is formed via non-doped InGaAs, and thus the breakdown voltage in the reverse direction can be increased as compared with the case where the electrode is directly formed on InAlAs.

[0004]

However, in the above disclosed technique, the contact layer 308 is removed in the portion between the source electrode 309 and the drain electrode 310, and the Schottky layer 307 having a film thickness of 10 nm (depth) is formed. About 5n
It is necessary to stop the etching in m), and an extremely high precision etching technique is required. Variations in the etching depth cause variations in the threshold voltage of the HEMT 300, shifts in the optimum bias conditions, and the like, causing a problem that the element characteristics vary. Further, since the gate electrode 311 is formed on the Schottky layer 307, the contact layer 308 is located just 5 nm above the contact portion between the gate electrode 311 and the Schottky layer 307, and the etching is uneven. In this case, the width of the recess etching groove is locally narrowed, the side surface of the gate electrode 311 and the contact layer 308 may approach each other, and the breakdown voltage may decrease.

Therefore, in view of the above problems, an object of the present invention is to form a source electrode and a drain electrode which require ohmic contact on an n-type contact layer and to form a gate electrode which requires Schottky contact as a non-doped Schottky. Different from the conventional technique formed on the layer, a semiconductor layer suitable for both the ohmic junction and the Schottky junction is selected, and the source electrode, the drain electrode, and the drain electrode are formed on the semiconductor layer without performing recess etching. By directly forming the gate electrode, there is no variation in characteristics, the breakdown voltage is improved,
It is to provide a HEMT capable of high speed and high frequency operation.

[0006]

In order to solve the above problems, the structure of the present invention is applied to a substrate made of semi-insulating InP.
A formed field effect transistor on a substrate,
A first semiconductor layer made of InGaAs not doped with impurities, a second semiconductor layer made of InAlAs having at least a portion doped with n-type impurities, and a semiconductor layer made of InGaAs not doped with impurities of 2 nm or more and 5n or more.
a third semiconductor layer having a film thickness of m or less is laminated ,
No impurities are added between the conductor layer and the third semiconductor layer.
It has a Schottky layer made of InAlAs and has a technical means of directly forming a source electrode, a drain electrode and a gate electrode on the third semiconductor layer.

The structure of the second invention employs a technical means in which the film thickness of the third semiconductor layer is equal directly under each of the source electrode, the drain electrode and the gate electrode.

The structure of the third invention employs a technical means that the source electrode and the drain electrode are formed so as to diffuse into the laminated semiconductor layers by the alloying treatment.

The structure of the fourth invention adopts the technical means that the source electrode and the drain electrode are made of AuGe / Ni / Au and the gate electrode is made of Ti / Pt / Au.

The structure of the fifth invention employs a technical means in which n-type impurities are ion-implanted directly under the source electrode and the drain electrode.

The structure of the sixth invention adopts the technical means that the source electrode, the drain electrode and the gate electrode are made of the same material.

In the structure of the seventh invention, the material forming the source electrode, the drain electrode and the gate electrode is Ti / Pt /
The technical means of being Au is adopted.

According to the eighth aspect of the invention, the first semiconductor layer I
The n composition is a technical means of being 53% or more and 100% or less.

[0014]

FUNCTIONS AND EFFECTS The inventors of the present application have studied theoretically the effect of the film thickness of a layer (hereinafter referred to as a cap layer) formed on the outermost surface of a semiconductor laminated structure on the HEMT performance. FIG. 3 shows a part of the result. FIG. 3A is a schematic cross-sectional view showing the configuration of the model used for the calculation.
InAlAs is formed on the substrate 1 made of semi-insulating InP.
The buffer layer 2 made of (In composition 52%) has a thickness of 100.
nm, a channel layer 3 made of InGaAs (In composition 80%) with a film thickness of 20 nm, InAlAs (In composition 52
%) Spacer layer 4 having a film thickness of 5 nm and n-type InAl
The doped layer 5 made of As (In composition: 52%) has a film thickness of 10
nm, an InAlAs (In composition: 52%) Schottky layer 6 having a film thickness of 5 nm, InGaAs (In composition: 53%).
%), The semiconductor layered structure in which the cap layer 7 made of a metal oxide film is sequentially laminated with a film thickness t (nm) is considered, and calculation is performed for the structure in which the gate electrode 11 is formed on the cap layer 7. Here, the doped layer 5 was doped with Si so that the carrier concentration was 7 × 10 ¹⁸ cm ⁻³ , and the other layers were non-doped.

In the calculation, the cross section AA 'in the figure was used as a one-dimensional model, and the fluctuation rate of the amount of electrons accumulated in the channel layer 3 with respect to the gate bias 13 was obtained, and the theoretically obtained mutual conductance was calculated. The electron quantity is calculated by using the method of solving the Schrodinger wave equation and Poisson's equation. Further, in the calculation, the saturation velocity of electrons in the channel layer 3 is assumed to be 2.5 × 10 ⁷ cm / sec, and it is expressed by the mutual conductance per 1 mm of the gate width. Here, the calculation result is shown in FIG. It can be seen that the transconductance increases as the film thickness t of the cap layer 7 decreases. It is considered that as the transconductance becomes higher, the gain of the HEMT is improved, and at the same time, the noise characteristic is also improved, so that the device performance is improved. From the above calculation, it was found that the cap layer 7 immediately below the gate electrode 11 should be thin.

On the other hand, considering the gate breakdown voltage,
For example, when the thickness of the cap layer 7 is set to 0 nm and the Schottky layer 6 is exposed, the leakage current of the gate increases and the breakdown voltage decreases, as described in JP-A-4-159730. Occurs. The main cause of this problem is that the interface level of the Schottky layer 6 is high, and it is considered that this interface level is related to the natural oxide layer of the semiconductor. Therefore, it can be said that the leakage problem can be solved by protecting the surface to the extent that the Schottky layer 6 is not oxidized. Therefore, the inventors of the present application experimentally investigated how thick InGaAs used for the cap layer 7 could prevent oxygen from entering. Specifically, a 100 nm InGaAs (In composition 53%) film is formed on an InP substrate by the molecular beam epitaxy (hereinafter referred to as MBE) method, and once taken out from the vacuum container of the MBE device into the air. Then, the distribution in the depth direction of oxygen in the InGaAs film was measured while gradually etching the surface with Ar ions using an Auger photoelectron spectrometer. As a result of the measurement, InGaAs with an In composition of 53%
Then, it was revealed that oxygen penetrated from the surface to about 2 nm. That is, if the surface of the Schottky layer 6 is covered with the cap layer 7 having a film thickness of 2 nm or more, the Schottky layer 6
It was found that the invasion of oxygen into the can be prevented.

Next, in order to reduce variations in device performance, HEM is premised on that recess etching is not performed.
Considering the structure of T, the source electrode and the drain electrode are
Non-doped InGaAs in contact with the gate electrode 11
Since it is formed on the cap layer 7 made of, it becomes a problem whether a good ohmic contact can be obtained. Here, the present inventors set the thickness of the cap layer 7 to about 5 nm.
It has been confirmed that good ohmic characteristics can be obtained even on a non-doped semiconductor layer if the source electrode and drain electrode are made thinner so that the electrode material diffuses into the semiconductor layer by alloying. did. Further, as another means for obtaining an ohmic contact, a region where a source electrode and a drain electrode are formed is n-doped by ion implantation.
A method of making ⁺ type is possible.

As a result of the theoretical calculation and the experimental examination as described above, H using InAlAs / InGaAs was obtained.
HEM without recess etching in EMT
We devised a structure that can configure T and that does not have variations in device performance due to variations in etching. A specific action of the present invention is to provide a first semiconductor layer made of InGaAs, to which no impurity is added, on a substrate made of semi-insulating InP ,
InAl with n-type impurities added at least in part
A second semiconductor layer made of As and a film thickness of 2 nm or more and 5 nm or less made of InGaAs to which impurities are not added.
Of the third semiconductor layer are stacked, the second semiconductor layer and the third
InAlAs with no impurities added between semiconductor layers
And a source electrode, a drain electrode, and a gate electrode are directly formed on the third semiconductor layer. This makes it possible to form the gate electrode without using recess etching, so that variations in device characteristics can be reduced, and since the side surface of the gate electrode and the semiconductor layer do not come into contact with each other, a decrease in breakdown voltage is prevented. The effect is that you can . Also, excellent element characteristics
HEMT can be obtained. Within the third semiconductor layer
Since it is possible to prevent oxygen from entering the semiconductor layer of the gate,
Can be prevented from increasing and the breakdown voltage can be prevented from decreasing.
In addition to being able to improve the source and drain electrodes
A good ohmic contact can be obtained (claim 1).

The second function is to change the film thickness of the third semiconductor layer by
The same is made directly under each of the source electrode, the drain electrode, and the gate electrode. This makes it possible to further reduce variations in device characteristics ( claim 2 ).

The third function is to form the source electrode and the drain electrode so as to diffuse into the laminated semiconductor layers by the alloying treatment. Thus, in a third semiconductor layer of undoped, the ohmic characteristics of the source electrode and the drain electrode can be made favorable (claim
3 ).

The fourth function is to construct a source electrode and a drain electrode with AuGe / Ni / Au, and to use Ti / Pt / Au.
Constitutes a gate electrode. As a result, the source electrode and the drain electrode can be better ohmic-contacted on the third semiconductor layer made of InGaAs, and Ti forming the gate electrode can form a Schottky junction with the third semiconductor layer. ( Claim 4 ).

The fifth function is to ion-implant an n-type impurity directly under the source electrode and the drain electrode. Thus, the source electrode and the drain electrode can be in ohmic contact with the third semiconductor layer of undoped, it can be Schottky contact gate electrode (claim
5 ).

The sixth function is to form the source electrode, the drain electrode and the gate electrode with the same material. This allows
The HEMT manufacturing method can be simplified and the production efficiency can be improved ( claim 6 ).

The seventh effect is that the source electrode, the drain electrode and the gate electrode are made of Ti / Pt / Au. Thereby, HEMT can be produced more preferably ( Claim 7 ).

The eighth function is to make the In composition of the first semiconductor layer 53% or more and 100% or less. Thereby, the electron mobility of the first semiconductor layer is increased, the resistance value between the source electrode and the drain electrode is reduced, and the performance of the HEMT is improved ( claim 8 ).

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on specific embodiments. FIG. 1 shows InAlA according to the present invention.
It is a typical sectional view showing composition of a 1st example of s / InGaAs / InP system HEMT100 (equivalent to a field effect transistor). As shown in FIG. 1, the semi-insulating I
InAlAs (In composition 52
%) Buffer layer 2, InGaAs (In composition 8
0%) of the channel layer 3 (corresponding to the first semiconductor layer), a spacer layer 4 of InAlAs (In composition 52%), and a doped layer 5 of n-type InAlAs (In composition 52%) (second). Equivalent to semiconductor layer), InAlAs
Schottky layer 6 made of (In composition 52%), InG
A cap layer 7 (corresponding to a third semiconductor layer) made of aAs (In composition 53%) is sequentially laminated. Then, the source electrode 9 and the drain electrode 10 made of AuGe / Ni / Au and the gate electrode 11 made of Ti / Pt / Au are directly formed on the cap layer 7, and the HEMT 10 is formed.
0 is configured. Here, in order to increase the number of electrons in the doped layer 5 as compared with the above calculation, 1 × 10 ¹⁹ is added.
cm ⁻³ was doped with Si, and the other layers were non-doped.

Next, a method of manufacturing the HEMT 100 will be described. First, in the MBE apparatus, a buffer layer 2 having a film thickness of 100 nm, a channel layer 3 having a film thickness of 20 nm, a spacer layer 4 having a film thickness of 5 nm, a dope layer 5 having a film thickness of 10 nm, and a Schottky layer 6 are sequentially formed on the substrate 1. A cap layer 7 having a film thickness of 5 nm is successively grown to a film thickness of 2 nm. Then, the source electrode 9 and the drain electrode 10 are formed on the cap layer 7, heated at 360 ° C. for 2 minutes for alloying, and Ge is diffused into the semiconductor laminated structure to obtain ohmic contact. Subsequently, the gate electrode 11 is formed on the cap layer 7 between the source electrode 9 and the drain electrode 10. Here, the distance between the source electrode 9 and the drain electrode 10 is 2 μm, the gate electrode 11 is located in the approximate center of both, and a so-called T-shaped gate having an upper width of 0.5 μm and a lower width of 0.15 μm is formed. . Since Ti of the gate electrode 11 is in contact with the cap layer 7, a Schottky junction can be formed.

With the configuration shown in FIG. 1, the HEMT 100 can be constructed without performing recess etching. If recess etching is omitted, HE
The film thickness of each semiconductor layer constituting the MT100 is determined by the first crystal growth step, but when an MBE apparatus is used,
Since the film thickness of the semiconductor layer can be controlled with extremely high accuracy on the atomic layer order and has high reproducibility, it is possible to extremely reduce variations in element characteristics and improve the quality of the HEMT 100. Furthermore, by omitting the etching process, the manufacturing process can be simplified and the HEM
Cost reduction of T100 can be realized.

In the above embodiment, the channel layer 3 is made of InG.
It was composed of aAs (In composition 80%).
The purpose is to improve the performance of the HEMT 100 by increasing the electron mobility of aAs to reduce the resistance between the source electrode 9 and the drain electrode 10, and when the performance required for the HEMT 100 is not so severe, the substrate 1 The operation of HEMT 100 is possible even with an In composition of 53% having a lattice constant equal to, and Inx Ga1-x As (x = 0.53 to 1) may be used. In addition, although the doped layer 5 is normally doped in the above embodiment, for example, a non-doped film thickness of 100 nm is used.
It is also possible to realize a structure in which the central portion of InAlAs is subjected to planar doping of about 1 × 10 ¹² cm ⁻² . here,
Although Si is used as the impurity to be doped, other materials such as Se can be used as an n-type doped material depending on the film forming method.

Next, a second embodiment according to the present invention will be described. Figure 2 shows InAlAs / InGaAs / In
FIG. 3 is a schematic cross-sectional view showing the configuration of a P-type HEMT 101. As shown in FIG. 2, the main feature of this embodiment is that ions are implanted into the portions directly below the source electrode 9 and the drain electrode 10 to form the ion-implanted region 12, and the manufacturing method thereof will be described below. explain. First, similarly to the first embodiment, the buffer layer 2, the channel layer 3, the spacer layer 4, the dope layer 5, the Schottky layer 6, and the cap layer 7 are sequentially laminated on the substrate 1. Next, Si ⁺ is implanted into the region directly below the portion where the source electrode 9 and the drain electrode 10 are formed, for example, at an energy of 150 KeV to about 4 × 10 ¹⁴ cm ⁻² , and flash annealing is performed at 950 ° C. for 2 seconds. , N ⁺ -type ion implantation region 12 is formed. Then, the HEMT 101 is formed by forming the source electrode 9, the drain electrode 10 and the gate electrode 11 made of Ti / Pt / Au on the cap layer 7.

Since the source electrode 9 and the drain electrode 10 thus formed on the ion implantation region 12 are in contact with the n ⁺ type semiconductor layer, an ohmic junction can be obtained. On the other hand, the gate electrode 11 formed in the region where the ion implantation is not performed is in contact with the non-doped semiconductor layer, so that a Schottky junction can be obtained.

By configuring the HEMT 101 as described above, it is not necessary to use recess etching as in the first embodiment, so that there is no variation in element characteristics, stable quality can be obtained, and the etching process is performed. The manufacturing process of the HEMT 101 can be simplified because the manufacturing process can be omitted. Further, the source electrode 9 and the drain electrode 1
0 and the gate electrode 11 are all made of the same material (Ti / Pt
/ Au), the manufacturing process can be further simplified.

In this embodiment, there is a problem that the contact resistance between the source electrode 9 and the drain electrode 10 is slightly high. When the contact resistance becomes a problem, the first embodiment is used, or the first embodiment and the second embodiment are combined and ion implantation is performed, and then the source electrode 9 and the drain electrode 10 are AuGe / drained. The contact resistance between the source electrode 9 and the drain electrode 10 can be minimized by forming the alloy with Ni / Au and performing heat treatment to alloy it. As described above, according to the present invention, InAlAs / InGaAs / InP having no characteristic variation and a simplified manufacturing process is provided.
The system HEMT 101 can be realized.

Although the spacer layer 4 is provided between the channel layer 3 and the doped layer 5 in the above embodiment, the spacer layer 4 is provided to prevent the scattering of electrons due to the impurities in the doped layer 5. And a spacer layer 4 if necessary.
The configuration may be omitted. Further, in the present embodiment, the buffer layer 2 is provided on the InP substrate 1, but the buffer layer 2 is a layer provided for the purpose of improving the crystal defects of the substrate 1, and the buffer layer 2 may be provided if necessary. The configuration may be omitted.

As indicated above, according to the present invention,
On a substrate of at least semi-insulating InP, a first semiconductor layer of undoped InGaAs, a second semiconductor layer of at least partially n-type doped InAlAs, and a third semiconductor layer of undoped InGaAs. In a field effect transistor in which a semiconductor layer is stacked, a gate electrode can be formed without using recess etching by directly forming a source electrode, a drain electrode, and a gate electrode over a third semiconductor layer. In addition, variations in device characteristics can be reduced, and since the side surface of the gate electrode and the semiconductor layer do not come into contact with each other, the breakdown voltage can be prevented from lowering. Moreover, since the etching process can be omitted, the efficiency of HEMT production can be improved. In the above embodiment, it is preferable to use, for example, Si or Se as the n-type impurity.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a sectional view showing the configuration of a second embodiment according to the present invention.

FIG. 3 is a cross-sectional view (a) showing a configuration of a model used for calculating the optimum value of the thickness of the cap layer according to the present invention and a graph (b) showing the calculation result.

FIG. 4 is a cross-sectional view showing the configuration of a conventional HEMT.

[Explanation of symbols]

1 semi-insulating InP substrate 2 non-doped InAlAs buffer layer 3 non-doped InGaAs channel layer 4 non-doped InAlAs spacer layer 5 n-type InAlAs doped layer 6 non-doped InAlAs Schottky layer 7 InGaAs cap layer 9 source electrode 10 drain electrode 11 gate electrode 12 ion implantation region 100 InAlAs / InGaAs / InP
System HEMT

Continuation of front page (56) Reference JP-A-4-180240 (JP, A) JP-A 64-23576 (JP, A) JP-A 5-182987 (JP, A) JP-A 5-283435 (JP , A) JP 60-132376 (JP, A) JP 64-41273 (JP, A) JP 6-140435 (JP, A) JP 4-159730 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/778 H01L 29/812

Claims (8)

(57) [Claims] 1. A substrate formed of semi-insulating InP.
And a field effect transistor, on said substrate, no impurity is added InGaAs
A first semiconductor layer made of, consists of InGaAs which is not a second semiconductor layer made of InAlAs the n-type <br/> impurity to at least a portion is added, an impurity is added
The third semiconductor layer of 5nm or less thickness than 2nm and are stacked <br/>, impurities between the said second semiconductor layer a third semiconductor layer
Schottky made of InAlAs with no added
A field effect transistor having a layer, wherein a source electrode, a drain electrode, and a gate electrode are directly formed on the third semiconductor layer. 2. The field effect transistor according to claim 1, wherein the film thickness of the third semiconductor layer is equal immediately below each of the source electrode, the drain electrode, and the gate electrode. 3. The source electrode and the drain electrode are
The field effect transistor according to claim 1 , wherein the field effect transistor is formed so as to be diffused in the stacked semiconductor layers by an alloying process. 4. The source electrode and the drain electrode are A
uGe / Ni / Au, and the gate electrode is Ti /
The field effect transistor according to claim 3 , wherein the field effect transistor is made of Pt / Au. 5. The field effect transistor according to claim 1, wherein an n-type impurity is ion-implanted just below the source electrode and the drain electrode. 6. The field effect transistor according to claim 5 , wherein the source electrode, the drain electrode, and the gate electrode are made of the same material. 7. The field effect transistor according to claim 6 , wherein the material is Ti / Pt / Au. 8. The In composition of the first semiconductor layer is 53%.
It is 100% or less above 100%, The field effect transistor of Claim 1 characterized by the above-mentioned.