JP4794022B2 - Semiconductor device - Google Patents

Description

【００１３】
と書ける。ゲート電極パッドや配線などとの間の寄生容量Ｃ_paraは、半絶縁性ＧａＡｓ基板上に形成されたＭＥＳＦＥＴが０．０３〜０．０５ｐＦであるのに対して、従来のＧａＡｓ／ＳｉのＭＥＳＦＥＴの場合、０．６〜０．７ｐＦ、あるいはＳｉＯ₂ を挿入したものでは０．１５ｐＦと大きいものであった。このように、界面の低抵抗層が原因となる寄生容量の増大が高周波特性の劣化の原因となっている。
【００１４】
次に、ＤＣ通電試験によるＭＥＳＦＥＴの電流値の減少の原因について説明する。これはミスフィット転位などが原因ではなく、エピタキシャル成長膜中の引っ張り応力が原因であることがわかった。例えばＧａＡｓ／ＳｉのＭＥＳＦＥＴではＧａＡｓの線膨張係数がＳｉの約２倍であることから、成長後の降温によってエピタキシャル成長膜に引っ張り応力が生じる。このような引っ張り応力により、伝導帯の底付近の分散関係がΓを正のエネルギー値として、近似的に、
【００１５】
【数２】

【００１６】
と書ける。Γ（＞０）は引っ張り応力による伝導帯の低下を意味する。ここで、ｍは伝導電子の有効質量、Ｅｃは伝導帯の底のエネルギーである。このとき、伝導帯中の電子の状態密度Ｎ（Ｅ）は、
【００１７】
【数３】

【００１８】
となる。
【００１９】
また、伝導帯中の電子の数は、
【００２０】
【数４】

【００２１】
と書ける。これらから分かるように、Γは伝導帯の状態密度や電子数を増やす。すなわち、ＧａＡｓ／ＳｉのＭＥＳＦＥＴでは、エージング前の初期状態で、エピタキシャル成長膜のチャネル部に加わっている引っ張り応力によってＧａＡｓ／ＧａＡｓと比較して状態密度が大きく、電流値が増大している状態となっている。そこで長時間のエージングによって局所的な応力緩和が起こり、増えていた電流値が小さくなると考えられる。つまり、Γ（＞０）が時間の経過と共に減少し、それが電流値の減少として観測される。
【００２２】
本発明はこのような従来技術の問題点に鑑みてなされたものであり、高周波特性の劣化とＤＣ通電試験による電流値の減少を解消した化合物半導体装置を提供することを目的とする。
【００２３】
【課題を解決するための手段】
上記目的を達成するために、請求項１に係る半導体装置では、Ｓｉ単結晶基板上に化合物半導体層を設けた半導体装置において、前記化合物半導体層が第一の化合物半導体層と第二の化合物半導体層とを順に積層して形成されており、前記第一の化合物半導体層がＧａＡｓ層と不純物としてＣを含むＩｎ_xＡｌ_yＧａ_1-x-yＡｓ層（０＜ｘ≦０．０５、０．２≦ｙ≦０．６）とから形成されており、前記第二の化合物半導体層がＩｎ_tＧａ_1-tＡｓ層（ｔ≧０．２）を含む層で形成されており、このＩｎ_tＧａ_1-tＡｓ層（ｔ≧０．２）をチャネルとして用いる。
【００２４】
上記半導体装置では、前記ＧａＡｓ層が１００〜２００Åの厚みに形成されていることが望ましい。
【００２５】
また、上記半導体装置では、前記第一の化合物半導体層における水銀プローブ式Ｃ−Ｖ測定による不純物密度が２×１０¹⁶ａｔｏｍｓ・ｃｍ^-3以上である領域の厚みが０．１μｍ以下であることが望ましい。
【００２６】
さらに、上記半導体装置では、前記Ｉｎ_t Ｇａ_1-t Ａｓ層（ｔ≧０．２）上にＰｔを含むショットキー電極が形成されていることが望ましい。
【００２７】
【発明の実施の形態】
以下、各請求項に係る実施形態を添付図面に基づき詳細に説明する。図１は請求項１に係る半導体装置の実施例の断面図であり、１はＳｉ基板、２はＧａＡｓ層、３はＩｎＡｌＧａＡｓ層、４はｉ−ＩｎＧａＡｓ層、５はｎ−ＩｎＧａＡｓ層、６はｎ⁺ −ＩｎＧａＡｓ層、７はオーミック電極、８はゲート電極、９ｂはＳｉＯ₂ 膜である。
【００２８】
抵抗率２〜６×１０³ Ωｃｍ程度の高抵抗Ｓｉ基板１上に、第一の化合物半導体層としてＧａＡｓ層２が１５０Å、その上にＩｎ_0.02Ａｌ_0.49Ｇａ_0.49Ａｓ層３が２．６μｍ形成されており、その上に第二の化合物半導体層としてｉ−ＩｎＧａＡｓ層４が１．６μｍ、およびチャネルとして働くｎ−Ｉｎ_0.2 Ｇａ_0.8 Ａｓ層５、コンタクト層として働くｎ⁺ −Ｉｎ_0.2 Ｇａ_0.8 Ａｓ層６が積層されている。
【００２９】
このような化合物半導体層は、（１１０）方向に数度のオフ角をもつ（１００）Ｓｉ基板１をカーボンサセプタ上に設置し、有機金属材料を加熱分解して他の有機金属材料構成元素と高温で反応させる有機金属化学気相成長法（ＭＯＣＶＤ法）により形成される。すなわち、まず９００〜９５０℃で熱処理した後、４００〜４５０℃に下げて保持し、ＧａＡｓ層２を１５０Å成長した後、通常の成長温度である６２０℃まで昇温し、Ｉｎ_0.02Ａｌ_0.49Ｇａ_0.49Ａｓ層３を２．６μｍ成長させ、続いて基板温度を５８０℃まで下げてＩｎ_0.2 Ｇａ_0.8 Ａｓ層４〜６を成長する。Ｉｎ_0.2 Ｇａ_0.8 Ａｓ層４はエピタキシャル成長膜中の応力低減に好適に用いられ、デバイスの信頼性の向上に寄与することを我々は見出した。この理由に関しては後述する。Ｉｎの組成を０．０２から０．２まで徐々に変化させたり、いわゆるメタモルフィック成長などの成長方法でＩｎ組成をさらに大きくしてもよい。
【００３０】
第一の半導体層２、３中のＩｎ_0.02Ａｌ_0.49Ｇａ_0.49Ａｓ層３は、不純物としてＣ（カーボン）を含んでおり、このＣ（カーボン）はＩｎ_0.02Ａｌ_0.49Ｇａ_0.49Ａｓ層３のＡｓサイトに不純物として混入し、Ｓｉ基板１からのＳｉ不純物の拡散によるｎ型キャリアを補償する働きをする。
【００３１】
図３は、アセック社製水銀プローブ式Ｃ−Ｖ測定装置による従来の半導体装置と本発明の実施例の半導体装置のエピタキシャル成長膜の深さ方向キャリア密度の測定結果であり、横軸は深さ０μｍをＳｉ基板１とＧａＡｓ層２の界面に選んである。測定は１００〜２００ｋＨｚで行った。深さ方向のキャリア密度の測定は、深さ分解能の低下などのために、電気化学的エッチングによるＣ−Ｖ測定では測定が困難なことが多いが、空乏層の広がり具合から深さを算出する水銀プローブ式Ｃ−Ｖ測定では可能である。この測定は第一の半導体層２、３まで成長が終了した時点で成長を中断して行うか、第二の半導体層４、５、６以降の化合物半導体層をエッチング除去した後に行なう。
【００３２】
従来の半導体装置の場合は、シリコン基板１から約０．３５μｍまでは３×１０¹⁶ａｔｏｍｓ・ｃｍ^-3以上のキャリア密度であり、約０．８５μｍまでは１×１０¹⁶ａｔｏｍｓ・ｃｍ^-3以上のキャリア密度であった。
【００３３】
本発明の実施例の場合、Ｉｎ_0.02Ａｌ_0.49Ｇａ_0.49Ａｓ層３の成長条件としてＶ族ガス中のアルシンのモル数のIII 族ガス中のトリメチルインジウム、トリメチルアルミニウム、トリメチルガリウムの合計のモル数に対する比で定義されるＶ／III 比を１００〜１５０に定めることにより、不純物密度が３×１０¹⁶ｃｍ^-3以上であるエピタキシャル成長膜の厚みが０．１μｍ以下まで低減した。
【００３４】
このような第一の半導体層２、３を形成することによって、ＭＥＳＦＥＴやＨＥＭＴなどの寄生容量は低減し、高周波特性が大幅に向上する。本実施例では１００μｍ×１００μｍのゲートパッドを有するゲート長が１μｍでゲート幅が１００μｍの場合、Ｃ_paraは０．０５ｐＦまで下がり、電流利得遮断周波数ｆ_T ＝１３ＧＨｚ、最大発振周波数ｆ_MAX ＝２４ＧＨｚのＭＥＳＦＥＴが得られた。
【００３５】
図５（ａ）は、本発明の実施例の半導体装置の出力インピーダンスＳ₂₂の測定結果を示す。測定にはウイルトロン製ネットワークアナライザー３７３６９Ａを用いて２０ＭＨｚから２０ＧＨｚまで行った。図５（ｂ）は、従来のＳｉ基板上のＧａＡｓ層を動作層とする半導体装置の測定結果であり、図５（ｃ）は、ＧａＡｓ基板上のＧａＡｓエピタキシャル層を動作層とする半導体装置の測定結果である。これらから分かるように、従来のＳｉ基板上のＧａＡｓ層を動作層とする半導体装置では、リアクタンス成分の影響を大きく受けている。これは界面の導電層が原因であると思われる。それに対して本実施例では、第一の半導体層２、３を基板からのＳｉ不純物の拡散によるｎ型キャリアを補償する構造を採ったため、ＧａＡｓ基板上の半導体装置とほぼ同等の出力インピーダンスＳ₂₂が得られていることがわかる。
【００３６】
このような補償による高抵抗化を目的とする不純物Ｃ（カーボン）のドーピングは、第一の化合物半導体層２、３の一部にＩｎ_xＡｌ_yＧａ_1-x-yＡｓ層（０＜ｘ≦０．０５、０．２≦ｙ≦０．６）３を用いることによって容易に達成することができる。Ａｌ組成ｙを大きくすると、Ｃ（カーボン）がＡｓサイトに入りやすくなり、補償を容易にする。Ａｌ組成ｙを大きくしすぎると、半導体装置のチャネル温度の上昇に起因する信頼性の悪化の原因となる。そのため、Ａｌ組成としては０．２≦ｙ≦０．６が好適に用いられる。また、Ｉｎを数％混入させることによって半導体基板の表面モホロジーが良好となる。
【００３７】
また、第一の半導体層２、３中のＳｉ基板側にＧａＡｓ膜２を１００〜２００Å形成するが、１００Å以下にすると表面モホロジーが劣化する。ＧａＡｓ膜２を２００Å以上形成した場合、寄生容量が増大して高周波特性が劣化する原因となる。
【００３８】
また、Ｓｉ基板１に直接ＡｌＧａＡｓなどを成長させることができた場合、高周波特性にはさらに有利に働く可能性があるが、ＡｌＧａＡｓの実効固化温度（後で定義する）がＧａＡｓよりもやや高いため、そりや応力を増大させる。本実施例の場合、Ｓｉと実効固化温度（後で定義する）が高いＩｎ_xＡｌ_yＧａ_1-x-yＡｓ層（０＜ｘ≦０．０５、０．２≦ｙ≦０．６）の間にＧａＡｓ層２が１００〜２００Å形成されているため、線膨張係数差によるそりおよび応力の駆動力が減ることになり、そりおよび応力の低減の点で有利である。
【００３９】
次に、Ｉｎ_0.2 Ｇａ_0.8 Ａｓ層４、５、６による応力および基板そりの低減の効果について説明する。我々は様々な層構造のヘテロエピタキシャル成長基板におけるそりや応力の実験データを詳細に比較して検討することにより、下に示す（２）で定義した実効固化温度がＩｎ_0.2 Ｇａ_0.8 Ａｓ層４、５、６で小さくなることを見出した。この実効固化温度の低下がエピタキシャル成長膜中の応力の低減に対応する。以下、そのメカニズムを説明する。
【００４０】
図４に示すようなｎ−１層のエピタキシャル成長層α₁ 〜α_n を積層したヘテロエピタキシャル基板を考える。このヘテロエピタキシャル基板は、成長温度が非常に高温であるため、転位が容易に動くことができ、このような転位の生成と運動によって各層α₁ 〜α_n の線膨張係数の相違による応力や格子定数の相違による応力は緩和され、ウエハのそりなどは発生せず平坦であり、ほとんどエピタキシャル成長膜中に応力は生じない。しかしながら、ある温度以下になると、このような転位の生成や運動は生じなくなり、応力を緩和することができず、各エピタキシャル成長層α₁ 〜α_n の間に大きさが等しく反対向きに力が働くと同時にウエハがそり始め、応力が生じ始める。この温度は各層α₁ 〜α_n によって異なり、以下では各層α₁ 〜α_n の実効固化温度と呼ぶことにする。それぞれのエピタキシャル成長層α₁ 〜α_n 、および基板のヤング率を上方から順にＥ₁ 、Ｅ₂ 、Ｅ₃ 、‥‥‥、Ｅ_n とし、エピタキシャル成長膜の厚みをｈ₁ 、ｈ₂ 、ｈ₃ 、‥‥‥、ｈ_n などとし、膜ｉにかかる応力σ_i は引っ張り応力を正として、
【００４１】
【数５】

【００４２】
‥‥‥‥‥‥（１）
と書ける。但し、ｂは基板の直径、ρは曲率半径、ｙ_u はエピタキシャル成長基板の上面からの距離、ｙ_m は中立面の位置であり、図４に示すように、エピタキシャル成長層α₁ 〜α_n 間に働く力Ｆを定めた。（１）の第一項はエピタキシャル成長層α₁ 〜α_n 間に働く力Ｆによる応力であり、第二項は曲げによる応力である。このような応力と同時に、大きさがｂ² ／８ρのそりが生じる。
【００４３】
（１）式中の中立軸の位置ｙ_m は曲げ応力の断面内総和が０であることから求まり、
【００４４】
【数６】

【００４５】
となる。また、曲率半径ρは曲げモーメントＭ_tot および断面２次モーメントＩ_i から容易に求まり、
【００４６】
【数７】

【００４７】
と書ける。ここで、Ｍ_tot およびＩ_i は、それぞれ曲げモーメントおよび断面２次モーメントであり、次のように書ける。
【００４８】
【数８】

【００４９】
、
【００５０】
【数９】

【００５１】
一方、（１）式中のＦは、ここでは格子定数の相違によって生じる歪みの大部分が転移や結晶欠陥によって緩和され、熱歪みとエピタキシャル成長層との間に働く力による歪みの和が各層で等しいと近似し、
【００５２】
【数１０】

【００５３】
‥‥‥‥‥‥‥‥‥‥‥‥（２）
と書ける。ここで、ΔＴ_i は実効固化温度と室温との温度差である。実際は、格子定数差に起因する歪みの項が各式に加わると考えることができるが、それは第一近似では線膨張係数の相違に起因する熱歪みが支配的であると考え、実効固化温度の再定義によってくりこむことができる。（２）式中のΔＴ_i および上に述べた実効固化温度は、そのような量として理解されなければならない。また、先に形成される下の層の実効固化温度が低いときは、その実効固化温度以下で初めて連続体近似が成り立つため、その下の層の実効固化温度と一致させなければならない。ここで、（２）式の解を本実施例のようにｎ＝４の場合に書き下しておく、
【００５４】
【数１１】

【００５５】
【数１２】

【００５６】
【数１３】

【００５７】
このＦ₁ 〜Ｆ₃ と（１）から、エピタキシャル成長膜に働く応力が求まることとなる。我々は（２）で定義した実効固化温度と様々なヘテロエピタキシャル膜構造のそりの実験結果を比較検討し、様々な化合物半導体混晶の実効固化温度を決定した。例えばＧａＡｓの実効固化温度は３５０℃程度であり、Ｉｎ_0.2 Ｇａ_0.8 Ａｓの実効固化温度は２４０℃程度である。
【００５８】
本実施例の場合の応力と基板そりをＩｎ_0.2 Ｇａ_0.8 Ａｓ層４、５、６の代わりにＧａＡｓ層を用いた場合と比較して述べる。本実施例のＩｎ_0.2 Ｇａ_0.8 Ａｓ４、５、６の代わりにＧａＡｓ層を用いた場合、（１）から求まる全応力（エピタキシャル成長膜の残留応力）は９．２×１０⁸ ｄｙｎ／ｃｍ² であり、３インチ基板の場合のそりはｂ² ／８ρ〜７９μｍとなる。それに対して、本実施例の場合、（１）から求まる全応力（エピタキシャル成長膜の残留応力）は２．６×１０⁸ ｄｙｎ／ｃｍ² となり、３インチ基板の場合のそりはｂ² ／８ρ〜５１μｍとなる。
【００５９】
このように、Ｉｎ_0.2 Ｇａ_0.8 Ａｓを用いることにより、そりおよび応力が低減するのは、Ｉｎ_0.2 Ｇａ_0.8 Ａｓの実効固化温度が２４０℃程度と、ＧａＡｓの実効固化温度３５０℃程度と比較して小さいからであると思われる。また、Ｉｎ_t Ｇａ_1-t Ａｓ層４、５、６の実効固化温度はｔ〜０．２付近で急激に低下する。そのため、ｔ≧０．２とすると、このような基板そりおよびエピタキシャル成長膜の残留応力が小さくなる。
【００６０】
本実施例のＭＥＳＦＥＴのＤＣ通電試験による電流値変動を図２（ａ）に記す。このように、従来の図２（ｂ）と比較して電流値の変動は小さくなった。これはエピタキシャル成長膜に残留しているひっぱり応力による伝導帯の低下がそもそも小さいため、通電試験による電流値変化も小さくなったと思われる。
【００６１】
このような半導体基板を用いてＭＥＳＦＥＴやＨＥＭＴを含む半導体装置が以下に示すプロセスによって形成される。すなわち、図６（ａ）に示すように、通常のフォトリソグラフィによって所望のメサ領域を限定し、硫酸、過酸化水素、水の混合液をエッチャントとしてＩｎＧａＡｓ膜４の途中までエッチングする。レジストを除去した後、一回り小さいメサ領域をフォトレジストにより形成し、同様に化合物半導体膜５、６をエッチングする。このエッチングはゲート電極の断線を妨げるため、第一回のエッチングよりもやや浅くすることが望ましい。このようにして、高さの異なる２段のメサが形成される。
【００６２】
次に、図６（ｂ）に示すように、プラズマＣＶＤ法またはスパッタリング法によって基板全面にＳｉＯ₂ またはＳｉＮ_x Ｏ_y などからなる絶縁膜９ａを約１．５μｍ形成し、フォトレジスト開口パターンを形成した後、メサ領域上の化合物半導体層６が完全に露出するように、バッファフッ酸などによって絶縁膜９ａをエッチングする。すると、化合物半導体層４上には絶縁膜９ａが残り、メサ領域上には化合物半導体層６が露出する。なお、この絶縁膜９ａのエッチングにはＲＩＥ（反応性イオンエッチング）法やＣＤＥ（ケミカルドライエッチング）法を用いてもよい。
【００６３】
次に、図７（ａ）に示すように、ゲート電極を形成する。プラズマＣＶＤ法などを用いて基板全面にＳｉＯ₂ からなる絶縁膜９ｂを０．５μｍ形成する。続いて、ゲート電極形成用のフォトレジスト開口パターンを形成し、図７（ｂ）に示すように、ＳｉＯ₂ 膜９ｂをエッチングする。このエッチングには、ＢＨＦ（バッファードフッ酸）（ＨＦ：Ｈ₂ Ｏ：ＮＨ₄ Ｆ＝１：１０：１０）を用いる。なお、エッチングに先立ってプラズマアッシャーを用いてアッシング処理を行ない、エッチャントが開口内に進入できるように前処理を行うことにより、微細な開口からのウエットエッチングを容易に行うことができる。
【００６４】
次に、図７（ｃ）に示すように、ｎ⁺ −ＩｎＧａＡｓ層６のリセスエッチングを行う。まず、アッシング前処理によってエッチング液が開口部に進入できるようにした後、硫酸、過酸化水素水を混合した水溶液を用いてｎ⁺ −ＩｎＧａＡｓ層６が完全にエッチングされるまでエッチングし、図７（ｄ）に示すように、Ｐｔ、Ａｕ／Ｐｔ／Ｔｉ、Ａｕ／Ａｌ／Ｐｔなどからなるゲート電極８を抵抗加熱真空蒸着装置を用いて形成する。ゲートはフォトレジスト１０をマスクとして形成されるため、フォトレジスト１０の開口幅によってゲート長は決定される。
【００６５】
本実施例のように、ｎ−ＩｎＧａＡｓ層５上にゲート電極８を形成する場合、ゲート電極８はＰｔを含む電極であることが望ましい。Ｐｔを含む電極とＩｎＧａＡｓ層とのショットキー接合はその障壁高さが約１．２ｅＶであり、ＧａＡｓとＡｌやＴｉとのショットキー障壁高さ約０．８ｅＶと比較して高い。このため、大信号動作させたとき、電流のスイング幅を大きくとることができ、大きな出力を得ることができる。また、増幅器の設計自由度が増すため、互いにトレイドオフの関係にある線形性と高効率性を同時に満たす増幅器などが比較的容易に形成できる。
【００６６】
その後、図７（ｅ）に示すように、フォトレジスト１０をリフトオフすることにより、フォトレジスト１０とその上のゲート電極８を除去する。
【００６７】
最後に、オーミックコンタクト層６上にオーミック電極７を形成するための開口パターン（不図示）を形成し、絶縁膜９ｂをバッファフッ酸でエッチングした後、オーミックコンタクト層６上にＡｕＧｅ／ＡｕまたはＡｕＧｅ／Ｎｉ／Ａｕからなるをオーミック電極７を蒸着してリフトオフによりパターニングし、熱処理によって合金化することで、図１に示すような半導体装置が形成される。
【００６８】
なお、ＭＥＳＦＥＴの代わりに、ＩｎＡｌＡｓ／ＩｎＧａＡｓあるいはＡｌＧａＡｓ／ＩｎＧａＡｓ型のＨＥＭＴを形成しても同様の効果があることは当業者には明らかである。
【００６９】
【発明の効果】
以上のように、請求項１に係る半導体装置によれば、Ｓｉ単結晶基板上に設けた第一の化合物半導体層がＧａＡｓ層と不純物としてＣを含むＩｎ_xＡｌ_yＧａ_1-x-yＡｓ層（０≦ｘ≦０．０５、０．２≦ｙ≦０．６）とから形成されており、バッファ層の高抵抗化が達成され、電流利得遮断周波数、最大発振周波数などの高周波特性が大幅に向上する。また、第一の化合物半導体層上に形成される第二の化合物半導体層がＩｎ_tＧａ_1-tＡｓ層（ｔ≧０．２）を含む層で形成されており、このＩｎ_tＧａ_1-tＡｓ層（ｔ≧０．２）をチャネルとして用いることから、エピタキシャル成長膜内の残留応力が低減し、半導体装置の優れた信頼性を確保することができる。また、同時に基板そりも低減することができ、歩留まりを大幅に向上させることができる。
【００７０】
また、請求項２に係る半導体装置では、第一の化合物半導体層中のＳｉ単結晶基板側のＧａＡｓ層の厚みを１００〜２００Åに形成したので、基板そりや応力を小さく保ちつつ、高周波特性を向上させることができる。また、表面モホロジーも良好な半導体基板を得ることができ、半導体装置の製造歩留まりが向上する。
また、請求項３に係る半導体装置によれば、第一の化合物半導体層における水銀プローブ式Ｃ−Ｖ測定による不純物密度が２×１０¹⁶ｃｍ^-3以上であるエピタキシャル成長膜の厚みが０．１μｍ以下となるように各種成長条件を調節し、カーボンなどの不純物の量を最適化したため、高周波特性が向上する。
【００７１】
さらに、請求項４に係る半導体装置によれば、前記Ｉｎ_t Ｇａ_1-t Ａｓ層（ｔ≧０．２）上にＰｔを含むショットキー電極を形成したため、ショットキー障壁高さが大きくなり、ゲート耐圧が大きくなる。また、大信号動作の際のスイング幅を大きくとることができるため、ドレイン効率や電力付加効率などが向上し、高周波用の半導体装置を形成した際に消費電力を小さくすることができる。また、ショットキー障壁高さが大きいため、優れた特性のエンハンスメント型の半導体装置を容易に形成することができる。
【図面の簡単な説明】
【図１】本発明に係る半導体装置のゲート電極と垂直な方向の断面図である。
【図２】（ａ）は本発明に係る半導体装置のＤＣ通電試験の結果であり、（ｂ）は従来のＳｉ基板上のＧａＡｓを動作層とする半導体装置のＤＣ通電試験の結果である。
【図３】水銀プローブ式Ｃ−Ｖ測定による深さ方向のキャリア密度の測定結果である。
【図４】エピタキシャル成長膜中のそりおよび応力低減を説明するための図である。
【図５】（ａ）は本発明に係る半導体装置の出力インピーダンスＳ₂₂の測定結果であり、（ｂ）は従来の半導体装置の出力インピーダンスＳ₂₂の測定結果であり、（ｃ）はＧａＡｓ基板上の半導体装置の出力インピーダンスＳ₂₂の測定結果である。
【図６】（ａ）〜（ｂ）は、本発明に係る半導体装置の製造方法のゲート電極と平行な方向の断面図である。
【図７】（ａ）〜（ｅ）は、本発明に係る半導体装置のゲート電極の形成方法を説明するための図である。
【符号の説明】
１‥‥‥Ｓｉ基板、２‥‥‥ＧａＡｓ層、３‥‥‥ＩｎＡｌＧａＡｓ層、４‥‥‥ｉ−ＩｎＧａＡｓ層、５‥‥‥ｎ−ＩｎＧａＡｓ層、６‥‥‥ｎ⁺ −ＩｎＧａＡｓ層、７‥‥‥オーミック電極、８‥‥‥ゲート電極、９（ａ）‥‥‥ＳｉＯ₂ 膜、９（ｂ）‥‥‥ＳｉＯ₂ 膜、１０‥‥‥フォトレジスト[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a field effect transistor (Metal Semiconductor Field Effect Transistor) and a high electron mobility transistor (High Electron Mobility Transistor) having a compound semiconductor laminated on a Si substrate as an operation layer.
[0002]
[Prior art]
A semiconductor device using a compound semiconductor can generally operate at a higher speed and a higher frequency range than a silicon semiconductor. As a high-speed, high-frequency transistor for high-speed digital signal processing or microwave amplification, MES (Metal Semiconductor) Field effect transistors such as FETs and HEMTs (High Electron Mobility Transistors) are used, and their use is gradually expanding. Nevertheless, the diameter of the bulk substrate made of only the compound semiconductor is still about 3 to 4 inches, and the semiconductor device formed on the substrate is larger than the silicon substrate that has been increased in size and price. This contributes to the difficulty of mass production.
[0003]
Accordingly, attention has been focused on a compound semiconductor substrate in which a III-V compound semiconductor layer is epitaxially grown on a silicon substrate. By epitaxially growing a compound semiconductor on a silicon substrate, it is possible to increase the diameter of the substrate and reduce the cost. In addition, since a substrate in which a compound semiconductor layer is formed on a silicon substrate has excellent mechanical strength and high thermal conductivity, it has characteristics such as excellent heat dissipation when a semiconductor device is formed and easy handling. . In addition, since compound semiconductors have excellent optical and electrical characteristics, if an excellent crystalline compound semiconductor layer can be grown on a silicon substrate, electronic devices such as MESFET and HEMT and optical devices such as LED and LD can be used on the same substrate. It is also possible to fabricate the optical / electronic hybrid device fabricated above.
[0004]
[Problems to be solved by the invention]
However, a disadvantage of a semiconductor device in which a compound semiconductor is formed on a silicon substrate is that when a compound semiconductor layer is heteroepitaxially grown on a silicon substrate, silicon atoms diffuse and penetrate into the compound semiconductor layer due to a temperature history during initial growth. This causes a problem that the compound semiconductor layer becomes a resistance to the compound semiconductor and the resistance of the compound semiconductor layer is lowered, and the high frequency characteristics of the semiconductor device are deteriorated.
[0005]
That is, when a compound device is formed by laminating a plurality of compound semiconductors on a silicon substrate and a semiconductor device having a part of the compound semiconductor layer as an operation layer is formed, a low resistance layer is formed at the interface between the silicon substrate and the compound semiconductor, Due to the large parasitic capacitance compared to the semiconductor device formed on the semi-insulating GaAs substrate or semi-insulating InP substrate, the current gain cutoff frequency f _T And maximum oscillation frequency f _MAX Only field effect transistors with significantly deteriorated high frequency characteristics such as were obtained.
[0006]
As an example of a conventional semiconductor device, an example in which MESFET is formed by forming GaAs on a silicon substrate will be described. A GaAs layer is formed on a silicon substrate by a so-called two-stage growth method, and a MESFET using the n-GaAs layer formed thereon as a channel is formed by a normal manufacturing process. When a MESFET having a gate length of 1 μm and a gate width of 100 μm having a gate pad of 100 μm × 100 μm was prototyped, the current gain cutoff frequency f _T = 4.9 GHz, maximum oscillation frequency f _MAX Only a device of = 5.2 GHz was obtained. This is due to an increase in the parasitic capacitance of the gate pad. When prototyped on a semi-insulating GaAs substrate with the same size and shape, f _T = 12 GHz or more, f _MAX = A semiconductor device of 20 GHz or more was obtained.
[0007]
For example, in Japanese Patent Laid-Open No. 8-51121, there is SiO under the gate pad. ₂ It has been proposed to improve the high-frequency characteristics by inserting.
[0008]
However, SiO inserted under the gate pad ₂ When the thickness is increased, the high-frequency characteristics are improved, but even if the thickness is increased, the limit is about 1.5 μm. At this time, when the semiconductor device having the above-described shape is formed, the current gain cutoff frequency f is increased. _T = 6.6 GHz, maximum oscillation frequency f _MAX Although the frequency is improved up to about 7.3 GHz, the high frequency characteristics are still inferior compared with the case of trial manufacture on a semi-insulating GaAs substrate.
[0009]
In addition, when the DC current test is performed, there is a problem that the current value fluctuates. In this DC current test, in order to simply evaluate the reliability of the epitaxially grown film, a constant voltage is applied between the source and the drain with the gate electrode opened to examine the fluctuation of the current value. is there. The reliability evaluation of a semiconductor device is performed by various methods such as a high temperature storage test and a DC current test. The DC current test can easily determine the material characteristics when a high electric field is continuously applied to the epitaxial growth film. .
[0010]
In a semiconductor device in which a compound semiconductor is formed on a conventional silicon substrate, a DC energization test in which 8 V is applied between the source and the drain with the gate opened is performed, as shown in FIG. 2B, for 28800 seconds. Later, a decrease in current value of 20% or more was observed. FIG. 2 shows the results of a DC current test of a semiconductor device according to an embodiment of the present invention to be described later.
[0011]
Next, the cause of the deterioration of the high frequency characteristics and the cause of the decrease in the current value due to the DC current test will be briefly described. First, the current gain cutoff frequency f of the MESFET _T The cause of the deterioration of the high-frequency characteristics will be described with reference to FIG. In the case of a substrate formed by stacking compound semiconductors on a conventional silicon substrate, silicon atoms diffuse into the compound semiconductor layer, so that a low resistance layer is generated at the interface between the silicon substrate and the compound semiconductor substrate. Therefore, the current gain cutoff frequency f _T Is the electron saturation rate v _s , The effective gate length is L _eff , Transconductance g _m , The gate parasitic capacitance is C _para As a general rule,
[0012]
[Expression 1]

[0013]
Can be written. Parasitic capacitance C between gate electrode pad and wiring _para The MESFET formed on the semi-insulating GaAs substrate is 0.03 to 0.05 pF, whereas the conventional GaAs / Si MESFET is 0.6 to 0.7 pF or SiO 2 ₂ It was as large as 0.15 pF. Thus, the increase in parasitic capacitance caused by the low resistance layer at the interface causes the deterioration of the high frequency characteristics.
[0014]
Next, the cause of the decrease in the current value of the MESFET due to the DC current test will be described. It was found that this was not caused by misfit dislocations but by tensile stress in the epitaxially grown film. For example, in a GaAs / Si MESFET, the linear expansion coefficient of GaAs is about twice that of Si, so that a tensile stress is generated in the epitaxial growth film due to the temperature drop after growth. Due to such tensile stress, the dispersion relation near the bottom of the conduction band is approximated with Γ as a positive energy value,
[0015]
[Expression 2]

[0016]
Can be written. Γ (> 0) means a decrease in the conduction band due to tensile stress. Here, m is the effective mass of conduction electrons, and Ec is the energy at the bottom of the conduction band. At this time, the density of states N (E) of electrons in the conduction band is
[0017]
[Equation 3]

[0018]
It becomes.
[0019]
The number of electrons in the conduction band is
[0020]
[Expression 4]

[0021]
Can be written. As can be seen, Γ increases the density of states and the number of electrons in the conduction band. That is, in the GaAs / Si MESFET, in the initial state before aging, the state density is larger than that of GaAs / GaAs due to the tensile stress applied to the channel portion of the epitaxial growth film, and the current value is increased. ing. Therefore, it is considered that local stress relaxation occurs due to long-term aging, and the increased current value becomes small. That is, Γ (> 0) decreases with time, and this is observed as a decrease in current value.
[0022]
The present invention has been made in view of such problems of the prior art, and an object of the present invention is to provide a compound semiconductor device that eliminates deterioration of high-frequency characteristics and a decrease in current value due to a DC current test.
[0023]
[Means for Solving the Problems]
To achieve the above object, in the semiconductor device according to claim 1, in the semiconductor device in which a compound semiconductor layer is provided on a Si single crystal substrate, the compound semiconductor layer includes a first compound semiconductor layer and a second compound semiconductor. layer When Are stacked in order, and the first compound semiconductor layer is a GaAs layer. Contains C as an impurity In _x Al _y Ga _1-xy As layer (0 <x ≦ 0.05, 0.2 ≦ y ≦ 0.6) When And the second compound semiconductor layer is made of In. _t Ga _1-t It is formed of a layer including an As layer (t ≧ 0.2). _t Ga _1-t An As layer (t ≧ 0.2) is used as the channel.
[0024]
In the semiconductor device, the GaAs layer is preferably formed to a thickness of 100 to 200 mm.
[0025]
In the semiconductor device, the impurity density of the first compound semiconductor layer measured by mercury probe CV measurement is 2 × 10. ¹⁶ atoms · cm ^-3 The thickness of the above region is desirably 0.1 μm or less.
[0026]
Further, in the semiconductor device, the In _t Ga _1-t It is desirable that a Schottky electrode containing Pt is formed on the As layer (t ≧ 0.2).
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments according to the claims will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of an embodiment of a semiconductor device according to claim 1; 1 is a Si substrate, 2 is a GaAs layer, 3 is an InAlGaAs layer, 4 is an i-InGaAs layer, 5 is an n-InGaAs layer, and 6 is n ⁺ -InGaAs layer, 7 is an ohmic electrode, 8 is a gate electrode, 9b is SiO ₂ It is a membrane.
[0028]
Resistivity 2-6 × 10 ^Three On the high-resistance Si substrate 1 of about Ωcm, a GaAs layer 2 as a first compound semiconductor layer has a thickness of 150 Å, and an In layer on it. _0.02 Al _0.49 Ga _0.49 The As layer 3 is formed to 2.6 μm, and the i-InGaAs layer 4 is 1.6 μm as the second compound semiconductor layer thereon, and n-In which functions as the channel _0.2 Ga _0.8 As layer 5, n acting as contact layer ⁺ -In _0.2 Ga _0.8 As layer 6 is laminated.
[0029]
In such a compound semiconductor layer, a (100) Si substrate 1 having an off angle of several degrees in the (110) direction is placed on a carbon susceptor, and an organometallic material is thermally decomposed to form other organometallic material constituent elements. It is formed by a metal organic chemical vapor deposition method (MOCVD method) that is reacted at a high temperature. That is, first, after heat treatment at 900 to 950 ° C., the temperature was lowered to 400 to 450 ° C., and the GaAs layer 2 was grown to 150 ° C. and then heated to 620 ° C. which is a normal growth temperature. _0.02 Al _0.49 Ga _0.49 As layer 3 is grown to 2.6 μm, and then the substrate temperature is lowered to 580 ° C. _0.2 Ga _0.8 As layers 4-6 are grown. In _0.2 Ga _0.8 We have found that the As layer 4 is suitably used for stress reduction in the epitaxially grown film and contributes to the improvement of device reliability. This reason will be described later. The composition of In may be gradually changed from 0.02 to 0.2, or the In composition may be further increased by a growth method such as so-called metamorphic growth.
[0030]
In in the first semiconductor layers 2 and 3 _0.02 Al _0.49 Ga _0.49 The As layer 3 contains C (carbon) as an impurity, and this C (carbon) is In. _0.02 Al _0.49 Ga _0.49 It functions as an impurity in the As site of the As layer 3 and compensates for n-type carriers due to diffusion of Si impurities from the Si substrate 1.
[0031]
FIG. 3 shows the measurement results of the carrier density in the depth direction of the epitaxially grown film of the conventional semiconductor device and the semiconductor device of the example of the present invention by the mercury probe CV measuring device manufactured by ASEC, and the horizontal axis is the depth of 0 μm. Is selected at the interface between the Si substrate 1 and the GaAs layer 2. The measurement was performed at 100 to 200 kHz. The measurement of the carrier density in the depth direction is often difficult to measure by CV measurement by electrochemical etching due to a decrease in depth resolution, but the depth is calculated from the extent of the depletion layer. This is possible with the mercury probe CV measurement. This measurement is performed by stopping the growth when the growth to the first semiconductor layers 2 and 3 is completed, or after removing the compound semiconductor layers after the second semiconductor layers 4, 5 and 6 by etching.
[0032]
In the case of a conventional semiconductor device, 3 × 10 from the silicon substrate 1 to about 0.35 μm. ¹⁶ atoms · cm ^-3 The carrier density is 1 × 10 up to about 0.85 μm. ¹⁶ atoms · cm ^-3 The carrier density was above.
[0033]
In the embodiment of the present invention, In _0.02 Al _0.49 Ga _0.49 As a growth condition of the As layer 3, the V / III ratio defined by the ratio of the number of moles of arsine in the group V gas to the total number of moles of trimethylindium, trimethylaluminum, and trimethylgallium in the group III gas is set to 100 to 150. By defining the impurity density, 3 × 10 ¹⁶ cm ^-3 The thickness of the epitaxial growth film as described above was reduced to 0.1 μm or less.
[0034]
By forming such first semiconductor layers 2 and 3, parasitic capacitances such as MESFET and HEMT are reduced, and the high frequency characteristics are greatly improved. In this embodiment, when the gate length having a gate pad of 100 μm × 100 μm is 1 μm and the gate width is 100 μm, C _para Decreases to 0.05 pF and the current gain cutoff frequency f _T = 13 GHz, maximum oscillation frequency f _MAX = 24 GHz MESFET was obtained.
[0035]
FIG. 5A shows the output impedance S of the semiconductor device according to the embodiment of the present invention. _{twenty two} The measurement results are shown. The measurement was performed from 20 MHz to 20 GHz using a network analyzer 37369A manufactured by Wiltron. FIG. 5B shows a measurement result of a conventional semiconductor device having a GaAs layer on a Si substrate as an active layer, and FIG. 5C shows a semiconductor device having a GaAs epitaxial layer on a GaAs substrate as an active layer. It is a measurement result. As can be seen from these, the conventional semiconductor device having the GaAs layer on the Si substrate as the operation layer is greatly affected by the reactance component. This is probably due to the conductive layer at the interface. On the other hand, in the present embodiment, the first semiconductor layers 2 and 3 have a structure that compensates for n-type carriers due to diffusion of Si impurities from the substrate. _{twenty two} It can be seen that is obtained.
[0036]
Doping of the impurity C (carbon) for the purpose of increasing resistance by such compensation is performed on part of the first compound semiconductor layers 2 and 3 with In. _x Al _y Ga _1-xy As layer (0 < x ≦ 0.05, 0.2 ≦ y ≦ 0.6) 3 can be easily achieved. When the Al composition y is increased, C (carbon) is likely to enter the As site, facilitating compensation. If the Al composition y is too large, the reliability will be deteriorated due to an increase in the channel temperature of the semiconductor device. Therefore, 0.2 ≦ y ≦ 0.6 is preferably used as the Al composition. Moreover, the surface morphology of the semiconductor substrate is improved by mixing a few percent of In.
[0037]
Further, the GaAs film 2 is formed in a thickness of 100 to 200 mm on the Si substrate side in the first semiconductor layers 2 and 3, but the surface morphology deteriorates if the thickness is less than 100 mm. When the GaAs film 2 is formed in a thickness of 200 mm or more, the parasitic capacitance increases and the high frequency characteristics are deteriorated.
[0038]
In addition, when AlGaAs or the like can be grown directly on the Si substrate 1, there is a possibility that the high-frequency characteristics may work more advantageously, but the effective solidification temperature of AlGaAs (defined later) is slightly higher than that of GaAs. , Increase warping and stress. In the case of this example, In is high in Si and effective solidification temperature (defined later). _x Al _y Ga _1-xy As layer (0 < Since the GaAs layer 2 is formed in the range of 100 to 200 mm between x ≦ 0.05 and 0.2 ≦ y ≦ 0.6), the driving force of warpage and stress due to the difference in linear expansion coefficient is reduced. And advantageous in terms of stress reduction.
[0039]
Next, In _0.2 Ga _0.8 The effect of reducing stress and substrate warpage by the As layers 4, 5, and 6 will be described. By examining in detail the experimental data of warpage and stress on heteroepitaxial growth substrates of various layer structures, the effective solidification temperature defined in (2) below is In _0.2 Ga _0.8 It has been found that As layers 4, 5, and 6 become smaller. This reduction in effective solidification temperature corresponds to a reduction in stress in the epitaxially grown film. The mechanism will be described below.
[0040]
N-1 epitaxial growth layer α as shown in FIG. ₁ ~ Α _n Consider a heteroepitaxial substrate with stacked layers. Since this heteroepitaxial substrate has a very high growth temperature, dislocations can move easily, and each layer α can be generated by the generation and movement of such dislocations. ₁ ~ Α _n The stress due to the difference in the linear expansion coefficient and the stress due to the difference in the lattice constant are alleviated, the wafer is not warped and is flat, and almost no stress is generated in the epitaxially grown film. However, when the temperature falls below a certain temperature, such dislocation generation and movement do not occur, stress cannot be relaxed, and each epitaxial growth layer α ₁ ~ Α _n At the same time, a force is applied in the opposite direction, and at the same time, the wafer begins to warp and stress begins to occur. This temperature is α ₁ ~ Α _n Each layer α ₁ ~ Α _n This will be referred to as the effective solidification temperature. Each epitaxial growth layer α ₁ ~ Α _n , And the Young's modulus of the substrate in order from the top ₁ , E ₂ , E _Three ... E _n And the thickness of the epitaxially grown film is h ₁ , H ₂ , H _Three ………………, h _n And the stress σ applied to the film i _i Is the tensile stress positive,
[0041]
[Equation 5]

[0042]
(1)
Can be written. Where b is the diameter of the substrate, ρ is the radius of curvature, and y _u Is the distance from the top surface of the epitaxial growth substrate, y _m Is the position of the neutral plane, and as shown in FIG. ₁ ~ Α _n The force F that works between them was determined. The first term of (1) is the epitaxial growth layer α ₁ ~ Α _n The stress is due to the force F acting between them, and the second term is the stress due to bending. At the same time, the magnitude is b ² A warp of / 8ρ occurs.
[0043]
(1) Neutral axis position y in the equation _m Is obtained because the sum of the bending stresses in the cross section is 0,
[0044]
[Formula 6]

[0045]
It becomes. The radius of curvature ρ is the bending moment M _tot And moment of inertia of section I _i Easily obtained from
[0046]
[Expression 7]

[0047]
Can be written. Where M _tot And I _i Are bending moment and cross-sectional second moment, respectively, and can be written as follows.
[0048]
[Equation 8]

[0049]
,
[0050]
[Equation 9]

[0051]
On the other hand, in the equation (1), F is largely relaxed by the transition and crystal defects here due to the difference in lattice constant, and the sum of the strain due to the force acting between the thermal strain and the epitaxial growth layer is different in each layer. Approximate to be equal,
[0052]
[Expression 10]

[0053]
…………………………………………………………………………………… (2)
Can be written. Where ΔT _i Is the temperature difference between the effective solidification temperature and room temperature. Actually, it can be considered that a strain term due to the difference in lattice constant is added to each equation, but in the first approximation, it is considered that the thermal strain due to the difference in linear expansion coefficient is dominant, and the effective solidification temperature Can be renormalized by redefinition. (2) ΔT in the equation _i And the effective solidification temperature mentioned above must be understood as such quantity. In addition, when the effective solidification temperature of the lower layer formed earlier is low, the continuum approximation is not established until the effective solidification temperature is lower than the effective solidification temperature. Here, the solution of equation (2) is written down when n = 4 as in this embodiment.
[0054]
[Expression 11]

[0055]
[Expression 12]

[0056]
[Formula 13]

[0057]
This F ₁ ~ F _Three From (1), the stress acting on the epitaxial growth film is obtained. We compared the effective solidification temperature defined in (2) with the experimental results of warpage of various heteroepitaxial film structures, and determined the effective solidification temperature of various compound semiconductor mixed crystals. For example, the effective solidification temperature of GaAs is about 350 ° C., and In _0.2 Ga _0.8 The effective solidification temperature of As is about 240 ° C.
[0058]
In this example, the stress and the substrate warp _0.2 Ga _0.8 A description will be given in comparison with a case where a GaAs layer is used instead of the As layers 4, 5 and 6. In this example _0.2 Ga _0.8 When a GaAs layer is used instead of As4, 5 and 6, the total stress obtained from (1) (residual stress of the epitaxially grown film) is 9.2 × 10 ⁸ dyn / cm ² The warpage in the case of a 3-inch substrate is b ² / 8ρ to 79 μm. On the other hand, in this example, the total stress (residual stress of the epitaxially grown film) obtained from (1) is 2.6 × 10 6. ⁸ dyn / cm ² And the warpage in the case of a 3-inch substrate is b ² / 8ρ to 51 μm.
[0059]
In this way, In _0.2 Ga _0.8 By using As, warpage and stress are reduced by In. _0.2 Ga _0.8 This is probably because the effective solidification temperature of As is about 240 ° C., which is smaller than the effective solidification temperature of GaAs of about 350 ° C. Also, In _t Ga _1-t The effective solidification temperature of the As layers 4, 5, 6 rapidly decreases in the vicinity of t to 0.2. Therefore, when t ≧ 0.2, the residual stress of such a substrate warp and epitaxial growth film is reduced.
[0060]
FIG. 2A shows current value fluctuations in the DC energization test of the MESFET of this example. Thus, the fluctuation of the current value was smaller than that of the conventional FIG. This is probably because the decrease in the conduction band due to the pulling stress remaining in the epitaxially grown film was small in the first place, and the change in the current value due to the energization test was also small.
[0061]
Using such a semiconductor substrate, a semiconductor device including MESFET and HEMT is formed by the following process. That is, as shown in FIG. 6A, a desired mesa region is limited by normal photolithography, and etching is performed halfway through the InGaAs film 4 using a mixed solution of sulfuric acid, hydrogen peroxide, and water as an etchant. After removing the resist, a slightly smaller mesa region is formed with a photoresist, and the compound semiconductor films 5 and 6 are similarly etched. Since this etching hinders disconnection of the gate electrode, it is desirable that the etching be slightly shallower than the first etching. In this way, two-stage mesas with different heights are formed.
[0062]
Next, as shown in FIG. 6B, the entire surface of the substrate is formed by a plasma CVD method or a sputtering method. ₂ Or SiN _x O _y After forming an insulating film 9a made of, for example, about 1.5 μm and forming a photoresist opening pattern, the insulating film 9a is etched with buffer hydrofluoric acid or the like so that the compound semiconductor layer 6 on the mesa region is completely exposed. . Then, the insulating film 9a remains on the compound semiconductor layer 4, and the compound semiconductor layer 6 is exposed on the mesa region. The insulating film 9a may be etched by RIE (reactive ion etching) or CDE (chemical dry etching).
[0063]
Next, as shown in FIG. 7A, a gate electrode is formed. SiO is applied to the entire surface of the substrate using a plasma CVD method or the like. ₂ An insulating film 9b made of 0.5 μm is formed. Subsequently, a photoresist opening pattern for forming a gate electrode is formed, and as shown in FIG. ₂ The film 9b is etched. For this etching, BHF (buffered hydrofluoric acid) (HF: H ₂ O: NH _Four F = 1: 10: 10) is used. Note that wet etching from a fine opening can be easily performed by performing an ashing process using a plasma asher prior to etching and performing a pretreatment so that the etchant can enter the opening.
[0064]
Next, as shown in FIG. ⁺ -Recess etching of the InGaAs layer 6 is performed. First, an etching solution can enter the opening by ashing pretreatment, and then an aqueous solution in which sulfuric acid and hydrogen peroxide solution are mixed is used. ⁺ Etching until the InGaAs layer 6 is completely etched, and as shown in FIG. 7D, a gate electrode 8 made of Pt, Au / Pt / Ti, Au / Al / Pt, etc. Use to form. Since the gate is formed using the photoresist 10 as a mask, the gate length is determined by the opening width of the photoresist 10.
[0065]
When the gate electrode 8 is formed on the n-InGaAs layer 5 as in this embodiment, the gate electrode 8 is preferably an electrode containing Pt. The Schottky junction between the Pt-containing electrode and the InGaAs layer has a barrier height of about 1.2 eV, which is higher than the Schottky barrier height of GaAs and Al or Ti of about 0.8 eV. For this reason, when a large signal operation is performed, the current swing width can be increased and a large output can be obtained. In addition, since the degree of freedom in designing the amplifier is increased, it is possible to relatively easily form an amplifier that satisfies the linearity and the high efficiency that are in a trade-off relationship with each other.
[0066]
Thereafter, as shown in FIG. 7E, the photoresist 10 and the gate electrode 8 thereon are removed by lifting off the photoresist 10.
[0067]
Finally, an opening pattern (not shown) for forming the ohmic electrode 7 is formed on the ohmic contact layer 6, the insulating film 9b is etched with buffer hydrofluoric acid, and then AuGe / Au or AuGe is formed on the ohmic contact layer 6. A semiconductor device as shown in FIG. 1 is formed by depositing an ohmic electrode 7 made of / Ni / Au, patterning it by lift-off, and alloying it by heat treatment.
[0068]
It is obvious to those skilled in the art that the same effect can be obtained by forming an InAlAs / InGaAs or AlGaAs / InGaAs type HEMT instead of the MESFET.
[0069]
【The invention's effect】
As described above, according to the semiconductor device of the first aspect, the first compound semiconductor layer provided on the Si single crystal substrate is the GaAs layer. Contains C as an impurity In _x Al _y Ga _1-xy As layer (0 ≦ x ≦ 0.05, 0.2 ≦ y ≦ 0.6) When Therefore, the resistance of the buffer layer is increased, and the high frequency characteristics such as the current gain cutoff frequency and the maximum oscillation frequency are greatly improved. The second compound semiconductor layer formed on the first compound semiconductor layer is In _t Ga _1-t It is formed of a layer including an As layer (t ≧ 0.2). _t Ga _1-t Since the As layer (t ≧ 0.2) is used as the channel, the residual stress in the epitaxial growth film is reduced, and the excellent reliability of the semiconductor device can be ensured. At the same time, substrate warpage can be reduced, and the yield can be greatly improved.
[0070]
Further, in the semiconductor device according to claim 2, since the thickness of the GaAs layer on the Si single crystal substrate side in the first compound semiconductor layer is formed to be 100 to 200 mm, the high frequency characteristics are maintained while keeping the substrate warpage and stress small. Can be improved. In addition, a semiconductor substrate having a good surface morphology can be obtained, and the manufacturing yield of semiconductor devices can be improved.
According to the semiconductor device of the third aspect, the impurity density in the first compound semiconductor layer measured by mercury probe CV measurement is 2 × 10. ¹⁶ cm ^-3 Various growth conditions are adjusted so that the thickness of the epitaxially grown film is 0.1 μm or less, and the amount of impurities such as carbon is optimized, so that the high frequency characteristics are improved.
[0071]
Furthermore, according to the semiconductor device of claim 4, the In _t Ga _1-t Since the Schottky electrode containing Pt is formed on the As layer (t ≧ 0.2), the Schottky barrier height increases and the gate breakdown voltage increases. In addition, since the swing width during large signal operation can be increased, drain efficiency, power addition efficiency, and the like are improved, and power consumption can be reduced when a high-frequency semiconductor device is formed. Further, since the Schottky barrier height is large, an enhancement type semiconductor device having excellent characteristics can be easily formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view in a direction perpendicular to a gate electrode of a semiconductor device according to the present invention.
2A is a result of a DC energization test of a semiconductor device according to the present invention, and FIG. 2B is a result of a DC energization test of a conventional semiconductor device using GaAs on an Si substrate as an operating layer.
FIG. 3 is a measurement result of carrier density in the depth direction by mercury probe type CV measurement.
FIG. 4 is a diagram for explaining warpage and stress reduction in an epitaxially grown film.
FIG. 5A is an output impedance S of a semiconductor device according to the present invention. _{twenty two} (B) is the output impedance S of the conventional semiconductor device. _{twenty two} (C) is the output impedance S of the semiconductor device on the GaAs substrate. _{twenty two} It is a measurement result.
6A to 6B are cross-sectional views in the direction parallel to the gate electrode of the method for manufacturing a semiconductor device according to the present invention.
7A to 7E are views for explaining a method for forming a gate electrode of a semiconductor device according to the present invention.
[Explanation of symbols]
1 ... Si substrate, 2 ... GaAs layer, 3 ... InAlGaAs layer, 4 ... i-InGaAs layer, 5 ... n-InGaAs layer, 6 ... n ⁺ -InGaAs layer, 7 ... Ohmic electrode, 8 ... Gate electrode, 9 (a) ... SiO ₂ Membrane, 9 (b) ... SiO ₂ Film, 10 ... Photoresist

Claims (4)

In a semiconductor device in which a compound semiconductor layer is provided on a Si single crystal substrate, the compound semiconductor layer is formed by sequentially stacking a first compound semiconductor layer and a second compound semiconductor layer, and the first compound semiconductor layer is formed from an _{in x Al y Ga 1-xy} as layer containing C as the GaAs layer and the impurity (0 <x ≦ 0.05,0.2 ≦ y ≦ 0.6), the second compound semiconductor layer is formed of a layer containing in _t Ga _1-t as layer (t ≧ 0.2), the use of this in _t Ga _1-t as layer (t ≧ 0.2) as a channel A semiconductor device characterized by the above.   2. The semiconductor device according to claim 1, wherein the GaAs layer is formed to a thickness of 100 to 200 mm. 2. The thickness of the region where the impurity density in the first compound semiconductor layer is 2 × 10 ¹⁶ atoms · cm ⁻³ or more as measured by mercury probe CV measurement is 0.1 μm or less. The semiconductor device described. 2. The semiconductor device according to claim 1, wherein a Schottky electrode containing Pt is formed on the In _t Ga _1-t As layer (t ≧ 0.2).

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