JP3447571B2 - Field effect transistor and method for forming the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor formed on a silicon substrate using a compound semiconductor film and a method for forming the field effect transistor.

[0002]

2. Description of the Related Art A conventional manufacturing process for forming a high frequency FET by epitaxially growing a compound semiconductor on a silicon substrate and its structure are as follows.

First, a plan view of a high frequency FET is shown in FIG. Reference numeral 1 is a gate electrode, 2 is a source electrode, and 3 is a drain electrode. M is called a mesa portion and is a portion which is etched leaving an active layer of a compound semiconductor. Wg is a gate width of usually 50 μm to 200 μm, Lg is a gate length of usually 0.1 μm to 2 μm, and Lsd is a distance between the source electrode 2 and the drain electrode 3 of usually 1 μm to 10 μm. Also,
Ls and Ld are the widths of the source electrode 2 and the drain electrode 3, respectively, and are usually 10 μm to 50 μm.

To form the high-frequency FET of FIG. 8 on a silicon substrate, MOCVD or MBE is used as shown in FIG.
A buffer layer 5 made of a compound semiconductor such as GaAs, InGaAs, or InP is grown on the silicon substrate 4 so as to have a resistance as high as possible, and the carrier density is 1 × 1.
A substrate 4 is used in which an n-type active layer 6 having a density of 0 ¹⁶ to 5 × 10 ¹⁷ cm ⁻³ and an n-type contact layer 7 having a carrier density of 1 × 10 ¹⁸ cm ⁻³ or more has been grown, if necessary.

After that, the process shown in FIG.
0 or the field effect transistor shown in FIG. 11 is formed. First, the mesa region M shown in FIG. 8 is formed by mesa etching while leaving the active layer 6. Next, Ti (about 3
00Å) and Al (about 3000Å) and Au (about 3000)
Å) is vapor-deposited and lifted off to form the gate electrode 1
To form. Before forming the gate electrode 1, the compound semiconductor layer 6 may be recess-etched by using photolithography, if necessary. After forming an insulating film (not shown) such as SiO ₂ , a contact hole (not shown) is opened, and AuGe (about 1000Å) / Ni (about 3)
Source / drain electrodes 2 and 3 are formed by vapor-depositing 00Å) / Au (about 3000Å) and lifting off. After that, in hydrogen gas or nitrogen gas atmosphere, about 450 ℃
The source / drain electrodes 2 and 3 and the compound semiconductor layer 6 are ohmic-contacted by annealing for about 2 minutes. If necessary, a part of the gate electrode 1 and the source / drain electrodes 2 and 3 are Au-plated to a thickness of 2 μm to 5 μm to improve the power resistance of the FET.

[0006]

However, in such a conventional field effect transistor, silicon is automatically doped into the buffer layer 5 from the silicon substrate 4 during the growth of the compound semiconductor layers 5 and 6, and the compound semiconductor buffer layer 5 is formed. It is extremely difficult to increase the resistance of the
It was about 00 Ωcm, and since the gate electrode ′ 1 was in contact with the compound semiconductor buffer layer 5, its high frequency characteristics were significantly deteriorated.

Therefore, as shown in FIG. 11, a structure may be considered in which the compound semiconductor buffer layer 5 is entirely etched except for the mesa M, but the resistivity of the silicon substrate 4 is 1000 to 10000 Ωcm even if it is high. However, it is insufficient for insulating the gate electrode 1. Further, the buffer layer 5 is usually required to have a thickness of 1 μm or more, the step of the mesa M is large, the electrode widths of the gate electrode ′ 1, the source / drain electrodes 2 and 3 vary widely, and the element characteristics become non-uniform. Or, the wire was broken and the yield was greatly reduced.

The present invention has been made in view of the problems of the prior art as described above, and the deterioration of the high frequency characteristics caused by the auto-doping of the buffer layer with silicon and the region other than the mesa portion of the buffer layer. It is an object of the present invention to provide a field effect transistor that eliminates disconnection, insulation failure, and non-uniformity of characteristics that occur due to removal of all of the above.

[0009]

In order to achieve the above object, in the field effect transistor according to claim 1, a buffer layer and an active layer are provided on a silicon substrate, and a gate electrode and a source / drain are provided on the active layer. in a field effect transistor provided with an electrode, provided with a _{Al x Ga 1-x as (} 0.9 ≦ x ≦ 1) layer oxidized between the buffer layer and the active layer, the oxidized _Al x _{Ga 1- The} impurity concentration is 1 × 10 ¹⁶ at between the _x As layer and the active layer.
Al _y Ga _1-y As (0 ≦ y <of ms · cm ⁻³ or less)
0.9) layer was provided.

In the method of manufacturing a field effect transistor according to a second aspect of the present invention, a field effect transistor in which a buffer layer and an active layer are formed on a silicon substrate and a gate electrode and source / drain electrodes are formed on the active layer. Forming a buffer layer on the silicon substrate.
As layer, Al _x Ga _1-x having a thickness of 500 Å or more
An As (0.9 ≦ x ≦ 1) layer and a layer to be an active layer are formed, and the Al _x Ga is formed on the back surface of the silicon substrate.
A hole reaching the _1-x As layer is formed, and this Al _x Ga is formed.
_{The 1-x} As layer is wet-oxidized, and then the gate electrode and the source / drain electrodes are formed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the invention according to claims 1 and 2 will be described below. FE according to these inventions
A plan view of T is shown in FIG. 1, and a sectional view thereof is shown in FIG. 6 (A-A sectional view of FIG. 1). In FIG. 6, '8 is Al of 500 Å or more
_x Ga _1-x As (0.9 ≦ x ≦ 1) layer, which exhibits a specific resistance of 1 × 10 ⁵ Ωcm or more by the wet oxidation described later, and the active layer 6, the gate electrode 1 and the substrate 4
It is possible to significantly improve the insulation property between Further, since the hole 9 is formed in the back surface of the silicon substrate 4 by etching and the Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer is wet-oxidized therethrough, the step of the mesa M is significantly reduced. be able to.

First, as shown in FIG. 2, the GaAs buffer layer 5 is grown to 0.2 to 2 μm on the silicon substrate 4 by the ordinary two-step growth method by MOCVD or MBE. Since compound semiconductors such as GaAs, InGaAs, and InP are formed using a large-diameter silicon substrate of 4 inches or more, which is excellent in mechanical strength, the reduction in manufacturing yield due to cracking of the substrate can be greatly improved. Moreover, since silicon having a good thermal conductivity is used for the substrate, the heat dissipation of the FET can be greatly improved. The thermal conductivity of silicon is 1.45 watt / cm ° C. at 300K.

Next, 0.05 to 5 μm of Al _x Ga is used.
After growing the _1-x As (0.9 ≦ x ≦ 1) layer 8, an n-type GaAs layer 6 serving as an active layer having an electron density of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ is grown to 1000 to 5000 Å. To do. The electron density and film thickness of the active layer 6 are appropriately selected according to the desired FET characteristics. Furthermore, in order to reduce ohmic resistance with the source electrode and the drain electrode as necessary, the electron density is 5 × 10 ¹⁷ to
N-type GaA forming a contact layer of 2 × 10 ¹⁸ cm ⁻³
The s layer 7 may be grown to 100 to 2000Å.

Thereafter, as shown in FIG. 3, several hundreds of μm square or round holes 9 are formed on the back surface of the silicon substrate 4 by using RIE as a mask or photoresist such as SiN _x or SiO _2.
(Reactive Ion Etching) etc. A of 0.05-5 μm
Etching is performed up to the l _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 8. The silicon substrate 4 is also etched by RIE.
The substrate 4 is placed in a quartz tube furnace (not shown) for wet oxidation of the Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 8. Then, by bubbling nitrogen into the ultrapure water in a constant temperature bath at about 90 ° C. for 1 to 10 liters / minute, the vapor of the ultrapure water is supplied into the quartz tube to 400 to 500.
A shown in FIG. 4 was obtained by heating at 0 ° C. and oxidizing for 1 to 10 hours.
l _x Ga _1-x As (0.9 ≦ x ≦ 1) Oxide layer of layer 8 ′
Get 8. In addition, the time and temperature required for oxidation are Al _x G
a _1−x As (0.9 ≦ x ≦ 1) depends on the film thickness of the layer 8, the Al composition x, and the opening area of the hole 9, but the opening area of the hole 9 is 0.04 mm 2 and the film thickness of AlAs ′ 8 is At 1000Å, AlAs layer'8 by wet oxidation at 400 ° C for 3 hours
Oxidation is completed. In this case, it is Al _x G that is oxidized.
The entire portion of the a1 _- xAs (0.9≤x≤1) layer 8 is not oxidized. The oxidation temperature is 400 to 5
Since the temperature is as low as 00 ° C., the silicon substrate 4 is hardly oxidized. Further, when the film thickness of the Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 8 is less than 500 Å, the cross-sectional area in which oxidation proceeds becomes small, and when the Al composition x is less than 0.9. Is not practical because the compound that is oxidized is reduced and the oxidation time is long.

Next, in order to form the mesa region M shown in FIG. 1, a photoresist is formed in the region of the mesa region'M.
Using this photoresist as a mask, the contact layer 7 and the active layer 6 are etched with a sulfuric acid-based etchant to form the mesa region'M in FIG. After forming the mesa region'M,
By depositing Ti (about 300 Å), Al (about 3000 Å) or Au (about 3000 Å) and lifting off, the gate electrodes 1 and 1 are formed. In addition, the gate electrode 1, '
Before forming No. 1, recess etching of the compound semiconductor layer may be performed by using photolithography, if necessary.

[0016] Next, after forming an insulating film such as SiO ₂ (not shown), a contact hole (not shown), A
uGe (about 1000Å) / Ni (about 300Å) / Au
After the source electrode 2 and the drain electrode 3 are formed by depositing (about 3000 Å) and lifting off, the source electrode 2 and the drain electrode 3 are annealed at about 450 ° C. for about 2 minutes in a hydrogen gas or nitrogen gas atmosphere. An ohmic contact is made between the compound semiconductor layers. Further, if necessary, a part of the gate electrodes 1 ′ ′ and the source / drain electrodes 2 and 3 are Au-plated until the film thickness becomes 2 μm to 5 μm.
Improves ET power resistance. As described above, the field effect transistor shown in FIG. 6 is formed.

Further, as shown in FIG. 7, the active layer 6 and Al _x Ga are formed.
_1-x As (0.9 ≦ x ≦ 1) oxide layer 8 and undoped Al _y Ga _1-y As (0 ≦ y <0.9) layer 1
Insert 0. In this way, the active layer 6 and Al _x Ga _1-x
By inserting the undoped Al _y Ga _1-y As (0 ≦ y <0.9) layer 10 between the As (0.9 ≦ x ≦ 1) oxide layer 8 and the electrons in the active layer 6. Mobility can be increased and high frequency characteristics can be further improved. That is, by inserting the undoped Al _y Ga _1-y As (0 ≦ y <0.9) layer 10 having a bandgap energy Eg larger than that of the active layer 6, the effect of confining electrons in the active layer 6 is increased. It was oxidized _Al x _{Ga 1-x} As
By improving atomic smoothness at the interface between (0.9 ≦ x ≦ 1) ′ 8 and the active layer 6, the mobility of electrons in the active layer 6 is improved, and the high frequency of the field effect transistor is improved. This is to improve the characteristics.

[0018]

As described above, according to the field effect transistor of the first aspect, the Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer oxidized between the buffer layer and the active layer is formed. Since the gate electrode, the source electrode, the drain electrode, and the active layer are electrically isolated from the silicon substrate by the wet oxide film of the Al _x Ga _1-x As layer, these electrodes are provided. The parasitic capacitance between the pad portion and the compound semiconductor buffer layer or the silicon substrate can be reduced, and the high frequency characteristics can be significantly improved. In addition, the step difference in the mesa region can be reduced to the film thickness of the active layer, and it is possible to greatly reduce the inconvenience that the electrode widths of the gate electrode and the source / drain electrodes are varied or the wire is disconnected at the step portion of the mesa region. Further, the active layer and the _{Al x Ga 1-x As (} 0.9
≦ x ≦ 1) and an oxide layer of undoped Al _y Ga
_{Since the 1-y} As (0 ≦ y <0.9) layer is provided, the mobility of electrons in the active layer can be increased and the high frequency characteristics can be further improved.

According to the method of manufacturing a field effect transistor according to the second aspect, a GaAs layer serving as a buffer layer on a silicon substrate and Al _x G having a thickness of 500 Å or more.
a _1-x As (0.9 ≦ x ≦ 1) layer and a layer to be an active layer are formed, and the Al _x G is formed from the back surface of the silicon substrate.
A hole reaching the a _1-x As layer is formed, and this Al _x G
Since the a _1-x As layer is wet-oxidized and then the gate electrode and the source / drain electrodes are formed, the oxidized Al _x Ga _1-x As is formed between the buffer layer and the active layer.
Can be easily formed, and the step of the mesa can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a field effect transistor of the present invention.

FIG. 2 is a cross-sectional view of an epitaxial layer of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the field effect transistor of the present invention.

FIG. 4 is a cross-sectional view of the manufacturing process of the field effect transistor of the present invention.

FIG. 5 is a cross-sectional view of the manufacturing process of the field effect transistor of the present invention.

FIG. 6 is a cross-sectional view of the field effect transistor of the present invention.

FIG. 7 is a cross-sectional view of the field effect transistor of the present invention.

FIG. 8 is a plan view of a conventional field effect transistor.

FIG. 9 is a sectional view of an epitaxial layer of a conventional example.

FIG. 10 is a cross-sectional view of a conventional field effect transistor.

FIG. 11 is a cross-sectional view of a conventional field effect transistor.

[Explanation of symbols]

1; gate electrode, '1; gate electrode pad portion, 2; source electrode, 3; drain electrode, 4; high resistance silicon substrate, 5; high resistance GaAs buffer layer, 6; GaAs active layer, 7; GaAs contact layer , 8; Al _x Ga
_1-x As (0.9≤x≤1) layer, '8; Wet-oxidized Al _x Ga _1-x As (0.9≤x≤1) layer,
9: Hole for wet oxidation 10: Undoped Al _y
Ga _1-y As (0 ≦ y <0.9) layer

Continuation of front page (56) References JP-A-6-208963 (JP, A) C.I. B. Wheeler et. a. , Selectively Oxidized GaAs MESFET's Transferred to a Si Substrate, IEEE Electron Device Letters, USA, April 1997, Vol. 18, No. 4, p. 138-140 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/203-21/205 H01L 29/778 H01L 29/812 INSPEC (DIALOG)

Claims (2)

(57) [Claims] 1. A field effect transistor having a buffer layer and an active layer provided on a silicon substrate, and a gate electrode and source / drain electrodes provided on the active layer, wherein Al oxidized between the buffer layer and the active layer. _x Ga _1-x As
(0.9 ≦ x ≦ 1) layer provided Rutotomoni and this oxidation
Impurity concentration is increased between the Al _x Ga _1-x As layer and the active layer.
Degree is 1 × ¹⁰ 16 atoms · ^{cm -3} or less of _Al y G
A field-effect transistor comprising an a1 _- yAs (0≤y <0.9) layer . 2. A method of forming a field effect transistor, comprising forming a buffer layer and an active layer on a silicon substrate, and forming a gate electrode and a source / drain electrode on the active layer, wherein the buffer layer and the active layer are formed on the silicon substrate. GaAs
Layer, Al _x Ga _1-x As having a thickness of 500 Å or more
A (0.9 ≦ x ≦ 1) layer and a layer to be an active layer are formed, and the Al _x Ga _1-x is formed from the back surface of the silicon substrate.
A hole reaching the As layer is formed, and this Al _x Ga _{1-x is formed.}
A method of forming a field effect transistor, characterized in that the As layer is wet-oxidized, and then the gate electrode and the source / drain electrodes are formed.