JP3515913B2 - Semiconductor substrate and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method for forming the same, and more particularly to a semiconductor substrate having a compound semiconductor layer formed on a single crystal substrate and a method for forming the same.

[0002]

2. Description of the Related Art Electronic devices using compound semiconductors of Group III-V of the periodic table such as gallium arsenide can operate at higher speeds and higher frequencies than devices using silicon. Since it is possible, its use for electronic devices such as microwave devices and millimeter wave devices is expanding. However, a bulk compound semiconductor substrate made of only a compound semiconductor has a small diameter of 3 to 4 inches, a large diameter of about 5 to 6 inches, and a high price, which is 6 to 8 inches or even 12 inches. It is difficult to mass-produce a semiconductor device formed on the silicon substrate and to develop the semiconductor device in the future, as compared with a silicon substrate which has a large diameter and is inexpensive.

Therefore, what is drawing attention is a compound semiconductor substrate of heteroepitaxial growth in which a compound semiconductor layer is epitaxially grown on a silicon substrate. By epitaxially growing a compound semiconductor on a silicon substrate, it is possible to increase the diameter of a substrate having a compound semiconductor layer and reduce the cost. In addition, a substrate in which a compound semiconductor layer is formed on a silicon substrate has excellent mechanical strength and high thermal conductivity, and thus has features such as excellent heat dissipation when a semiconductor device is formed. Further, since a compound semiconductor material such as gallium arsenide has both optical characteristics and electrical characteristics, if an excellent crystalline compound semiconductor can be grown on a silicon substrate, MESFET (metal semiconductor field effect transistor) or HEMT (high electron mobility) can be obtained. It is also possible to realize an optical / electronic hybrid device in which an optical element such as an LED or an LD as well as an electronic element such as a transistor is manufactured on the same substrate.

A semiconductor substrate having a compound semiconductor formed on a silicon substrate has many merits as described above.
When a compound semiconductor layer made of a group III-V element such as gallium arsenide is heteroepitaxially grown on a substrate made of a group IV element such as silicon, the substrate temperature during growth is high in the initial stage of growth of the compound semiconductor layer. The silicon atom of the substrate material diffuses into the compound semiconductor layer, and this acts as a dopant for the compound semiconductor to reduce the resistance of the compound semiconductor layer, resulting in deterioration of device characteristics using the compound semiconductor layer.

A second compound semiconductor layer is further formed on the compound semiconductor layer formed on the silicon substrate.
When the compound semiconductor layer of 1 is used as the operating layer of the device, the compound semiconductor layer formed directly on the silicon substrate does not have a resistance sufficiently higher than that of the second compound semiconductor layer. Deterioration or insufficient element isolation between devices to integrate elements (IC)
Was making it difficult. For example, in an FET, the pinch-off characteristic is deteriorated, the threshold is shifted, and the drain conductance is increased, so that the performance of the element is deteriorated. Further, when the elements are highly integrated, the isolation characteristics of the elements are deteriorated due to the generation of leakage current between the elements, and the operation failure of the integrated circuit,
This causes performance degradation such as increased power consumption and increased delay time.

The present invention has been made based on such a background, and a field effect transistor in which the resistance of a compound semiconductor layer epitaxially grown on a single crystal substrate is lowered or the crystallinity is impaired is provided. An object is to provide a method for forming the same.

[0007]

In order to achieve the above object, the semiconductor substrate according to claim 1 is a semiconductor substrate in which a buffer layer made of a compound semiconductor and an active layer are provided on a single crystal substrate. Al _x Ga _1-x As
(0 ≦ x ≦ l) and a bottom region having an Al composition ratio of x <0.8 on the surface and a small upper region formed on the bottom region. An oxide layer was provided on the bottom region side.

Further, in the method for manufacturing a semiconductor substrate according to the third aspect of the present invention, Al _x Ga _1- having a region where the Al composition ratio is x <0.8 and a region where x> 0.9 is formed on the single crystal substrate. forming an _x- As layer, forming an active layer made of a compound semiconductor on the Al _x Ga _1-x As layer, and extending to a region where the composition ratio of Al between the active layer and the buffer layer is x <0.8. After etching away, the region where the Al composition ratio is x> 0.9 or more is oxidized.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the invention according to each claim will be described in detail below. FIG. 1 is a sectional view of a semiconductor substrate showing an embodiment of the semiconductor substrate according to claim 1.
Is a single crystal substrate, 2 is a buffer layer, and 3 is an active layer.

In the present invention, the single crystal substrate 1 such as silicon or sapphire is used as the substrate for forming the compound semiconductor layer. When the single crystal substrate 1 such as silicon or sapphire is used as the substrate for forming the compound semiconductor layer, a substrate having a large mechanical strength of 4 inches or more can be used, which results from cracking of the substrate. The decrease in manufacturing yield can be significantly improved. Further, the thermal conductivity of silicon (Si) is 1.45 watts at 300K.
Since it is as good as / cm ° C, the heat dissipation of the FET can be greatly improved.

On this single crystal substrate 1, Al _x Ga _{1-x is formed.}
The buffer layer 2 made of As (0 ≦ x ≦ l) is 0.2 to 4
It is formed to a thickness of μm. The buffer layer 2 is composed of bottom regions 2a and 2b having a large area and upper regions 2c and 2d having a small area. The bottom regions 2a and 2b have a film structure in which Al is gradually increased so that the Al composition ratio is changed from x = 0 to x = 0.8, and at the interfaces with the upper regions 2c and 2d, An Al _x Ga _1-x As layer 2b having an Al composition ratio of x <0.8 is arranged. The upper region is composed of the oxide layer 2c and the upper layer 2d. This oxide layer 2c is made of Al _x Ga _1-x As (0.9 ≦ x
It is formed by oxidizing <1) and has a specific resistance of 10 ⁵ Ωcm or more.

As described above, when the oxidized Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 8 is formed in the buffer layer 2, the single crystal substrate 1, the active layer 3 and the gate electrode (not formed) are formed. Insulation with (shown) is significantly improved. As a result, the leakage of current to the buffer layer 2 side is eliminated, the mutual conductance is increased, the noise characteristic is improved, and the stray capacitance is reduced to improve the high frequency characteristic.

In this case, Al _x Ga _1-x As (0.9 ≦
x ≦ 1) The layer 2c is formed to have a film thickness of, for example, about 0.1 μm. Al _x Ga _1-x As (0.9 ≦ x ≦ 1)
When the thickness of the layer 2c is less than 0.05 μm or when the Al composition x
Is less than 0.9, the oxidation time becomes long and it is not practical.

On the oxide layer 2c, Al _y Ga _1-y As (0
≦ y <0.9) Layer 2d is formed. This Al _y G
The a _1-y As (0 ≦ y <0.9) layer 2d is made of Al _x Ga.
_{The 1-x} As (0.9 ≦ x ≦ 1) layer 2c serves to absorb As segregated during oxidation. That is, Al _x Ga
_1-x As (0.9 ≦ x ≦ 1) Avoids the inconvenience that As segregated during oxidation of the layer 2c is mixed into the active layer 3, improves the mobility of electrons in the active layer 3, and improves high frequency characteristics. To improve.

An active layer 3 is formed on the buffer layer 2. The active layer 3 is made of, for example, GaAs and has an electron density of, for example, about 1 to 5 × 10 ¹⁷ atoms · cm ⁻³ . This active layer 3 has a thickness of 1000 to 5000.
It is formed with a thickness of about Å. The electron density and the film thickness of the active layer 3 are appropriately selected according to the desired characteristics of the FET. Further, if necessary, in order to reduce ohmic resistance with the source electrode and the drain electrode, n-type GaA having an electron density of 5 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ^−3.
A contact layer (not shown) composed of an s layer or the like and having a thickness of about 100 to 2000 Å may be provided.

Next, a method of forming the semiconductor substrate as described above will be described. First, as shown in FIG. 2, the compound semiconductor layers 2 and 3 are formed. That is, Al _x Ga _1-x As (0 ≦ x <0..0) is formed on the single crystal substrate 1 made of silicon or the like by the MOCVD method or the MBE method using the ordinary two-step growth method.
8) a layer of the bottom regions 2a, 2b of 0.2-2 μm
Grow to the thickness of. Next, Al _x Ga _1-x As (0.
9 ≦ x ≦ 1) Layer 2c is grown to a thickness of 0.05 to 1 μm. Next, the Al _x Ga _1-x As (0 ≦ x <0.9) layer 2d is grown to a thickness of 0.1 to 1 μm. Next, an n-type GaAs layer serving as the active layer 3 having an electron density of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ is grown to 1000 to 5000 Å. Further, if necessary, in order to reduce the ohmic resistance with the source electrode and the drain electrode, an n-type GaAs to be a contact layer (not shown) having an electron density of 5 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ^−3. The layer is grown to 100-2000Å.

Next, as shown in FIG. 1, the active layer 3, Al
_x Ga _1-x As (0 ≦ x <0.9) layer 2d, and Al
_{The x} Ga _1-x As (0.9 ≦ x ≦ 1) layer 2c is mesa-etched. At this time, using a normal photolithography, a desired mesa region is masked with a photoresist, and a mixed solution of tartaric acid, hydrogen peroxide solution, and water is used as an etchant.
Etching is performed up to the l _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 2c. In this case, Al _x Ga _1-x As (0.9 ≦ x
≦ 1) In the lower part of the layer 2c, this Al _x Ga _1-x As is formed.
(0.9 ≦ x ≦ 1) Al _x Ga having an Al composition ratio of x <0.8 so as to have etching selectivity with respect to the layer 2c.
_{Since the 1-x} As (0 ≦ x <0.8) layer 2a is formed, the Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 2c is formed.
Can be accurately etched.

With the above etchant, the active layer 3 and Al
_When the etching rate of the _x Ga _1-x As (0 ≦ x <0.9) layer 2d becomes extremely small, the active layer 3 and Al _x Ga
_In order to shorten the etching time of the _1-x As (0 ≦ x <0.9) layer 2d, a general mixed solution of sulfuric acid, hydrogen peroxide and water is used as an etchant, and the active layer 3 and Al _x Ga _{1- x} A
It is also possible to perform selective etching using an etchant of the above-mentioned mixed solution of tartaric acid, hydrogen peroxide, and water after performing etching halfway through the s (0 ≦ x <0.9) layer 2d.

Next, Al _x Ga _1-x As (0.9 ≦ x ≦
1) Wet oxidation of the layer 2c is performed. First, the single crystal substrate 1
Is put in a quarantine furnace of a quartz tube. Next, by bubbling nitrogen into the ultrapure water in a thermostat at about 90 ° C. for 1 to 10 liters / minute, the ultrapure water vapor is supplied into the quartz tube. Quartz tube is heated to 400-500 ℃, 1-1
By oxidizing for 0 hour, Al _x Ga _1-x As (0.9 ≦ x
≤1) An oxide layer of layer 2c is obtained. The time and temperature required for the oxidation are different depending on the film thickness, the Al composition x, and the width of the Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 2c, but when the width is 100 μm, the Al _x Ga _{1-x is} When the thickness of the As (0.9 ≦ x ≦ 1) layer 2c is 1 μm, Al _x Ga _1-x As (0.9 ≦ x ≦) under the active layer 3 is formed by wet oxidation at 400 ° C. for 3 hours. 1) Layer 2
The oxidation of c is complete. In this case, AlAs is oxidized towards the inside of the layer to a thickness of a few hundred μm, whereas GaAs is not. Therefore, the active layer 3 and the like are not oxidized. The Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 2
When the film thickness of c is less than 0.05, or the Al composition x is 0.9.
When it is less than 1, the oxidation time becomes long and it is not practical.

[0020]

As described above, according to the semiconductor substrate of the first aspect, the buffer layer is made of Al _x Ga _1-x As (0 ≦ x
≦ l) and the composition ratio of Al on the surface is x <
The upper region of the buffer layer has an extremely high resistance because it is composed of a bottom region of 0.8 and a small upper region formed on this bottom region, and an oxide layer is provided on the bottom region side of this upper region. And there is no leakage current to the buffer layer side,
The transconductance and noise characteristics are improved, and the stray capacitance is reduced, resulting in a field effect transistor having excellent high frequency characteristics.

Further, in the method for manufacturing a semiconductor substrate according to the third aspect of the present invention, Al _x Ga _1- having a region where the Al composition ratio is x <0.8 and a region where x> 0.9 is formed on the single crystal substrate. forming an _x- As layer, forming an active layer made of a compound semiconductor on the Al _x Ga _1-x As layer, and extending to a region where the composition ratio of Al between the active layer and the buffer layer is x <0.8. After etching away, the region where the Al composition ratio is x> 0.9 or more is oxidized, so that even the oxide layer can be accurately etched, the height of the mesa can be suppressed low, and the unevenness of the device can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor substrate according to claim 1 and claim 2.

FIG. 2 is a cross-sectional view showing an embodiment of a method of manufacturing a semiconductor substrate according to claim 3.

[Explanation of symbols]

1 ... Single crystal substrate, 2 ... Buffer layer, 2a, 2b
……… Bottom area, 2c, 2d ……… Top area, 2c ……
… Oxide layer, 3 ……… Active layer

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/205 H01L 21/308 H01L 21/338 H01L 29/812

Claims (3)

(57) [Claims] 1. A semiconductor substrate having a buffer layer made of a compound semiconductor and an active layer on a single crystal substrate, wherein the buffer layer is made of Al _x Ga _{1 -x} As (0 ≦ x ≦ l) and has a surface. Characterized in that it is formed by a bottom region having a composition ratio of Al of x <0.8 and a small upper region formed on the bottom region, and an oxide layer is provided on the bottom region side of the upper region. And semiconductor substrate. 2. The semiconductor substrate according to claim 1, wherein the oxide layer has a thickness of 0.05 to 1 μm. 3. A composition ratio of Al is x <x on a single crystal substrate.
Al _x Ga having a region of 0.8 and a region of x> 0.9
_A region in which a _1-x As layer is formed, an active layer made of a compound semiconductor is formed on the Al _x Ga _1-x As layer, and the Al composition ratio of the active layer and the buffer layer is x <0.8. A method of manufacturing a semiconductor substrate, comprising: oxidizing a region where the Al composition ratio is x> 0.9 or more after etching and removing the upper part.