JP3405684B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a field effect transistor having a compound semiconductor layer formed on a silicon substrate as an operating layer.

[0002]

2. Description of the Related Art Semiconductor devices using compound semiconductors are generally capable of operating at higher speeds and higher frequencies than silicon semiconductors.
Used as a high-speed and high-frequency transistor for high-speed digital signal processing or microwave amplification.
(Metal Semiconductor) FET and HEMT (High Elec
Its fields of use, such as tron Mobility Transistor, are gradually expanding.

Nevertheless, the diameter of the bulk substrate made only of the compound semiconductor is still about 3 to 4 inches, which is formed on the silicon substrate, which is larger in diameter and lower in price than the silicon substrate. This is one of the factors that make mass production of semiconductor devices difficult.

Therefore, a compound semiconductor substrate in which a III-V group compound semiconductor layer is epitaxially grown on a silicon substrate by an epitaxial growth method is drawing attention. By epitaxially growing a compound semiconductor on a silicon substrate, it is possible to increase the diameter of a substrate having a compound semiconductor layer and reduce the cost. In addition, a substrate in which a compound semiconductor layer is formed on a silicon substrate has characteristics such as excellent mechanical strength and high thermal conductivity, excellent heat dissipation when a semiconductor device is formed, and easy handling. . In addition, since compound semiconductors have both optical and electrical characteristics, if an excellent crystalline compound semiconductor layer can be grown on a silicon substrate, electronic devices such as MESFETs and HEMTs and L
It is also possible to manufacture an optical / electronic hybrid device in which optical devices such as ED and LD are manufactured on the same substrate.

However, a disadvantage of the compound semiconductor substrate in which the compound semiconductor is formed on the silicon substrate is that a silicon atom is formed in the compound semiconductor layer due to the temperature history at the initial growth when the compound semiconductor layer is heteroepitaxially grown on the silicon substrate. However, there is a problem that the compound semiconductor layer is diffused and invaded, and serves as a dopant for the compound semiconductor to lower the resistance of the compound semiconductor layer, thereby deteriorating the device characteristics.

That is, when a compound semiconductor is laminated on a silicon substrate to form a field effect transistor having this compound semiconductor layer as an operating layer, the interface between the silicon substrate and the compound semiconductor does not have sufficiently high resistance. It causes deterioration of pinch-off characteristics, shift of threshold value, increase of drain conductance, and deterioration of device performance.
Further, when the elements are highly integrated, performance degradation such as deterioration of isolation characteristics of the elements, malfunction of the integrated circuit, increase of power consumption, increase of delay time and the like are brought about.

Then, the literature, CB Wheeler et al .; IE
EE ELECTON DEVICE LETTERS VOL.18. NO4, (1997) is a GaAs MESFET using a conductive GaAs substrate.
A technique to form an AlAs layer just below the channel, mesa-etch to the AlAs layer, and wet-oxidize AlAs to electrically separate the channel portion from the conductive GaAs substrate and then polish and bond it to the silicon substrate. Is disclosed.

However, in the above document, the gate length is 3
It has been reported that a decrease in the current value and the transconductance gm is observed in the MESFET having a μm and a gate width of 100 μm. In a MESFET with a gate length of 3 μm formed on a GaAs substrate, the mutual conductance gm
Is usually 70 to 90 mS / mm, but the ME of the above document
The maximum value of the SFET is only about 50 mS / mm, and the uniformity with respect to the gate voltage Vgs is poor. Also, a clear decrease in drain current is seen.

The cause of the characteristic deterioration when the AlAs layer is provided immediately below the channel and is oxidized will be briefly described below.
The cause of the decrease in drain current when an oxidized AlAs layer is formed directly under the channel is that CB Wheeler et al. Formed the AlAs layer directly under the channel. Therefore, the influence of the state of the interface between the GaAs channel and the oxidized AlAs is considered. He points out that he may have received it.

However, as a result of intensive studies by the present inventors, the characteristics of the transistor are deteriorated when the oxidized AlAs layer is formed immediately below the channel because the donor in the channel layer is inactivated by heat treatment. It was discovered that this was due to a decrease in mobility. That is, when forming an oxidized AlAs layer directly under the channel, ultrapure water and A
Hydrogen radicals and the like are generated by the chemical reaction with 1As to form strong bonds between Si _{Ga and} H in the channel, and the Si _{Ga and} As bonds are greatly extended and weakened. As a result of this lattice relaxation, the shallow donor level of Si _Ga disappears and becomes electrically inactive, and despite the good pinch-off characteristics, a decrease in drain current due to a decrease in carrier density is observed, and the transconductance is reduced. It is thought that this is because it caused a decrease in

Here, the well-known InAlAs
It is presumed that a phenomenon similar to the inactivation of the donor by the heat treatment at 350 ° C. or higher in the In / InGaAs mixed crystal system (the silicon in the InAlAs layer is bound to fluorine and is inactivated during the heat treatment).

The present invention has been made in view of the above problems of the prior art. The donor in the channel layer or the electron supply layer is an Al _x Ga _1-x As layer (0.9 ≦ x ≦).
It is an object of the present invention to provide a field effect transistor and a method for manufacturing the same, which solves the problem caused by inactivation during the heat treatment of 1).

[0013]

To achieve the above object, in a field effect transistor according to a first aspect of the present invention, a buffer layer made of a compound semiconductor and a channel layer are laminated on a silicon substrate and the channel is formed. In a field effect transistor in which a gate electrode is formed on a layer, Al _x Ga _1-x As (0.9 ≦ x ≦ 1) in the buffer layer
And an impurity diffusion prevention layer having an electron affinity larger than that of the channel layer is provided between the oxide film and the channel layer.

Further, in the field effect transistor according to claim 3, a buffer layer made of a compound semiconductor and a channel layer are laminated and formed on a silicon substrate, and a gate electrode is formed on the channel layer. , Al _x Ga _1-x As in the buffer layer
An oxide film of (0.9 ≦ x ≦ 1) is provided, and one or more pairs of compound semiconductor layers having different electron affinities are alternately laminated between the oxide film and the channel layer. An impurity diffusion prevention layer was provided.

Further, in the method of manufacturing a field effect transistor according to the present invention, an electric field for forming a gate electrode on the channel layer after the buffer layer and the channel layer made of a compound semiconductor are laminated on the silicon substrate. In the method of manufacturing an effect transistor, an Al _x Ga _1-x As layer of 500 Å or more (0.9 ≦ x ≦ is formed on the silicon substrate.
After forming a buffer layer and a channel layer containing 1), an insulating film is formed on a region where a transistor is formed, and the other region is formed on the Al _x Ga _1-x As layer (0.9 ≦ x ≦).
After etching to 1), the remaining Al _x Ga
_{The 1-x} As layer (0.9 ≦ x ≦ 1) is wet-oxidized.

[0016]

1 is a sectional view of an embodiment of a field effect transistor according to claim 1. Undoped GaAs layers 2, 4 and 6 of 0.1 μm to 2 μm on the high resistance silicon substrate or the n-type Si substrate 1, an AlAs oxide film 3, and undoped In _0.2 Ga _0.8 between the undoped GaAs layers 4 and 6. A buffer layer is formed by inserting about 100 Å the As layer 5, and n serving as an operation layer is formed thereon.
A -GaAs active layer 7 and an n ⁺ -GaAs contact layer 8 are formed, and ohmic electrodes 10 and 11 are formed on the contact layer 8 and a gate electrode 12 is formed on the active layer 7. Thus, the In _y Ga _1-y As (y = 0.2) layer 5 was formed between the AlAs layer 3 and the channel layer 7. The thickness of the In _y Ga _1-y As layer 5 is smaller than the thickness at which dislocations occur due to lattice mismatch, but if the thickness is too small or the In composition y is too small, Macroscopically, it is equivalent to the case where only the GaAs layer is used, and the characteristic deterioration cannot be reduced. Therefore, the In composition y and the film thickness are selected within a range where mobility deterioration in the channel does not occur. Also, two or more In _y Ga _1-y As layers 5 may be inserted.

The In _y Ga _1-y As layer 5 plays a role of a diffusion preventing layer for hydrogen radicals, which are impurities, and effectively forms a strong bond between Si _{Ga and} H in the channel. It can be prevented and donor inactivation due to heat treatment does not occur.

In the above embodiment, GaAs is used as the channel layer 7.
Although the example in which InGaAs is used as the impurity diffusion preventing layer 5 such as hydrogen radicals has been described above, the impurity diffusion preventing layer 5 may have any electron affinity higher than that of the channel layer 7. The electron affinity χe is defined by the energy difference between the vacuum level and the bottom of the conduction band. The insertion of such a layer prevents diffusion of hydrogen radicals and the like. For example, when an In _0.15 Ga _0.85 As layer is used for the channel layer, In
_{A 0.35} Ga _0.65 As layer or the like may be inserted.

FIG. 2 is a sectional view showing an embodiment of the field effect transistor according to claim 3. On the high resistance silicon substrate or the n-type Si substrate 1, an undoped GaAs layer 2 of 0.1 μm to 2 μm, an oxidized AlAs layer 3, and 15 GaAs and Al _0.2 Ga _0.8 As, respectively.
A buffer layer is formed in the order of a superlattice layer 13 formed by inserting three pairs of 0 to 300Å into each other, and an n-GaAs active layer 7 serving as an operating layer and an n ⁺ -GaAs layer are formed thereon.
The contact layer 8 is formed, the ohmic electrodes 10 and 11 are formed on the contact layer 8, and the gate electrode 1 is formed on the active layer 7.
2 is formed.

As described above, the AlAs layer 3 and the channel layer 7 are formed.
And GaAs and Al _0.2 Ga _0.8 As of 150 to 300 Å are inserted in three pairs each to form an impurity diffusion preventing layer 13 such as hydrogen radicals.

As such an impurity diffusion preventing layer 13, a superlattice layer in which one or more pairs of compound semiconductor layers of two or more kinds having different electron affinities χe are alternately formed is used. For such an impurity diffusion prevention layer 13, a compound semiconductor whose lattice constants do not differ greatly is preferably used.

FIG. 3 shows the electron affinity χ e (e
V) and the lattice constant d (Å) are shown. As can be seen from FIG. 3, in addition to AlGaAs / GaAs, for example, InP / I
nGaAs, AlGaP / GaP, AlGaSb / Ga
Sb or the like can also be used. On the other hand, InGaAs / GaAs and InAlA, which have a relatively large difference in lattice constant,
You may use s / InAs, InGaSb / InSb, etc. In the case of these superlattice layers, dislocations due to lattice mismatch should not occur, and the film thickness and composition ratio should be carefully formed so as not to be equivalent to the case where macroscopically no superlattice layer is formed. I have to.

These impurity diffusion preventing layers 13 function as diffusion preventing layers for hydrogen radicals, which are impurities, and can effectively prevent the formation of strong bonds between Si _{Ga and} H in the channel. The heat treatment does not inactivate the donor.

Next, a method of manufacturing the In _y Ga _1-y As layer will be described with reference to FIG. 4 as an example. The same applies when the impurity diffusion preventing layer 13 is provided. The compound semiconductor layers 2 to 8 are metal organic chemical vapor deposition (MOCVD method) in which the silicon substrate 1 is placed on a carbon susceptor, and the organic metal material is decomposed by heating to react with other organic metal material constituent elements at high temperature. Is formed by.

That is, by the MOCVD method, the surface orientation is (100) or a resistivity 1 with an off angle of several degrees is 1
The high resistance Si substrate 1 of 0 ² to 10 ³ Ωcm is set to 900 to 95
After heat treatment at 0 ° C, the temperature is lowered to 400 to 450 ° C and kept, and GaAs is grown to 100 to 200Å and 650
Undoped GaAs layer 2, undoped A
lAs layer 3, undoped GaAs layer 4, undoped In
_{The y-} Ga _1-y As layer 5 and the undoped GaAs layer 6 are stacked in this order to form buffer layers 2 to 6. This buffer layer 2
An n-GaAs active layer 7 having a carrier density of about 1 to 5 × 10 ¹⁷ cm ⁻³ is formed on the layers 6 to 6. This active layer 7 functions as a channel of MESFET. Further, an n ⁺ -GaAs contact layer 8 is formed on this.

When the compound semiconductor layers 2 to 8 are thus formed on the silicon substrate 1, arsenic diffuses to the silicon substrate 1 side at the interface between the silicon substrate 1 and the compound semiconductor layers 2 to 8, and the compound semiconductor layer 2 side. Silicon diffuses into the. The low resistance layers 1a and 2a are formed by such mutual diffusion.

However, according to the following
By oxidizing the As layer 3, the low resistance layers 1a, 2
a can be such that it does not affect the electrical properties of the device.

First, Si having a thickness of about 0.3 μm
An insulating film 9 made of O ₂ is formed on the entire surface by a CVD method or a sputtering method (see FIG. 4B).

A photoresist opening pattern (not shown) is formed in a portion other than the region where the element is formed, and the SiO ₂ film 9 is etched with buffer hydrofluoric acid (FIG. 4C).
reference). The CDE method or the RIE method may be used.

The compound semiconductor layers 3 to 8 are etched until the AlAs layer 3 is completely etched using a mixed solution of phosphoric acid, hydrogen peroxide and water as an etchant, and then the resist (not shown) is removed. The etching depth may be deeper.

Wet oxidation of the AlAs layer 3 is performed. First, the substrate 1 was placed in a quartz tube heating furnace, 6 liters / minute of nitrogen gas was bubbled into ultrapure water in a constant temperature bath at 95 ° C., and steam was supplied into the tube furnace for 30 minutes at 450 ° C. Oxidize for 40 minutes. In such wet oxidation, AlA
Since the s-layer 3 was formed to 500 Å or more, A
Oxidation of the 1As layer 3 proceeds in parallel with the substrate 1, and unnecessary diffusion can be made relatively small. In this way, the AlAs layer 3 is oxidized over almost the entire area where the device is formed, so that 10 ¹¹ Ωc
The resistivity is equal to or higher than m, and the compound semiconductor layers 4 to 8 which are higher than the resistivity are substantially electrically isolated from the substrate 1. The oxidation time may be appropriately adjusted depending on the size of one element. By such heat treatment, the InGaAs layer 5 serves as a layer for preventing diffusion of impurities, and therefore the channel layer 7 is not deteriorated. In addition, GaAs is not oxidized.

A photoresist opening pattern (not shown) for forming the gate electrode 12 is formed and isotropic etching is performed using buffer hydrofluoric acid to form the SiO ₂ film 9.
Is etched to enlarge the opening, and the contact layer 8 and, if necessary, part of the active layer 7 are formed by using the SiO ₂ film 9 as a mask and using a mixed solution of phosphoric acid, hydrogen peroxide and water as an etchant. Etching is performed to form a recess area (see FIG. 1).

Ti is formed on the gate portion by the vapor deposition method and the lift-off method.
A gate electrode 12 made of / Al or the like is formed. After forming an opening pattern for forming an ohmic electrode on the ohmic contact layer 8 and etching the SiO ₂ film 9 with buffer hydrofluoric acid, an ohmic electrode 10 made of AuGe / Au or AuGe / Ni / Au is formed on the ohmic contact layer 8. , 11 are vapor-deposited, lift-off and heat-treated to alloy.

Although the MESFET has been described as an example in the above embodiment, the deterioration of the electron supply capability of the electron supply layer can be prevented even in the HEMT. Needless to say, the same effect can be obtained for other electronic devices.

[0035]

As described above, according to the field effect transistor of the _{first aspect} , Al _x Ga _{1-x is} contained in the buffer layer.
Since an oxide film of As (0.9 ≦ x ≦ 1) is provided and an impurity diffusion prevention layer having an electron affinity higher than that of the channel layer is provided between the oxide film and the channel layer, the silicon substrate and the compound are prevented. It is effective not to be affected by the low resistance layer formed at the interface with the semiconductor film, to prevent the diffusion of impurities such as hydrogen radicals, and to form a strong bond between Si _{Ga and} H in the channel. Can be prevented. Therefore,
It is possible to significantly increase the mutual conductance as compared with the conventional example.

According to the field effect transistor of the third aspect, Al _x Ga _1-x As (0.
An impurity diffusion prevention layer formed by providing an oxide film of 9 ≦ x ≦ 1) and alternately laminating one or more pairs of two or more kinds of compound semiconductor layers having different electron affinities between the oxide film and the channel layer. With the provision of the above structure, there is no influence of the low resistance layer formed at the interface between the silicon substrate and the compound semiconductor film, diffusion of impurities such as hydrogen radicals can be prevented, and Si _Ga- H It is possible to effectively prevent the formation of strong bonds. Therefore, it is possible to significantly increase the mutual conductance as compared with the conventional example.

Further, according to the method of manufacturing a field effect transistor according to claim 5, a buffer layer and a channel including an Al _x Ga _1-x As layer (0.9 ≦ x ≦ 1) of 500 Å or more on a silicon substrate. After forming the layer, an insulating film is formed in the region where the element is formed, and Al _x Ga is formed in the other region.
After etching to _1-x As layer (0.9 ≦ x ≦ 1),
Since the remaining Al _x Ga _1-x As layer (0.9 ≦ x ≦ 1) is wet-oxidized, even if the Al _x Ga _1-x As layer (0.9 ≦ x ≦ 1) is heat-treated, the channel It is possible to prevent the donor in the layer from being deactivated, and it is possible to form a field effect transistor having a significantly increased transconductance as compared with the conventional example.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a field effect transistor according to claim 1.

FIG. 2 is a sectional view showing an embodiment of a field effect transistor according to claim 2;

FIG. 3 is a diagram illustrating a relationship between a lattice constant of a compound semiconductor and an electron affinity.

FIG. 4 is a cross-sectional view showing an embodiment of a method of manufacturing a field effect transistor according to claim 3.

[Explanation of symbols]

1 ... Silicon substrate, 2, 4, 6 ... GaAs layer,
3 ... AlAs oxide film, 5 ... Impurity diffusion prevention layer, 7 ... Channel layer, 8 ... Contact layer, 9 ...
・ ・ ・ SiO ₂ film, 10, 11 ・ ・ ・ Source / drain electrodes, 12 ・ ・ ・ Gate electrodes

Continuation of front page (56) References JP-A-6-208963 (JP, A) JP-A-11-312692 (JP, A) C.I. B. Whwlwr et. a. , Selectively Oxidized GaAs MESFET's Transferred to a Si Substrate, IEEE Electron Device Letters, USA, April 1997, Vol. 18, No. 4, p. 138-140 A. R. Massengale et. al. , Collector-up AlGaAs / GaAs HBTs Using Oxidized Al As, Device Research Conference, 1996. Dige st. 54th Annual, June 1996, p. 36-37 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/812

Claims (5)

(57) [Claims] 1. In a field effect transistor in which a buffer layer made of a compound semiconductor and a channel layer are laminated on a silicon substrate and a gate electrode is formed on the channel layer, Al _x Ga ₁ is formed in the buffer layer. _-x A
An electric field characterized in that an oxide film of s (0.9 ≦ x ≦ 1) is provided, and an impurity diffusion preventing layer having an electron affinity larger than that of the channel layer is provided between the oxide film and the channel layer. Effect transistor. 2. The impurity diffusion preventing layer is In _y Ga _1-y
The field effect transistor according to claim 1, wherein the field effect transistor is made of As. 3. A field effect transistor comprising a buffer layer and a channel layer made of a compound semiconductor laminated on a silicon substrate and having a gate electrode formed on the channel layer, wherein Al _x Ga _{1 is} contained in the buffer layer. _-x A
An oxide film of s (0.9 ≦ x ≦ 1) is provided, and one or more pairs of compound semiconductor layers having different electron affinities are alternately laminated between the oxide film and the channel layer. A field effect transistor comprising the impurity diffusion prevention layer described above. 4. The field effect transistor according to claim 3, wherein the impurity diffusion prevention layer is composed of alternating layers of AlGaAs and GaAs. 5. A method for manufacturing a field effect transistor, comprising: forming a buffer layer made of a compound semiconductor and a channel layer on a silicon substrate, and forming a gate electrode on the channel layer;
Å After forming the buffer layer and the channel layer including the Al _x Ga _1-x As layer (0.9 ≦ x ≦ 1) or more, an insulating film is formed on the region where the transistor is formed, and the other layers are formed. After the region is etched to the Al _x Ga _1-x As layer (0.9 ≦ x ≦ 1), the remaining Al _x Ga _1-x As is removed.
A method of manufacturing a field effect transistor, which comprises wet-oxidizing a layer (0.9 ≦ x ≦ 1).