JP3582338B2 - Switching unit, power supply and electronic equipment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a switching unit, a power supply, and an electronic device that can increase charging efficiency.
[0002]
[Prior art]
As a rectifier circuit for charging a capacitor or a battery with AC electromotive force generated by a generator, a bridge-type rectifier circuit using switch means such as a transistor is known. In this bridge-type rectifier circuit, the switch means is turned on / off according to the power generation state of the generator in order to increase the efficiency of rectification.
Here, FIG. 8 is a circuit diagram showing a configuration example of this type of charging circuit. In the figure, AG is an AC generator, which generates electric power according to the movement of the wristwatch. Here, FIG. 9 is a perspective view showing the configuration of the AC generator AG and its peripheral mechanism. As shown in the drawing, the AC generator AG includes a rotor 14 and a stator 15. When the rotor 14 in the form of a bipolar magnetized disk rotates, an electromotive force is generated in an output coil 16 of the stator 15, and an AC output is generated. Can be taken out. In the figure, reference numeral 13 denotes a rotating weight that makes a turning motion in the wristwatch main body case, and 11 denotes a wheel train mechanism that transmits the rotating motion of the rotating weight 13 to the generator AG. The oscillating weight 13 rotates according to the swing of the arm of the person wearing the wristwatch, and accordingly, an electromotive force can be obtained from the AC generator AG.
[0003]
The alternating current output from the AC generator AG is rectified by the charging circuit 24 and supplied to the large-capacity capacitor 5 and the processing device 9. The processing device 9 drives the timepiece device 7 with the electric power discharged from the large-capacity capacitor 5.
[0004]
Next, the charging circuit 24 will be described with reference to FIG. In this figure, the NMOS transistor N1 is ON / OFF controlled by a comparator COM3, and the two constitute a unidirectional unit 1 for switching a current in one direction. Similarly, 2 is a unidirectional unit composed of a PMOS transistor P1 and a comparator COM1, 3 is a unidirectional unit composed of an NMOS transistor N2 and a comparator COM4, and 4 is composed of a PMOS transistor P2 and a comparator COM2. It is a unidirectional unit. Unidirectional units 1 and 2 are connected in series from ground to the positive power supply, and similarly, unidirectional units 3 and 4 are connected in series from ground to the positive power supply. An AC generator AG is connected between a connection point between the unidirectional units 1 and 2 and a connection point between the unidirectional units 3 and 4. As described above, the one-way units 1 to 4 constitute a bridge circuit.
[0005]
In the above configuration, the comparator COM1 compares the potential of the output terminal AG1 of the generator AG with the positive power supply Vdd, and the comparator COM2 compares the potential of the output terminal AG2 of the generator AG with the positive power supply Vdd. The comparator COM3 compares the potential of the output terminal AG2 with the ground potential, and the comparator COM4 compares the potential of the output terminal AG1 with the ground potential.
In the configuration described above, when an electromotive force is generated in the AC generator AG and, for example, the terminal AG1 has a positive potential with respect to the ground, the output signal of the comparator COM4 becomes H level and the NMOS transistor N2 is turned on. Next, when the voltage value of the output terminal AG1 of the AC generator AG exceeds the terminal voltage Vdd of the large-capacity capacitor 5, the output signal of the comparator COM1 becomes L level, and the PMOS transistor P1 is turned on. As a result, a charging current path is formed as shown by an arrow in the figure, and the charging current flows through a path including the one-way unit 3, the AC generator AG, the one-way unit 2, and the large-capacity capacitor 5.
Then, when the potential of the terminal AG1 falls below Vdd, the output signal of the comparator COM1 becomes H level, and the PMOS transistor P1 is turned off. As a result, the above-described charging path is interrupted. If the PMOS transistor P1 remains on even when the potential of the terminal AG1 falls below Vdd, the discharge current from the large-capacity capacitor 5 flows backward and the charging efficiency deteriorates, so that when the potential of the terminal AG1 exceeds Vdd. Only a charging path is formed.
On the other hand, when the electromotive force in the opposite direction is output from the AC generator AG and becomes positive with respect to the ground potential from the terminal AG2, the output signal of the comparator COM3 becomes H level, and the NMOS transistor N2 is turned on. When the potential of the terminal AG2 exceeds the terminal voltage Vdd of the large-capacity capacitor 5, the output signal of the comparator COM2 becomes L level, and the PMOS transistor P2 is turned on. As a result, a charging current flows through a path including the one-way unit 1, the AC generator AG, the one-way unit 4, and the large-capacity capacitor 5. Then, when the potential of the terminal AG2 becomes lower than Vdd, the output signal of the comparator COM2 becomes H level, and the PMOS transistor P2 is turned off. As a result, the above-described charging path is interrupted.
As described above, the rectification operation by the one-way units 2 and 3 and the one-way units 1 and 4 is alternately repeated, and the large-capacity capacitor 5 is charged.
[0006]
[Problems to be solved by the invention]
By the way, in the case of a unidirectional unit (for example, the unidirectional units 2 and 4 in FIG. 8) in which a voltage between both ends of a diode (including a parasitic diode) is compared by a comparator, the drain and the source of a MOS transistor which is a switch means Designing the conduction resistance (on-resistance) between them to be as small as possible can be considered as a method of reducing the loss of the charging path and improving the charging efficiency. However, since the on-resistance is low, the conduction current is particularly low. Is smaller, the voltage between the source and the drain becomes lower, becomes lower than the threshold value of the comparator (COM1 or COM2), and the switch means is turned off. When the switch is turned off, the potential difference at the input terminal of the comparator increases due to the forward voltage drop of the diode, and the switch is turned on again. As described above, when the low current is conducted, a phenomenon occurs in which the on / off of the switch unit is frequently repeated.
[0007]
For this reason, the drive current consumption of the switch means becomes larger than the minute charging current, and the energy efficiency is reversed.
For example, FIGS. 10 (a), (b), and (c) show the voltage, the charging current, and the control current of the terminal AG1 of the circuit shown in FIG. 8, respectively. In the period Ts, it can be seen that the switching means repeats on / off and the control current increases. When the control current increases in this way, the control current becomes larger than the charging current, and the energy balance is reversed.
[0008]
The above phenomenon also appears, for example, when a pulse-like chopper charging current is generated when charging is performed by a chopper method.
The present invention has been made in view of the above circumstances, and for example, a switching unit, a power supply device and a switching unit capable of improving an energy balance when switching is performed by using a switching means such as a MOS transistor and improving charging efficiency. It is intended to provide electronic equipment.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, in the switching unit according to the first aspect, a first switching unit and a second switching unit connected in parallel to the first switching unit and having an ON resistance larger than that of the first switching unit. 2 switch means and the first and second switch means connected in parallel. Controlling on / off of the first and second switch means based on the voltage between both ends; The voltage at both ends is the specified value that's all When the first and second switch means are Control to turn on A first control unit for performing the off-control for forcibly turning off the first switch unit in preference to the first control unit for a predetermined time after the voltage between both ends exceeds the predetermined value. Means.
Further, in the switching unit according to the second aspect, the first switching means and the second switching means connected in parallel to the first switching means and having an on-resistance larger than that of the first switching means are connected in parallel. Of the first and second switch means connected Controlling on / off of the first and second switch means based on the voltage between both ends; The voltage at both ends is the specified value that's all When the first and second switch means are Control to turn on First control means for performing the operation, and off control means for forcibly turning off the first switch means in preference to the first control means until the voltage between both ends exceeds the predetermined value by a predetermined amount. Characterized by having
Further, in the switching unit according to the third aspect, the first switching means and the second switching means connected in parallel to the first switching means and having an ON resistance larger than that of the first switching means are connected in parallel. Of the first and second switch means connected Controlling on / off of the first and second switch means based on the voltage between both ends; The voltage at both ends is the specified value that's all When the first and second switch means are Control to turn on A first control unit that determines whether or not the voltage between both ends exceeds the predetermined value at predetermined intervals, and when the voltage exceeds the predetermined value, gives priority to the first control unit in the period, and A switching unit for forcibly turning off the first switch unit.
According to a fourth aspect of the present invention, in the switching unit, a diode connected in parallel to the first and second switch means in the same direction is provided.
Further, in the switching unit according to the fifth aspect, the first and second switch means are constituted by MOS transistors, and the diode is a parasitic diode of the MOS transistor.
Further, in the power supply device according to claim 6, the switching unit according to any one of claims 1 to 5 is interposed between the power generation unit and the charging unit, and the terminal voltage of the power generation unit and the charging unit of the charging unit. The terminal voltage is applied to both ends of the first and second switch means, and the first and second switch means constitute a charging path from the power generation means to the charging means. It is characterized by the following.
Further, in the power supply device according to claim 7, the power generation means is an AC generator.
Further, in the power supply device according to claim 8, the power generation means is a solar cell.
According to a ninth aspect of the present invention, there is provided an electronic apparatus including an electronic device that receives power supply from the power supply device according to any one of the sixth to eighth aspects.
An electronic apparatus according to a tenth aspect is characterized in that the electronic device is an electronic timepiece.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
A: Configuration of the embodiment
FIG. 1 is a circuit diagram showing a configuration of one embodiment of the present invention. This embodiment is an embodiment in which the present invention is applied to an electronic wristwatch. Parts corresponding to those in FIGS. 8 and 9 described above are denoted by the same reference numerals, and description thereof is omitted.
[0011]
In FIG. 1, P1L is a PMOS transistor (switch means) having a low on-resistance, and its source and drain are commonly connected to a PMOS transistor P1S (switch means) having a high on-resistance. That is, the current paths are connected in parallel. Also, P2L has an on-resistance small The source and the drain of the PMOS transistor (switch means), which is a PMOS transistor (switch means) and have a large on-resistance, are commonly connected. That is, the respective current paths are connected in parallel as described above.
[0012]
NAN is a NAND gate that outputs an inverted signal of the logical product of the output signals of the comparators COM1 and COM2. Output signal φT of NAND gate NAN is output to mask pulse generation circuit 20. The mask pulse generation circuit 20 includes a latch circuit 22 and a timer circuit 21 as shown in FIG. 2, and generates a mask signal φT1 from the signal φT and the clock signal CLK. Here, the timer circuit 21 is constituted by a retrigger type counter, and starts counting from the count value “0” every time the signal φT1 rises to the H level. When a predetermined count value is reached, timer circuit 21 sets count-up signal φT2 to L level.
[0013]
Next, the latch circuit 22 is a circuit that latches the signal φT. When the signal φT rises to the H level in the latch circuit 22, the signal φT1 which is the output signal of the latch circuit 22 goes to the H level. Thereby, the timer circuit 21 is reset and starts counting. When the count reaches a predetermined value, the timer circuit 21 outputs a signal φT2 indicating a count-up, whereby the latch circuit 22 is reset. As described above, the timer circuit 21 has a function of passing a predetermined time after the rise of the signal φT, and the signal φT1 goes to the H level only for the predetermined time.
In the present embodiment, an operation clock signal of a clock is used as the clock signal CLK.
[0014]
Next, OR1 shown in FIG. 1 is an OR gate that takes the logical sum of the output signal φP1S of the comparator COM1 and the signal φT1, and OR2 is the OR gate that takes the logical sum of the output signal φP2S of the comparator COM2 and the signal φT1.
[0015]
B: Operation of the embodiment
Next, the operation of this embodiment with the above-described configuration will be described. Here, a case where an electromotive force is generated from the AC generator AG and the voltage of the terminal AG1 is output with a waveform as shown in FIG. Before time t1 shown in FIG. 3, it is assumed that the output signal φP1S of the comparator COM1 is at the H level and the PMOS transistors P1S and P1L are off.
[0016]
Now, the voltage of the terminal AG1 starts to increase from time t1 in FIG. 3A, and when it reaches Vdd at time t2, the output signal φP1S of the comparator COM1 goes to L level, and the PMOS transistors P1S and P1L are turned on. . At this time, since the output signal of the comparator COM4 also goes to the H level, the NMOS transistor N2 is also turned on, and a charging path to the large-capacity capacitor 5 is formed.
[0017]
When signal φP1S goes low, output signal φT of NAND gate NAN goes high, so that output signal φT1 of latch circuit 22 shown in FIG. 2 goes high and timer circuit 21 starts counting. . When the signal φT1 goes high, the output signal φP1L of the OR gate OR1 goes high, and the PMOS transistor P1L having a small on-resistance is turned off. As a result, the switch means forming the charging path is the PMOS transistor P1S and the NMOS transistor N2, and the comparator COM1 compares the voltage between the source and the drain of only the PMOS transistor P1S. In this case, since the ON resistance of the PMOS transistor P1S is large, the voltage between both ends thereof does not fall below the threshold value of the comparator COM1 even when the electromotive force of the AC generator AG is small, and the PMOS transistor P1S maintains the ON state. .
[0018]
Then, when the timer circuit 21 counts up at time t3, the output signal φT1 of the latch circuit 22 goes low, and the PMOS transistor P1L is turned on. At this time, as shown in FIG. 3A, the voltage of the terminal AG1 is also large, and even if the PMOS transistor P1L is turned on, the voltage between the source and the drain of the PMOS transistors P1S and P1L is not changed by the comparator. It does not fall below the threshold. In this embodiment, the time from the start of counting by the timer 21 to the count-up is set on the assumption that a predetermined amount of voltage increase can be obtained after the voltage of the terminal AG1 exceeds Vdd.
[0019]
Further, the voltage at the terminal AG1 is relatively high after time t3 in FIG. 3, but becomes a voltage value close to Vdd at time t4. As a result, the voltage between the source and the drain of the PMOS transistors P1S and P1L falls below the threshold value of the comparator COM1. At this time, when φP1S once becomes H level and the PMOS transistors P1S and P1L are turned off, the source-drain voltages of the PMOS transistors P1S and P1L rise and fall to L level again. Thereby, the output signal φT of the NAND gate NAN also goes low once and then goes high, the output signal φT1 of the latch circuit 22 shown in FIG. 2 goes high, and the timer circuit 21 starts counting. . That is, the signal φT1 is at the H level for a predetermined period, the output signal φP1L of the OR gate OR1 is at the H level, and the PMOS transistor P1L having a small on-resistance is turned off. Therefore, in the same manner as described above, the comparator COM1 compares the source potential and the drain potential of only the PMOS transistor P1S having a large on-resistance. As a result, even if the electromotive force of the AC generator AG is weak, the output signal of the comparator COM1 is not inverted, and the PMOS transistor P1S maintains the ON state.
[0020]
Then, at time t5, when the voltage of the terminal AG1 falls below Vdd, the output signal φP1S of the comparator COM1 goes high, and the PMOS transistor P1S is turned off. Since the signal φP1S is also supplied to the gate of the PMOS transistor P1L via the OR gate OR1, the PMOS transistor P1L is also turned off regardless of the value of the signal φT1.
[0021]
As described above, in the present embodiment, even when the current is low, the PMOS transistors P1S, P1L, P2S, and P2L do not repeatedly turn on / off, so that the occurrence of surge can be prevented and the drive current increases. Can be suppressed.
When the terminal AG1 becomes negative with respect to the ground and the terminal AG2 becomes positive with respect to the ground, the PMOS transistors P2S and P2L and the comparator COM2 perform the same operation as described above.
Here, FIGS. 4 (a), 4 (b) and 4 (c) show the voltage of the terminal AG1, the charging current and the control current, and a surge occurs even in the small section Ts of the charging current shown in FIG. 4 (b). It can be seen that the control current was suppressed. The difference is clear when compared with FIG.
[0022]
C: Modified example
The application range of the present invention is not limited to the above-described embodiment, and for example, the following various modifications are possible.
(1) Although the above-described embodiment is an example in which the present invention is applied to a rectifier circuit of an AC generator, the present invention can also be applied to a DC power supply. Hereinafter, such an application example will be described.
FIG. 5 is an example of a charging circuit using a solar cell as a power supply. In this figure, an outline of an electronic device 40 for operating a processing device 39 such as a clock device by a solar cell B is shown. The electronic device 40 includes a power supply device 50 for supplying DC power from the solar cell B to the large-capacity capacitor 5 as a charging device and the processing device 39. The power supply device 50 includes an input terminal 21 connected to the solar cell B, a first output terminal 22 connected to the large-capacity capacitor 5, and a second output terminal 23 connected to the processing device 39. It has. A start-up resistor 28 is connected to the second output terminal 23 in series with the first output terminal 22, that is, the large-capacity capacitor 5, and a bypass switch 51 is connected in parallel with the resistor 28. Accordingly, when the charge level of the large-capacity capacitor 5 is low, the output terminal 23 connected to the processing device 39 by the start-up resistor 28 in order to prevent power from being mainly consumed by the large-capacity capacitor 5. A sufficient voltage is generated. When a certain voltage is generated in the large-capacity capacitor 5, the startup resistor 28 is bypassed by the bypass switch 51, and the large-capacity capacitor 5 can be charged efficiently.
[0023]
An auxiliary capacitor 8 is connected in parallel to the processing device 39 of this example for stabilizing the operating voltage. Further, a short-circuit switch 52 is connected in parallel with the input terminal 21 of the power supply device 50, and the input voltage V0 from the solar cell B becomes too high and adversely affects the processing device 39 and the large-capacity capacitor 5. , The input from the solar cell B is short-circuited to prevent the output voltage V1 from becoming too high. In order to perform such control, the power supply device 50 includes a control circuit 37. The control circuit 37 monitors the input voltage V0 and the output voltage V1 on the output terminal 23 side of the large-capacity capacitor 5, and monitors the short-circuit voltage. The switch 52 and the bypass switch 51 can be operated.
[0024]
In the power supply device 40, when the output of the solar cell B that converts discontinuous light energy into electric power decreases, the electric power discharged from the large-capacity capacitor 5 is supplied from the output terminal 22 to the output terminal 23, and the processing device 39 Driven. At this time, when a current flows from the large-capacity capacitor 5 to the solar cell B, power is wasted and the solar cell B may be damaged. For this reason, the power supply device 50 is provided with a unidirectional unit 31 for preventing backflow from the large-capacity capacitor 5 to the solar cell B.
[0025]
In the one-way unit 31 of the present example, a current flows when the electromotive voltage V0 of the solar cell B supplied to the input terminal 21 is larger in absolute value than the voltage V1 of the output terminal 22 connected to the large-capacity capacitor 5. And a switch 38 connected in parallel with the diode 35. The switch 38 is operated by a control signal φ1 from a control circuit 37. FIG. 6 shows an example of the control signal φ1. The input voltage V0 of the input terminal 21 and the output voltage V1 of the output terminal 22 are input to the control circuit 37, and these voltages V0 and V1 correspond to voltages across the diode 35. First, at time t1, when the solar cell B does not generate power and no charge is accumulated in the large-capacity capacitor 5, the input voltage V0 and the output voltage V1 are 0, and the difference between them is also 0. . Therefore, the control signal φ1 is held at a low level, and the switch 38 is off. In order to turn off when a control power supply cannot be secured, for example, a field effect transistor switch such as an enhancement type MOSFET can be used.
[0026]
Next, when the solar cell B starts power generation at time t2, the input voltage V0 increases (to the negative side). Therefore, a current flows through the diode 35, and a forward voltage Vf is generated. Therefore, the voltage V1 at the other end of the diode 35 becomes smaller than the input voltage V0 on the plus side. The control circuit 37 detects this potential difference and sets the control signal φ1 to high level at time t3 to turn on the switch 38. As a result, the electric power from the solar cell B flows bypassing the diode 35 and is supplied to the large-capacity capacitor 5 and the processing circuit 39 without loss of the forward voltage Vf.
[0027]
The switch 38 shown in FIG. 5 has a large on-resistance, and the switch 41 has a small on-resistance. AND is an AND gate, whose output signal controls ON / OFF of the switch 41.
[0028]
FIG. 7 is a block diagram showing a configuration of the control circuit 37. As shown in FIG. 7, the control circuit 37 has a mask pulse generation circuit 20, a comparator COM6, and an inverter 60. The mask pulse generating circuit 20 performs the same operation as that shown in FIG. The comparator COM6 compares the voltages V0 and V1, and outputs the result of the comparison as a signal φ1. The signal φ1 supplied to the mask pulse generation circuit 20 functions in the same manner as the signal φT described above.
[0029]
According to the above configuration, immediately after the voltage V0 exceeds the voltage V1, the ON resistance of the switch 38 is small, so that the potential difference between the two drops below the threshold value of the comparator COM6, and the switch 41 frequently switches on / off. However, in this example, the signal φT1 (however, the inverted signal) is controlled by the operation of the mask pulse circuit 20, so that the switch is switched while the potential difference between the voltages V0 and V1 is small. 41 is controlled to be turned off. Therefore, in such a situation, only the switch 38 having a large on-resistance is turned on, and no surge occurs as in the above-described embodiment, and the control current is suppressed.
[0030]
(2) Although the above embodiment is an example of an electronic wristwatch, a circuit or the like having another function may be incorporated. For example, a circuit having a radio, a pager, a computer function, or a circuit having a pedometer, a sphygmomanometer, and a mobile phone function may be provided.
[0031]
(3) A voltage comparison circuit may be provided instead of the timer circuit 21 in the above-described embodiment. That is, when comparing the two voltages, the timer circuit 21 pays attention to the fact that even if one exceeds the other, it initially only slightly exceeds it, and measures the time until it exceeds the predetermined amount. Therefore, a voltage difference detection circuit for directly detecting the difference between the two voltages may be provided, and the on / off of the switch means may be controlled depending on whether or not the detected voltage difference exceeds a predetermined amount.
[0032]
Further, a circuit configuration as shown in FIG. 11 may be adopted. In the signals shown in this figure, those having the same functions as those in FIG. 2 are denoted by the same reference numerals.
In FIG. 11, 90 is a latch circuit, 91 is a T-FF (toggle flip-flop), and NOR is a NOR gate. In the circuit shown in this figure, when the signal φT rises, the mask pulse φT1 is output until the next falling edge of the clock signal CLK. Therefore, when φT rises to the H level again after outputting the mask pulse φT1, the mask pulse φT1 is output again in the same manner.
That is, in the circuit shown in FIG. 11, if the rising of the signal φT is detected in one cycle of the clock signal CLK as a unit as shown in FIG. An operation of outputting φT1 is performed.
According to such a configuration, even when the time required for the output voltage of the generator to sufficiently exceed the charging voltage of the large-capacity capacitor 5 cannot be predicted, each time the former exceeds the latter, the mask is required. Since the pulse φT1 is output, generation of a surge current can be suppressed.
[0033]
(4) Power storage means such as a battery may be used instead of the large-capacity capacitor 5. The AC generator AG is not limited to the one described in the present embodiment, and another AC generator may be used.
[0034]
(5) The above-described embodiment is an example in which a unidirectional unit (a unit that allows current to flow in one direction) is configured using a parasitic diode of a MOS transistor. However, a diode is separately used without using a parasitic diode. May be used. Further, the present invention is not limited to a unidirectional unit, but can be applied to a switch unit that allows current to flow in both directions.
[0035]
(6) The generator to which the present invention is applied is not limited to the one described above. That is, a chopper configuration may be used. In this case, a booster circuit can be connected before the large-capacity capacitor 5, and a spring-powered generator can be used as the generator. In the case of a chopper configuration, for example, a configuration in which the output signals of the comparators COM3 and COM4 shown in FIG. 1 are choppered (for example, a configuration in which an OR circuit that takes the logical sum of the output of these comparators and a clock signal) is provided. It may be provided.
[0036]
Here, FIG. 13 is a perspective view showing the mechanical structure of an electronically controlled mechanical timepiece provided with a mainspring generator. In this wristwatch, the mainspring 110 is connected to a crown (not shown), and winding the crown stores mechanical energy in the mainspring 110. A speed increasing gear train 120 is provided between the mainspring 110 and the rotor 131 of the generator 130. The speed increasing gear train 120 includes a second wheel & pinion 121 to which the minute hand 124 is fixed, a third wheel & pinion 122, and a fourth wheel & pinion 123 to which the second hand 125 is fixed. Then, the movement of the mainspring 110 is transmitted to the rotor 131 of the generator 130 by the speed increasing train train 120, so that power generation is performed. Here, the generator 130 also functions as an electromagnetic brake, and rotates a pointer fixed to the speed increasing train 120 at a constant speed. In this sense, the generator 130 also functions as a governor.
[0037]
Next, FIG. 14 is a block diagram showing an electrical configuration of the electronically controlled mechanical timepiece. In the figure, the chopper circuit 200 includes a generator 130 and a rectifier circuit 140. The electromotive voltage of the generator 130 is rectified by the rectifier circuit 140 and the capacitor 150 is charged. Here, as described above, the rectifier circuit 140 uses a circuit obtained by modifying the circuit of the present embodiment into a chopper configuration, and the generator 130 is used in place of the AC generator AG.
[0038]
The capacitor 150 supplies power to the chopper circuit 200, the speed control circuit 170, and the oscillation circuit 160. The oscillation circuit 160 generates the clock signal CLK using the crystal oscillator 161. In the speed control circuit 170, when the detection circuit 102 detects the power generation frequency of the generator 130, the control circuit 103 controls the electromagnetic brake based on the detection result so that the rotation cycle of the rotor 131 matches the cycle of the clock signal CLK. Is adjusted to control the rectifier circuit 140 so that the rotation speed of the rotor 131 is constant. In this case, the rectifier circuit 140 is controlled by a control signal generated based on the clock signal CLK.
[0039]
Here, the rotation of the generator 130 is controlled by turning on and off both ends of the coil of the generator 130 with a switch capable of short-circuiting and choppering. This switch corresponds to, for example, the N-channel MOS transistors N1 and N2 (see FIG. 1) in the above-described embodiment. When the switch is turned on by this chopper ring, a short brake is applied to the generator 130 and electric energy is accumulated in the coil of the generator 130. On the other hand, when the switch is turned off, the generator 130 operates to release the electric energy stored in the coil and generate an electromotive voltage. At this time, the electric voltage at the time when the switch is turned off is added to the electromotive voltage, so that the value can be increased. For this reason, when the generator 130 is controlled by choppering, the decrease in the generated power during braking can be compensated for by the increase in the electromotive voltage when the switch is turned off, and the braking torque can be increased while maintaining the generated power at or above a certain level. An electronically controlled mechanical timepiece with a long time can be constructed.
In the above configuration, only when the output voltage of the generator 130 is not sufficiently high, the surge current of the switch means of the rectifier circuit 140 can be prevented by the mask pulse.
[0040]
【The invention's effect】
As described above, according to the present invention, the generation of surge current can be suppressed, and the charging efficiency can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a mask pulse circuit according to the first embodiment.
FIG. 3 is a timing chart for explaining the operation of the embodiment.
FIG. 4 is a waveform chart for explaining a state of occurrence of a surge in the embodiment.
FIG. 5 is a block diagram showing a configuration of a modification of the embodiment.
FIG. 6 is a timing chart for explaining the operation of the modification.
FIG. 7 is a block diagram showing a configuration of a control circuit 37 of the modification.
FIG. 8 is a block diagram showing a configuration of a conventional device.
FIG. 9 is a perspective view showing a configuration of a generator AG shown in FIG.
FIG. 10 is a waveform diagram showing a state of occurrence of a surge in the conventional device shown in FIG.
FIG. 11 is a block diagram showing another modification of the present invention.
FIG. 12 is a waveform chart for explaining an operation of the modification shown in FIG. 11;
FIG. 13 is a perspective view showing an external configuration of a generator portion in another modification of the present invention.
FIG. 14 is a block diagram showing an electrical configuration of a modification shown in FIG.
[Explanation of symbols]
COM1 comparator
COM2 comparator
COM6 comparator
P1S PMOS transistor
P1L PMOS transistor
P2S PMOS transistor
P2L PMOS transistor
OR1, OR2 OR gate
NAN NAND Gate
20 Mask pulse generation circuit
21 Timer circuit
22 Latch circuit
38 switch
41 switch

Claims (10)

First switch means;
A second switch connected in parallel to the first switch and having an on-resistance greater than that of the first switch;
On / off of the first and second switch means is controlled based on the voltage between both ends of the first and second switch means connected in parallel, and when the voltage between both ends becomes a predetermined value or more , the second switch means 1. first control means for controlling the second switch means to be turned on ;
An off-control means for forcibly turning off the first switch means in preference to the first control means for a predetermined time after the voltage between both ends exceeds the predetermined value. And a switching unit. First switch means;
A second switch connected in parallel to the first switch and having an on-resistance greater than that of the first switch;
On / off of the first and second switch means is controlled based on the voltage between both ends of the first and second switch means connected in parallel, and when the voltage between both ends becomes a predetermined value or more , the second switch means 1. first control means for controlling the second switch means to be turned on ;
Switching control means for forcibly turning off the first switch means prior to the first control means until the voltage between both ends exceeds the predetermined value by a predetermined amount. unit. First switch means;
A second switch connected in parallel to the first switch and having an on-resistance greater than that of the first switch;
On / off of the first and second switch means is controlled based on the voltage between both ends of the first and second switch means connected in parallel, and when the voltage between both ends becomes a predetermined value or more , the second switch means 1. first control means for controlling the second switch means to be turned on ;
It is determined at predetermined intervals whether or not the voltage between both ends exceeds the predetermined value, and when the voltage exceeds the predetermined value, the first switch is forcibly activated in the cycle in preference to the first control. A switching unit comprising: an off-control means for turning off. 4. The switching unit according to claim 1, further comprising a diode connected in parallel to said first and second switch means in the same direction. 4. The switching unit according to claim 1, wherein said first and second switch means are constituted by MOS transistors, and said diodes are parasitic diodes of said MOS transistors. The switching unit according to claim 1 is interposed between the power generation means and the charging means, and a terminal voltage of the power generation means and a terminal voltage of the charging means are equal to those of the first and second switch means. A power supply device configured to be applied to both ends, wherein the first and second switch means constitute a charging path from the power generation means to the charging means. The power supply device according to claim 6, wherein the power generation unit is an AC generator. The power supply device according to claim 6, wherein the power generation unit is a solar cell. An electronic apparatus, comprising: an electronic device that receives power supply from the power supply device according to claim 6. The electronic device according to claim 9, wherein the electronic device is an electronic timepiece.

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